1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004-2011 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 #include <fsl_mdio.h> 21 #include <asm/errno.h> 22 #include <asm/processor.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define TX_BUF_CNT 2 27 28 static uint rxIdx; /* index of the current RX buffer */ 29 static uint txIdx; /* index of the current TX buffer */ 30 31 typedef volatile struct rtxbd { 32 txbd8_t txbd[TX_BUF_CNT]; 33 rxbd8_t rxbd[PKTBUFSRX]; 34 } RTXBD; 35 36 #define MAXCONTROLLERS (8) 37 38 static struct tsec_private *privlist[MAXCONTROLLERS]; 39 static int num_tsecs = 0; 40 41 #ifdef __GNUC__ 42 static RTXBD rtx __attribute__ ((aligned(8))); 43 #else 44 #error "rtx must be 64-bit aligned" 45 #endif 46 47 static int tsec_send(struct eth_device *dev, void *packet, int length); 48 49 /* Default initializations for TSEC controllers. */ 50 51 static struct tsec_info_struct tsec_info[] = { 52 #ifdef CONFIG_TSEC1 53 STD_TSEC_INFO(1), /* TSEC1 */ 54 #endif 55 #ifdef CONFIG_TSEC2 56 STD_TSEC_INFO(2), /* TSEC2 */ 57 #endif 58 #ifdef CONFIG_MPC85XX_FEC 59 { 60 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 61 .devname = CONFIG_MPC85XX_FEC_NAME, 62 .phyaddr = FEC_PHY_ADDR, 63 .flags = FEC_FLAGS, 64 .mii_devname = DEFAULT_MII_NAME 65 }, /* FEC */ 66 #endif 67 #ifdef CONFIG_TSEC3 68 STD_TSEC_INFO(3), /* TSEC3 */ 69 #endif 70 #ifdef CONFIG_TSEC4 71 STD_TSEC_INFO(4), /* TSEC4 */ 72 #endif 73 }; 74 75 #define TBIANA_SETTINGS ( \ 76 TBIANA_ASYMMETRIC_PAUSE \ 77 | TBIANA_SYMMETRIC_PAUSE \ 78 | TBIANA_FULL_DUPLEX \ 79 ) 80 81 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ 82 #ifndef CONFIG_TSEC_TBICR_SETTINGS 83 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 84 TBICR_PHY_RESET \ 85 | TBICR_ANEG_ENABLE \ 86 | TBICR_FULL_DUPLEX \ 87 | TBICR_SPEED1_SET \ 88 ) 89 #endif /* CONFIG_TSEC_TBICR_SETTINGS */ 90 91 /* Configure the TBI for SGMII operation */ 92 static void tsec_configure_serdes(struct tsec_private *priv) 93 { 94 /* Access TBI PHY registers at given TSEC register offset as opposed 95 * to the register offset used for external PHY accesses */ 96 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 97 0, TBI_ANA, TBIANA_SETTINGS); 98 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 99 0, TBI_TBICON, TBICON_CLK_SELECT); 100 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 101 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS); 102 } 103 104 #ifdef CONFIG_MCAST_TFTP 105 106 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 107 108 /* Set the appropriate hash bit for the given addr */ 109 110 /* The algorithm works like so: 111 * 1) Take the Destination Address (ie the multicast address), and 112 * do a CRC on it (little endian), and reverse the bits of the 113 * result. 114 * 2) Use the 8 most significant bits as a hash into a 256-entry 115 * table. The table is controlled through 8 32-bit registers: 116 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 117 * gaddr7. This means that the 3 most significant bits in the 118 * hash index which gaddr register to use, and the 5 other bits 119 * indicate which bit (assuming an IBM numbering scheme, which 120 * for PowerPC (tm) is usually the case) in the tregister holds 121 * the entry. */ 122 static int 123 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 124 { 125 struct tsec_private *priv = privlist[1]; 126 volatile tsec_t *regs = priv->regs; 127 volatile u32 *reg_array, value; 128 u8 result, whichbit, whichreg; 129 130 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 131 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 132 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 133 value = (1 << (31-whichbit)); 134 135 reg_array = &(regs->hash.gaddr0); 136 137 if (set) { 138 reg_array[whichreg] |= value; 139 } else { 140 reg_array[whichreg] &= ~value; 141 } 142 return 0; 143 } 144 #endif /* Multicast TFTP ? */ 145 146 /* Initialized required registers to appropriate values, zeroing 147 * those we don't care about (unless zero is bad, in which case, 148 * choose a more appropriate value) 149 */ 150 static void init_registers(tsec_t *regs) 151 { 152 /* Clear IEVENT */ 153 out_be32(®s->ievent, IEVENT_INIT_CLEAR); 154 155 out_be32(®s->imask, IMASK_INIT_CLEAR); 156 157 out_be32(®s->hash.iaddr0, 0); 158 out_be32(®s->hash.iaddr1, 0); 159 out_be32(®s->hash.iaddr2, 0); 160 out_be32(®s->hash.iaddr3, 0); 161 out_be32(®s->hash.iaddr4, 0); 162 out_be32(®s->hash.iaddr5, 0); 163 out_be32(®s->hash.iaddr6, 0); 164 out_be32(®s->hash.iaddr7, 0); 165 166 out_be32(®s->hash.gaddr0, 0); 167 out_be32(®s->hash.gaddr1, 0); 168 out_be32(®s->hash.gaddr2, 0); 169 out_be32(®s->hash.gaddr3, 0); 170 out_be32(®s->hash.gaddr4, 0); 171 out_be32(®s->hash.gaddr5, 0); 172 out_be32(®s->hash.gaddr6, 0); 173 out_be32(®s->hash.gaddr7, 0); 174 175 out_be32(®s->rctrl, 0x00000000); 176 177 /* Init RMON mib registers */ 178 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 179 180 out_be32(®s->rmon.cam1, 0xffffffff); 181 out_be32(®s->rmon.cam2, 0xffffffff); 182 183 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS); 184 185 out_be32(®s->minflr, MINFLR_INIT_SETTINGS); 186 187 out_be32(®s->attr, ATTR_INIT_SETTINGS); 188 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS); 189 190 } 191 192 /* Configure maccfg2 based on negotiated speed and duplex 193 * reported by PHY handling code 194 */ 195 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) 196 { 197 tsec_t *regs = priv->regs; 198 u32 ecntrl, maccfg2; 199 200 if (!phydev->link) { 201 printf("%s: No link.\n", phydev->dev->name); 202 return; 203 } 204 205 /* clear all bits relative with interface mode */ 206 ecntrl = in_be32(®s->ecntrl); 207 ecntrl &= ~ECNTRL_R100; 208 209 maccfg2 = in_be32(®s->maccfg2); 210 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX); 211 212 if (phydev->duplex) 213 maccfg2 |= MACCFG2_FULL_DUPLEX; 214 215 switch (phydev->speed) { 216 case 1000: 217 maccfg2 |= MACCFG2_GMII; 218 break; 219 case 100: 220 case 10: 221 maccfg2 |= MACCFG2_MII; 222 223 /* Set R100 bit in all modes although 224 * it is only used in RGMII mode 225 */ 226 if (phydev->speed == 100) 227 ecntrl |= ECNTRL_R100; 228 break; 229 default: 230 printf("%s: Speed was bad\n", phydev->dev->name); 231 break; 232 } 233 234 out_be32(®s->ecntrl, ecntrl); 235 out_be32(®s->maccfg2, maccfg2); 236 237 printf("Speed: %d, %s duplex%s\n", phydev->speed, 238 (phydev->duplex) ? "full" : "half", 239 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 240 } 241 242 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 243 /* 244 * When MACCFG1[Rx_EN] is enabled during system boot as part 245 * of the eTSEC port initialization sequence, 246 * the eTSEC Rx logic may not be properly initialized. 247 */ 248 void redundant_init(struct eth_device *dev) 249 { 250 struct tsec_private *priv = dev->priv; 251 tsec_t *regs = priv->regs; 252 uint t, count = 0; 253 int fail = 1; 254 static const u8 pkt[] = { 255 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25, 256 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00, 257 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01, 258 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1, 259 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00, 260 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 261 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 262 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 263 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 264 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 265 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 266 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 267 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 268 0x71, 0x72}; 269 270 /* Enable promiscuous mode */ 271 setbits_be32(®s->rctrl, 0x8); 272 /* Enable loopback mode */ 273 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); 274 /* Enable transmit and receive */ 275 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); 276 277 /* Tell the DMA it is clear to go */ 278 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); 279 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 280 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 281 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 282 283 do { 284 tsec_send(dev, (void *)pkt, sizeof(pkt)); 285 286 /* Wait for buffer to be received */ 287 for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) { 288 if (t >= 10 * TOUT_LOOP) { 289 printf("%s: tsec: rx error\n", dev->name); 290 break; 291 } 292 } 293 294 if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt))) 295 fail = 0; 296 297 rtx.rxbd[rxIdx].length = 0; 298 rtx.rxbd[rxIdx].status = 299 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 300 rxIdx = (rxIdx + 1) % PKTBUFSRX; 301 302 if (in_be32(®s->ievent) & IEVENT_BSY) { 303 out_be32(®s->ievent, IEVENT_BSY); 304 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 305 } 306 if (fail) { 307 printf("loopback recv packet error!\n"); 308 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN); 309 udelay(1000); 310 setbits_be32(®s->maccfg1, MACCFG1_RX_EN); 311 } 312 } while ((count++ < 4) && (fail == 1)); 313 314 if (fail) 315 panic("eTSEC init fail!\n"); 316 /* Disable promiscuous mode */ 317 clrbits_be32(®s->rctrl, 0x8); 318 /* Disable loopback mode */ 319 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); 320 } 321 #endif 322 323 /* Set up the buffers and their descriptors, and bring up the 324 * interface 325 */ 326 static void startup_tsec(struct eth_device *dev) 327 { 328 int i; 329 struct tsec_private *priv = (struct tsec_private *)dev->priv; 330 tsec_t *regs = priv->regs; 331 332 /* reset the indices to zero */ 333 rxIdx = 0; 334 txIdx = 0; 335 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 336 uint svr; 337 #endif 338 339 /* Point to the buffer descriptors */ 340 out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx])); 341 out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx])); 342 343 /* Initialize the Rx Buffer descriptors */ 344 for (i = 0; i < PKTBUFSRX; i++) { 345 rtx.rxbd[i].status = RXBD_EMPTY; 346 rtx.rxbd[i].length = 0; 347 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 348 } 349 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 350 351 /* Initialize the TX Buffer Descriptors */ 352 for (i = 0; i < TX_BUF_CNT; i++) { 353 rtx.txbd[i].status = 0; 354 rtx.txbd[i].length = 0; 355 rtx.txbd[i].bufPtr = 0; 356 } 357 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 358 359 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 360 svr = get_svr(); 361 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 362 redundant_init(dev); 363 #endif 364 /* Enable Transmit and Receive */ 365 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); 366 367 /* Tell the DMA it is clear to go */ 368 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); 369 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 370 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 371 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 372 } 373 374 /* This returns the status bits of the device. The return value 375 * is never checked, and this is what the 8260 driver did, so we 376 * do the same. Presumably, this would be zero if there were no 377 * errors 378 */ 379 static int tsec_send(struct eth_device *dev, void *packet, int length) 380 { 381 int i; 382 int result = 0; 383 struct tsec_private *priv = (struct tsec_private *)dev->priv; 384 tsec_t *regs = priv->regs; 385 386 /* Find an empty buffer descriptor */ 387 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 388 if (i >= TOUT_LOOP) { 389 debug("%s: tsec: tx buffers full\n", dev->name); 390 return result; 391 } 392 } 393 394 rtx.txbd[txIdx].bufPtr = (uint) packet; 395 rtx.txbd[txIdx].length = length; 396 rtx.txbd[txIdx].status |= 397 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 398 399 /* Tell the DMA to go */ 400 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 401 402 /* Wait for buffer to be transmitted */ 403 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 404 if (i >= TOUT_LOOP) { 405 debug("%s: tsec: tx error\n", dev->name); 406 return result; 407 } 408 } 409 410 txIdx = (txIdx + 1) % TX_BUF_CNT; 411 result = rtx.txbd[txIdx].status & TXBD_STATS; 412 413 return result; 414 } 415 416 static int tsec_recv(struct eth_device *dev) 417 { 418 int length; 419 struct tsec_private *priv = (struct tsec_private *)dev->priv; 420 tsec_t *regs = priv->regs; 421 422 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 423 424 length = rtx.rxbd[rxIdx].length; 425 426 /* Send the packet up if there were no errors */ 427 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 428 NetReceive(NetRxPackets[rxIdx], length - 4); 429 } else { 430 printf("Got error %x\n", 431 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 432 } 433 434 rtx.rxbd[rxIdx].length = 0; 435 436 /* Set the wrap bit if this is the last element in the list */ 437 rtx.rxbd[rxIdx].status = 438 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 439 440 rxIdx = (rxIdx + 1) % PKTBUFSRX; 441 } 442 443 if (in_be32(®s->ievent) & IEVENT_BSY) { 444 out_be32(®s->ievent, IEVENT_BSY); 445 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 446 } 447 448 return -1; 449 450 } 451 452 /* Stop the interface */ 453 static void tsec_halt(struct eth_device *dev) 454 { 455 struct tsec_private *priv = (struct tsec_private *)dev->priv; 456 tsec_t *regs = priv->regs; 457 458 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 459 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 460 461 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) 462 != (IEVENT_GRSC | IEVENT_GTSC)) 463 ; 464 465 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); 466 467 /* Shut down the PHY, as needed */ 468 phy_shutdown(priv->phydev); 469 } 470 471 /* Initializes data structures and registers for the controller, 472 * and brings the interface up. Returns the link status, meaning 473 * that it returns success if the link is up, failure otherwise. 474 * This allows u-boot to find the first active controller. 475 */ 476 static int tsec_init(struct eth_device *dev, bd_t * bd) 477 { 478 uint tempval; 479 char tmpbuf[MAC_ADDR_LEN]; 480 int i; 481 struct tsec_private *priv = (struct tsec_private *)dev->priv; 482 tsec_t *regs = priv->regs; 483 int ret; 484 485 /* Make sure the controller is stopped */ 486 tsec_halt(dev); 487 488 /* Init MACCFG2. Defaults to GMII */ 489 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS); 490 491 /* Init ECNTRL */ 492 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); 493 494 /* Copy the station address into the address registers. 495 * Backwards, because little endian MACS are dumb */ 496 for (i = 0; i < MAC_ADDR_LEN; i++) 497 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 498 499 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | 500 tmpbuf[3]; 501 502 out_be32(®s->macstnaddr1, tempval); 503 504 tempval = *((uint *) (tmpbuf + 4)); 505 506 out_be32(®s->macstnaddr2, tempval); 507 508 /* Clear out (for the most part) the other registers */ 509 init_registers(regs); 510 511 /* Ready the device for tx/rx */ 512 startup_tsec(dev); 513 514 /* Start up the PHY */ 515 ret = phy_startup(priv->phydev); 516 if (ret) { 517 printf("Could not initialize PHY %s\n", 518 priv->phydev->dev->name); 519 return ret; 520 } 521 522 adjust_link(priv, priv->phydev); 523 524 /* If there's no link, fail */ 525 return priv->phydev->link ? 0 : -1; 526 } 527 528 static phy_interface_t tsec_get_interface(struct tsec_private *priv) 529 { 530 tsec_t *regs = priv->regs; 531 u32 ecntrl; 532 533 ecntrl = in_be32(®s->ecntrl); 534 535 if (ecntrl & ECNTRL_SGMII_MODE) 536 return PHY_INTERFACE_MODE_SGMII; 537 538 if (ecntrl & ECNTRL_TBI_MODE) { 539 if (ecntrl & ECNTRL_REDUCED_MODE) 540 return PHY_INTERFACE_MODE_RTBI; 541 else 542 return PHY_INTERFACE_MODE_TBI; 543 } 544 545 if (ecntrl & ECNTRL_REDUCED_MODE) { 546 if (ecntrl & ECNTRL_REDUCED_MII_MODE) 547 return PHY_INTERFACE_MODE_RMII; 548 else { 549 phy_interface_t interface = priv->interface; 550 551 /* 552 * This isn't autodetected, so it must 553 * be set by the platform code. 554 */ 555 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) || 556 (interface == PHY_INTERFACE_MODE_RGMII_TXID) || 557 (interface == PHY_INTERFACE_MODE_RGMII_RXID)) 558 return interface; 559 560 return PHY_INTERFACE_MODE_RGMII; 561 } 562 } 563 564 if (priv->flags & TSEC_GIGABIT) 565 return PHY_INTERFACE_MODE_GMII; 566 567 return PHY_INTERFACE_MODE_MII; 568 } 569 570 571 /* Discover which PHY is attached to the device, and configure it 572 * properly. If the PHY is not recognized, then return 0 573 * (failure). Otherwise, return 1 574 */ 575 static int init_phy(struct eth_device *dev) 576 { 577 struct tsec_private *priv = (struct tsec_private *)dev->priv; 578 struct phy_device *phydev; 579 tsec_t *regs = priv->regs; 580 u32 supported = (SUPPORTED_10baseT_Half | 581 SUPPORTED_10baseT_Full | 582 SUPPORTED_100baseT_Half | 583 SUPPORTED_100baseT_Full); 584 585 if (priv->flags & TSEC_GIGABIT) 586 supported |= SUPPORTED_1000baseT_Full; 587 588 /* Assign a Physical address to the TBI */ 589 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); 590 591 priv->interface = tsec_get_interface(priv); 592 593 if (priv->interface == PHY_INTERFACE_MODE_SGMII) 594 tsec_configure_serdes(priv); 595 596 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); 597 598 phydev->supported &= supported; 599 phydev->advertising = phydev->supported; 600 601 priv->phydev = phydev; 602 603 phy_config(phydev); 604 605 return 1; 606 } 607 608 /* Initialize device structure. Returns success if PHY 609 * initialization succeeded (i.e. if it recognizes the PHY) 610 */ 611 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) 612 { 613 struct eth_device *dev; 614 int i; 615 struct tsec_private *priv; 616 617 dev = (struct eth_device *)malloc(sizeof *dev); 618 619 if (NULL == dev) 620 return 0; 621 622 memset(dev, 0, sizeof *dev); 623 624 priv = (struct tsec_private *)malloc(sizeof(*priv)); 625 626 if (NULL == priv) 627 return 0; 628 629 privlist[num_tsecs++] = priv; 630 priv->regs = tsec_info->regs; 631 priv->phyregs_sgmii = tsec_info->miiregs_sgmii; 632 633 priv->phyaddr = tsec_info->phyaddr; 634 priv->flags = tsec_info->flags; 635 636 sprintf(dev->name, tsec_info->devname); 637 priv->interface = tsec_info->interface; 638 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); 639 dev->iobase = 0; 640 dev->priv = priv; 641 dev->init = tsec_init; 642 dev->halt = tsec_halt; 643 dev->send = tsec_send; 644 dev->recv = tsec_recv; 645 #ifdef CONFIG_MCAST_TFTP 646 dev->mcast = tsec_mcast_addr; 647 #endif 648 649 /* Tell u-boot to get the addr from the env */ 650 for (i = 0; i < 6; i++) 651 dev->enetaddr[i] = 0; 652 653 eth_register(dev); 654 655 /* Reset the MAC */ 656 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); 657 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ 658 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); 659 660 /* Try to initialize PHY here, and return */ 661 return init_phy(dev); 662 } 663 664 /* 665 * Initialize all the TSEC devices 666 * 667 * Returns the number of TSEC devices that were initialized 668 */ 669 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 670 { 671 int i; 672 int ret, count = 0; 673 674 for (i = 0; i < num; i++) { 675 ret = tsec_initialize(bis, &tsecs[i]); 676 if (ret > 0) 677 count += ret; 678 } 679 680 return count; 681 } 682 683 int tsec_standard_init(bd_t *bis) 684 { 685 struct fsl_pq_mdio_info info; 686 687 info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 688 info.name = DEFAULT_MII_NAME; 689 690 fsl_pq_mdio_init(bis, &info); 691 692 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 693 } 694