1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004-2011 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 #include <fsl_mdio.h> 21 #include <asm/errno.h> 22 #include <asm/processor.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define TX_BUF_CNT 2 27 28 static uint rxIdx; /* index of the current RX buffer */ 29 static uint txIdx; /* index of the current TX buffer */ 30 31 typedef volatile struct rtxbd { 32 txbd8_t txbd[TX_BUF_CNT]; 33 rxbd8_t rxbd[PKTBUFSRX]; 34 } RTXBD; 35 36 #define MAXCONTROLLERS (8) 37 38 static struct tsec_private *privlist[MAXCONTROLLERS]; 39 static int num_tsecs = 0; 40 41 #ifdef __GNUC__ 42 static RTXBD rtx __attribute__ ((aligned(8))); 43 #else 44 #error "rtx must be 64-bit aligned" 45 #endif 46 47 static int tsec_send(struct eth_device *dev, 48 volatile void *packet, int length); 49 50 /* Default initializations for TSEC controllers. */ 51 52 static struct tsec_info_struct tsec_info[] = { 53 #ifdef CONFIG_TSEC1 54 STD_TSEC_INFO(1), /* TSEC1 */ 55 #endif 56 #ifdef CONFIG_TSEC2 57 STD_TSEC_INFO(2), /* TSEC2 */ 58 #endif 59 #ifdef CONFIG_MPC85XX_FEC 60 { 61 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 62 .devname = CONFIG_MPC85XX_FEC_NAME, 63 .phyaddr = FEC_PHY_ADDR, 64 .flags = FEC_FLAGS, 65 .mii_devname = DEFAULT_MII_NAME 66 }, /* FEC */ 67 #endif 68 #ifdef CONFIG_TSEC3 69 STD_TSEC_INFO(3), /* TSEC3 */ 70 #endif 71 #ifdef CONFIG_TSEC4 72 STD_TSEC_INFO(4), /* TSEC4 */ 73 #endif 74 }; 75 76 #define TBIANA_SETTINGS ( \ 77 TBIANA_ASYMMETRIC_PAUSE \ 78 | TBIANA_SYMMETRIC_PAUSE \ 79 | TBIANA_FULL_DUPLEX \ 80 ) 81 82 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ 83 #ifndef CONFIG_TSEC_TBICR_SETTINGS 84 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 85 TBICR_PHY_RESET \ 86 | TBICR_ANEG_ENABLE \ 87 | TBICR_FULL_DUPLEX \ 88 | TBICR_SPEED1_SET \ 89 ) 90 #endif /* CONFIG_TSEC_TBICR_SETTINGS */ 91 92 /* Configure the TBI for SGMII operation */ 93 static void tsec_configure_serdes(struct tsec_private *priv) 94 { 95 /* Access TBI PHY registers at given TSEC register offset as opposed 96 * to the register offset used for external PHY accesses */ 97 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 98 0, TBI_ANA, TBIANA_SETTINGS); 99 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 100 0, TBI_TBICON, TBICON_CLK_SELECT); 101 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 102 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS); 103 } 104 105 #ifdef CONFIG_MCAST_TFTP 106 107 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 108 109 /* Set the appropriate hash bit for the given addr */ 110 111 /* The algorithm works like so: 112 * 1) Take the Destination Address (ie the multicast address), and 113 * do a CRC on it (little endian), and reverse the bits of the 114 * result. 115 * 2) Use the 8 most significant bits as a hash into a 256-entry 116 * table. The table is controlled through 8 32-bit registers: 117 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 118 * gaddr7. This means that the 3 most significant bits in the 119 * hash index which gaddr register to use, and the 5 other bits 120 * indicate which bit (assuming an IBM numbering scheme, which 121 * for PowerPC (tm) is usually the case) in the tregister holds 122 * the entry. */ 123 static int 124 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 125 { 126 struct tsec_private *priv = privlist[1]; 127 volatile tsec_t *regs = priv->regs; 128 volatile u32 *reg_array, value; 129 u8 result, whichbit, whichreg; 130 131 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 132 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 133 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 134 value = (1 << (31-whichbit)); 135 136 reg_array = &(regs->hash.gaddr0); 137 138 if (set) { 139 reg_array[whichreg] |= value; 140 } else { 141 reg_array[whichreg] &= ~value; 142 } 143 return 0; 144 } 145 #endif /* Multicast TFTP ? */ 146 147 /* Initialized required registers to appropriate values, zeroing 148 * those we don't care about (unless zero is bad, in which case, 149 * choose a more appropriate value) 150 */ 151 static void init_registers(tsec_t *regs) 152 { 153 /* Clear IEVENT */ 154 out_be32(®s->ievent, IEVENT_INIT_CLEAR); 155 156 out_be32(®s->imask, IMASK_INIT_CLEAR); 157 158 out_be32(®s->hash.iaddr0, 0); 159 out_be32(®s->hash.iaddr1, 0); 160 out_be32(®s->hash.iaddr2, 0); 161 out_be32(®s->hash.iaddr3, 0); 162 out_be32(®s->hash.iaddr4, 0); 163 out_be32(®s->hash.iaddr5, 0); 164 out_be32(®s->hash.iaddr6, 0); 165 out_be32(®s->hash.iaddr7, 0); 166 167 out_be32(®s->hash.gaddr0, 0); 168 out_be32(®s->hash.gaddr1, 0); 169 out_be32(®s->hash.gaddr2, 0); 170 out_be32(®s->hash.gaddr3, 0); 171 out_be32(®s->hash.gaddr4, 0); 172 out_be32(®s->hash.gaddr5, 0); 173 out_be32(®s->hash.gaddr6, 0); 174 out_be32(®s->hash.gaddr7, 0); 175 176 out_be32(®s->rctrl, 0x00000000); 177 178 /* Init RMON mib registers */ 179 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 180 181 out_be32(®s->rmon.cam1, 0xffffffff); 182 out_be32(®s->rmon.cam2, 0xffffffff); 183 184 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS); 185 186 out_be32(®s->minflr, MINFLR_INIT_SETTINGS); 187 188 out_be32(®s->attr, ATTR_INIT_SETTINGS); 189 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS); 190 191 } 192 193 /* Configure maccfg2 based on negotiated speed and duplex 194 * reported by PHY handling code 195 */ 196 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) 197 { 198 tsec_t *regs = priv->regs; 199 u32 ecntrl, maccfg2; 200 201 if (!phydev->link) { 202 printf("%s: No link.\n", phydev->dev->name); 203 return; 204 } 205 206 /* clear all bits relative with interface mode */ 207 ecntrl = in_be32(®s->ecntrl); 208 ecntrl &= ~ECNTRL_R100; 209 210 maccfg2 = in_be32(®s->maccfg2); 211 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX); 212 213 if (phydev->duplex) 214 maccfg2 |= MACCFG2_FULL_DUPLEX; 215 216 switch (phydev->speed) { 217 case 1000: 218 maccfg2 |= MACCFG2_GMII; 219 break; 220 case 100: 221 case 10: 222 maccfg2 |= MACCFG2_MII; 223 224 /* Set R100 bit in all modes although 225 * it is only used in RGMII mode 226 */ 227 if (phydev->speed == 100) 228 ecntrl |= ECNTRL_R100; 229 break; 230 default: 231 printf("%s: Speed was bad\n", phydev->dev->name); 232 break; 233 } 234 235 out_be32(®s->ecntrl, ecntrl); 236 out_be32(®s->maccfg2, maccfg2); 237 238 printf("Speed: %d, %s duplex%s\n", phydev->speed, 239 (phydev->duplex) ? "full" : "half", 240 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 241 } 242 243 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 244 /* 245 * When MACCFG1[Rx_EN] is enabled during system boot as part 246 * of the eTSEC port initialization sequence, 247 * the eTSEC Rx logic may not be properly initialized. 248 */ 249 void redundant_init(struct eth_device *dev) 250 { 251 struct tsec_private *priv = dev->priv; 252 tsec_t *regs = priv->regs; 253 uint t, count = 0; 254 int fail = 1; 255 static const u8 pkt[] = { 256 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25, 257 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00, 258 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01, 259 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1, 260 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00, 261 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 262 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 263 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 264 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 265 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 266 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 267 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 268 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 269 0x71, 0x72}; 270 271 /* Enable promiscuous mode */ 272 setbits_be32(®s->rctrl, 0x8); 273 /* Enable loopback mode */ 274 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); 275 /* Enable transmit and receive */ 276 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); 277 278 /* Tell the DMA it is clear to go */ 279 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); 280 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 281 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 282 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 283 284 do { 285 tsec_send(dev, (void *)pkt, sizeof(pkt)); 286 287 /* Wait for buffer to be received */ 288 for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) { 289 if (t >= 10 * TOUT_LOOP) { 290 printf("%s: tsec: rx error\n", dev->name); 291 break; 292 } 293 } 294 295 if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt))) 296 fail = 0; 297 298 rtx.rxbd[rxIdx].length = 0; 299 rtx.rxbd[rxIdx].status = 300 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 301 rxIdx = (rxIdx + 1) % PKTBUFSRX; 302 303 if (in_be32(®s->ievent) & IEVENT_BSY) { 304 out_be32(®s->ievent, IEVENT_BSY); 305 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 306 } 307 if (fail) { 308 printf("loopback recv packet error!\n"); 309 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN); 310 udelay(1000); 311 setbits_be32(®s->maccfg1, MACCFG1_RX_EN); 312 } 313 } while ((count++ < 4) && (fail == 1)); 314 315 if (fail) 316 panic("eTSEC init fail!\n"); 317 /* Disable promiscuous mode */ 318 clrbits_be32(®s->rctrl, 0x8); 319 /* Disable loopback mode */ 320 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK); 321 } 322 #endif 323 324 /* Set up the buffers and their descriptors, and bring up the 325 * interface 326 */ 327 static void startup_tsec(struct eth_device *dev) 328 { 329 int i; 330 struct tsec_private *priv = (struct tsec_private *)dev->priv; 331 tsec_t *regs = priv->regs; 332 333 /* reset the indices to zero */ 334 rxIdx = 0; 335 txIdx = 0; 336 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 337 uint svr; 338 #endif 339 340 /* Point to the buffer descriptors */ 341 out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx])); 342 out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx])); 343 344 /* Initialize the Rx Buffer descriptors */ 345 for (i = 0; i < PKTBUFSRX; i++) { 346 rtx.rxbd[i].status = RXBD_EMPTY; 347 rtx.rxbd[i].length = 0; 348 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 349 } 350 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 351 352 /* Initialize the TX Buffer Descriptors */ 353 for (i = 0; i < TX_BUF_CNT; i++) { 354 rtx.txbd[i].status = 0; 355 rtx.txbd[i].length = 0; 356 rtx.txbd[i].bufPtr = 0; 357 } 358 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 359 360 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 361 svr = get_svr(); 362 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 363 redundant_init(dev); 364 #endif 365 /* Enable Transmit and Receive */ 366 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); 367 368 /* Tell the DMA it is clear to go */ 369 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); 370 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 371 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 372 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 373 } 374 375 /* This returns the status bits of the device. The return value 376 * is never checked, and this is what the 8260 driver did, so we 377 * do the same. Presumably, this would be zero if there were no 378 * errors 379 */ 380 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 381 { 382 int i; 383 int result = 0; 384 struct tsec_private *priv = (struct tsec_private *)dev->priv; 385 tsec_t *regs = priv->regs; 386 387 /* Find an empty buffer descriptor */ 388 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 389 if (i >= TOUT_LOOP) { 390 debug("%s: tsec: tx buffers full\n", dev->name); 391 return result; 392 } 393 } 394 395 rtx.txbd[txIdx].bufPtr = (uint) packet; 396 rtx.txbd[txIdx].length = length; 397 rtx.txbd[txIdx].status |= 398 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 399 400 /* Tell the DMA to go */ 401 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 402 403 /* Wait for buffer to be transmitted */ 404 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 405 if (i >= TOUT_LOOP) { 406 debug("%s: tsec: tx error\n", dev->name); 407 return result; 408 } 409 } 410 411 txIdx = (txIdx + 1) % TX_BUF_CNT; 412 result = rtx.txbd[txIdx].status & TXBD_STATS; 413 414 return result; 415 } 416 417 static int tsec_recv(struct eth_device *dev) 418 { 419 int length; 420 struct tsec_private *priv = (struct tsec_private *)dev->priv; 421 tsec_t *regs = priv->regs; 422 423 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 424 425 length = rtx.rxbd[rxIdx].length; 426 427 /* Send the packet up if there were no errors */ 428 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 429 NetReceive(NetRxPackets[rxIdx], length - 4); 430 } else { 431 printf("Got error %x\n", 432 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 433 } 434 435 rtx.rxbd[rxIdx].length = 0; 436 437 /* Set the wrap bit if this is the last element in the list */ 438 rtx.rxbd[rxIdx].status = 439 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 440 441 rxIdx = (rxIdx + 1) % PKTBUFSRX; 442 } 443 444 if (in_be32(®s->ievent) & IEVENT_BSY) { 445 out_be32(®s->ievent, IEVENT_BSY); 446 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 447 } 448 449 return -1; 450 451 } 452 453 /* Stop the interface */ 454 static void tsec_halt(struct eth_device *dev) 455 { 456 struct tsec_private *priv = (struct tsec_private *)dev->priv; 457 tsec_t *regs = priv->regs; 458 459 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 460 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 461 462 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) 463 != (IEVENT_GRSC | IEVENT_GTSC)) 464 ; 465 466 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); 467 468 /* Shut down the PHY, as needed */ 469 phy_shutdown(priv->phydev); 470 } 471 472 /* Initializes data structures and registers for the controller, 473 * and brings the interface up. Returns the link status, meaning 474 * that it returns success if the link is up, failure otherwise. 475 * This allows u-boot to find the first active controller. 476 */ 477 static int tsec_init(struct eth_device *dev, bd_t * bd) 478 { 479 uint tempval; 480 char tmpbuf[MAC_ADDR_LEN]; 481 int i; 482 struct tsec_private *priv = (struct tsec_private *)dev->priv; 483 tsec_t *regs = priv->regs; 484 485 /* Make sure the controller is stopped */ 486 tsec_halt(dev); 487 488 /* Init MACCFG2. Defaults to GMII */ 489 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS); 490 491 /* Init ECNTRL */ 492 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); 493 494 /* Copy the station address into the address registers. 495 * Backwards, because little endian MACS are dumb */ 496 for (i = 0; i < MAC_ADDR_LEN; i++) 497 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 498 499 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | 500 tmpbuf[3]; 501 502 out_be32(®s->macstnaddr1, tempval); 503 504 tempval = *((uint *) (tmpbuf + 4)); 505 506 out_be32(®s->macstnaddr2, tempval); 507 508 /* Clear out (for the most part) the other registers */ 509 init_registers(regs); 510 511 /* Ready the device for tx/rx */ 512 startup_tsec(dev); 513 514 /* Start up the PHY */ 515 phy_startup(priv->phydev); 516 517 adjust_link(priv, priv->phydev); 518 519 /* If there's no link, fail */ 520 return priv->phydev->link ? 0 : -1; 521 } 522 523 static phy_interface_t tsec_get_interface(struct tsec_private *priv) 524 { 525 tsec_t *regs = priv->regs; 526 u32 ecntrl; 527 528 ecntrl = in_be32(®s->ecntrl); 529 530 if (ecntrl & ECNTRL_SGMII_MODE) 531 return PHY_INTERFACE_MODE_SGMII; 532 533 if (ecntrl & ECNTRL_TBI_MODE) { 534 if (ecntrl & ECNTRL_REDUCED_MODE) 535 return PHY_INTERFACE_MODE_RTBI; 536 else 537 return PHY_INTERFACE_MODE_TBI; 538 } 539 540 if (ecntrl & ECNTRL_REDUCED_MODE) { 541 if (ecntrl & ECNTRL_REDUCED_MII_MODE) 542 return PHY_INTERFACE_MODE_RMII; 543 else { 544 phy_interface_t interface = priv->interface; 545 546 /* 547 * This isn't autodetected, so it must 548 * be set by the platform code. 549 */ 550 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) || 551 (interface == PHY_INTERFACE_MODE_RGMII_TXID) || 552 (interface == PHY_INTERFACE_MODE_RGMII_RXID)) 553 return interface; 554 555 return PHY_INTERFACE_MODE_RGMII; 556 } 557 } 558 559 if (priv->flags & TSEC_GIGABIT) 560 return PHY_INTERFACE_MODE_GMII; 561 562 return PHY_INTERFACE_MODE_MII; 563 } 564 565 566 /* Discover which PHY is attached to the device, and configure it 567 * properly. If the PHY is not recognized, then return 0 568 * (failure). Otherwise, return 1 569 */ 570 static int init_phy(struct eth_device *dev) 571 { 572 struct tsec_private *priv = (struct tsec_private *)dev->priv; 573 struct phy_device *phydev; 574 tsec_t *regs = priv->regs; 575 u32 supported = (SUPPORTED_10baseT_Half | 576 SUPPORTED_10baseT_Full | 577 SUPPORTED_100baseT_Half | 578 SUPPORTED_100baseT_Full); 579 580 if (priv->flags & TSEC_GIGABIT) 581 supported |= SUPPORTED_1000baseT_Full; 582 583 /* Assign a Physical address to the TBI */ 584 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); 585 586 priv->interface = tsec_get_interface(priv); 587 588 if (priv->interface == PHY_INTERFACE_MODE_SGMII) 589 tsec_configure_serdes(priv); 590 591 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); 592 593 phydev->supported &= supported; 594 phydev->advertising = phydev->supported; 595 596 priv->phydev = phydev; 597 598 phy_config(phydev); 599 600 return 1; 601 } 602 603 /* Initialize device structure. Returns success if PHY 604 * initialization succeeded (i.e. if it recognizes the PHY) 605 */ 606 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) 607 { 608 struct eth_device *dev; 609 int i; 610 struct tsec_private *priv; 611 612 dev = (struct eth_device *)malloc(sizeof *dev); 613 614 if (NULL == dev) 615 return 0; 616 617 memset(dev, 0, sizeof *dev); 618 619 priv = (struct tsec_private *)malloc(sizeof(*priv)); 620 621 if (NULL == priv) 622 return 0; 623 624 privlist[num_tsecs++] = priv; 625 priv->regs = tsec_info->regs; 626 priv->phyregs_sgmii = tsec_info->miiregs_sgmii; 627 628 priv->phyaddr = tsec_info->phyaddr; 629 priv->flags = tsec_info->flags; 630 631 sprintf(dev->name, tsec_info->devname); 632 priv->interface = tsec_info->interface; 633 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); 634 dev->iobase = 0; 635 dev->priv = priv; 636 dev->init = tsec_init; 637 dev->halt = tsec_halt; 638 dev->send = tsec_send; 639 dev->recv = tsec_recv; 640 #ifdef CONFIG_MCAST_TFTP 641 dev->mcast = tsec_mcast_addr; 642 #endif 643 644 /* Tell u-boot to get the addr from the env */ 645 for (i = 0; i < 6; i++) 646 dev->enetaddr[i] = 0; 647 648 eth_register(dev); 649 650 /* Reset the MAC */ 651 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); 652 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ 653 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); 654 655 /* Try to initialize PHY here, and return */ 656 return init_phy(dev); 657 } 658 659 /* 660 * Initialize all the TSEC devices 661 * 662 * Returns the number of TSEC devices that were initialized 663 */ 664 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 665 { 666 int i; 667 int ret, count = 0; 668 669 for (i = 0; i < num; i++) { 670 ret = tsec_initialize(bis, &tsecs[i]); 671 if (ret > 0) 672 count += ret; 673 } 674 675 return count; 676 } 677 678 int tsec_standard_init(bd_t *bis) 679 { 680 struct fsl_pq_mdio_info info; 681 682 info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 683 info.name = DEFAULT_MII_NAME; 684 685 fsl_pq_mdio_init(bis, &info); 686 687 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 688 } 689