1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 20 #include "tsec.h" 21 #include "miiphy.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define TX_BUF_CNT 2 26 27 static uint rxIdx; /* index of the current RX buffer */ 28 static uint txIdx; /* index of the current TX buffer */ 29 30 typedef volatile struct rtxbd { 31 txbd8_t txbd[TX_BUF_CNT]; 32 rxbd8_t rxbd[PKTBUFSRX]; 33 } RTXBD; 34 35 struct tsec_info_struct { 36 unsigned int phyaddr; 37 u32 flags; 38 unsigned int phyregidx; 39 }; 40 41 /* The tsec_info structure contains 3 values which the 42 * driver uses to determine how to operate a given ethernet 43 * device. The information needed is: 44 * phyaddr - The address of the PHY which is attached to 45 * the given device. 46 * 47 * flags - This variable indicates whether the device 48 * supports gigabit speed ethernet, and whether it should be 49 * in reduced mode. 50 * 51 * phyregidx - This variable specifies which ethernet device 52 * controls the MII Management registers which are connected 53 * to the PHY. For now, only TSEC1 (index 0) has 54 * access to the PHYs, so all of the entries have "0". 55 * 56 * The values specified in the table are taken from the board's 57 * config file in include/configs/. When implementing a new 58 * board with ethernet capability, it is necessary to define: 59 * TSECn_PHY_ADDR 60 * TSECn_PHYIDX 61 * 62 * for n = 1,2,3, etc. And for FEC: 63 * FEC_PHY_ADDR 64 * FEC_PHYIDX 65 */ 66 static struct tsec_info_struct tsec_info[] = { 67 #ifdef CONFIG_TSEC1 68 {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX}, 69 #else 70 {0, 0, 0}, 71 #endif 72 #ifdef CONFIG_TSEC2 73 {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX}, 74 #else 75 {0, 0, 0}, 76 #endif 77 #ifdef CONFIG_MPC85XX_FEC 78 {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX}, 79 #else 80 #ifdef CONFIG_TSEC3 81 {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX}, 82 #else 83 {0, 0, 0}, 84 #endif 85 #ifdef CONFIG_TSEC4 86 {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX}, 87 #else 88 {0, 0, 0}, 89 #endif /* CONFIG_TSEC4 */ 90 #endif /* CONFIG_MPC85XX_FEC */ 91 }; 92 93 #define MAXCONTROLLERS (4) 94 95 static int relocated = 0; 96 97 static struct tsec_private *privlist[MAXCONTROLLERS]; 98 99 #ifdef __GNUC__ 100 static RTXBD rtx __attribute__ ((aligned(8))); 101 #else 102 #error "rtx must be 64-bit aligned" 103 #endif 104 105 static int tsec_send(struct eth_device *dev, 106 volatile void *packet, int length); 107 static int tsec_recv(struct eth_device *dev); 108 static int tsec_init(struct eth_device *dev, bd_t * bd); 109 static void tsec_halt(struct eth_device *dev); 110 static void init_registers(volatile tsec_t * regs); 111 static void startup_tsec(struct eth_device *dev); 112 static int init_phy(struct eth_device *dev); 113 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 114 uint read_phy_reg(struct tsec_private *priv, uint regnum); 115 struct phy_info *get_phy_info(struct eth_device *dev); 116 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 117 static void adjust_link(struct eth_device *dev); 118 static void relocate_cmds(void); 119 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 120 && !defined(BITBANGMII) 121 static int tsec_miiphy_write(char *devname, unsigned char addr, 122 unsigned char reg, unsigned short value); 123 static int tsec_miiphy_read(char *devname, unsigned char addr, 124 unsigned char reg, unsigned short *value); 125 #endif 126 #ifdef CONFIG_MCAST_TFTP 127 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 128 #endif 129 130 /* Initialize device structure. Returns success if PHY 131 * initialization succeeded (i.e. if it recognizes the PHY) 132 */ 133 int tsec_initialize(bd_t * bis, int index, char *devname) 134 { 135 struct eth_device *dev; 136 int i; 137 struct tsec_private *priv; 138 139 dev = (struct eth_device *)malloc(sizeof *dev); 140 141 if (NULL == dev) 142 return 0; 143 144 memset(dev, 0, sizeof *dev); 145 146 priv = (struct tsec_private *)malloc(sizeof(*priv)); 147 148 if (NULL == priv) 149 return 0; 150 151 privlist[index] = priv; 152 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE); 153 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + 154 tsec_info[index].phyregidx * 155 TSEC_SIZE); 156 157 priv->phyaddr = tsec_info[index].phyaddr; 158 priv->flags = tsec_info[index].flags; 159 160 sprintf(dev->name, devname); 161 dev->iobase = 0; 162 dev->priv = priv; 163 dev->init = tsec_init; 164 dev->halt = tsec_halt; 165 dev->send = tsec_send; 166 dev->recv = tsec_recv; 167 #ifdef CONFIG_MCAST_TFTP 168 dev->mcast = tsec_mcast_addr; 169 #endif 170 171 /* Tell u-boot to get the addr from the env */ 172 for (i = 0; i < 6; i++) 173 dev->enetaddr[i] = 0; 174 175 eth_register(dev); 176 177 /* Reset the MAC */ 178 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 179 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 180 181 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 182 && !defined(BITBANGMII) 183 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 184 #endif 185 186 /* Try to initialize PHY here, and return */ 187 return init_phy(dev); 188 } 189 190 /* Initializes data structures and registers for the controller, 191 * and brings the interface up. Returns the link status, meaning 192 * that it returns success if the link is up, failure otherwise. 193 * This allows u-boot to find the first active controller. 194 */ 195 int tsec_init(struct eth_device *dev, bd_t * bd) 196 { 197 uint tempval; 198 char tmpbuf[MAC_ADDR_LEN]; 199 int i; 200 struct tsec_private *priv = (struct tsec_private *)dev->priv; 201 volatile tsec_t *regs = priv->regs; 202 203 /* Make sure the controller is stopped */ 204 tsec_halt(dev); 205 206 /* Init MACCFG2. Defaults to GMII */ 207 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 208 209 /* Init ECNTRL */ 210 regs->ecntrl = ECNTRL_INIT_SETTINGS; 211 212 /* Copy the station address into the address registers. 213 * Backwards, because little endian MACS are dumb */ 214 for (i = 0; i < MAC_ADDR_LEN; i++) { 215 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 216 } 217 regs->macstnaddr1 = *((uint *) (tmpbuf)); 218 219 tempval = *((uint *) (tmpbuf + 4)); 220 221 regs->macstnaddr2 = tempval; 222 223 /* reset the indices to zero */ 224 rxIdx = 0; 225 txIdx = 0; 226 227 /* Clear out (for the most part) the other registers */ 228 init_registers(regs); 229 230 /* Ready the device for tx/rx */ 231 startup_tsec(dev); 232 233 /* If there's no link, fail */ 234 return (priv->link ? 0 : -1); 235 236 } 237 238 /* Write value to the device's PHY through the registers 239 * specified in priv, modifying the register specified in regnum. 240 * It will wait for the write to be done (or for a timeout to 241 * expire) before exiting 242 */ 243 void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value) 244 { 245 volatile tsec_t *regbase = priv->phyregs; 246 int timeout = 1000000; 247 248 regbase->miimadd = (phyid << 8) | regnum; 249 regbase->miimcon = value; 250 asm("sync"); 251 252 timeout = 1000000; 253 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 254 } 255 256 /* #define to provide old write_phy_reg functionality without duplicating code */ 257 #define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value) 258 259 /* Reads register regnum on the device's PHY through the 260 * registers specified in priv. It lowers and raises the read 261 * command, and waits for the data to become valid (miimind 262 * notvalid bit cleared), and the bus to cease activity (miimind 263 * busy bit cleared), and then returns the value 264 */ 265 uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum) 266 { 267 uint value; 268 volatile tsec_t *regbase = priv->phyregs; 269 270 /* Put the address of the phy, and the register 271 * number into MIIMADD */ 272 regbase->miimadd = (phyid << 8) | regnum; 273 274 /* Clear the command register, and wait */ 275 regbase->miimcom = 0; 276 asm("sync"); 277 278 /* Initiate a read command, and wait */ 279 regbase->miimcom = MIIM_READ_COMMAND; 280 asm("sync"); 281 282 /* Wait for the the indication that the read is done */ 283 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 284 285 /* Grab the value read from the PHY */ 286 value = regbase->miimstat; 287 288 return value; 289 } 290 291 /* #define to provide old read_phy_reg functionality without duplicating code */ 292 #define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum) 293 294 /* Discover which PHY is attached to the device, and configure it 295 * properly. If the PHY is not recognized, then return 0 296 * (failure). Otherwise, return 1 297 */ 298 static int init_phy(struct eth_device *dev) 299 { 300 struct tsec_private *priv = (struct tsec_private *)dev->priv; 301 struct phy_info *curphy; 302 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); 303 304 /* Assign a Physical address to the TBI */ 305 regs->tbipa = CFG_TBIPA_VALUE; 306 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); 307 regs->tbipa = CFG_TBIPA_VALUE; 308 asm("sync"); 309 310 /* Reset MII (due to new addresses) */ 311 priv->phyregs->miimcfg = MIIMCFG_RESET; 312 asm("sync"); 313 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 314 asm("sync"); 315 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 316 317 if (0 == relocated) 318 relocate_cmds(); 319 320 /* Get the cmd structure corresponding to the attached 321 * PHY */ 322 curphy = get_phy_info(dev); 323 324 if (curphy == NULL) { 325 priv->phyinfo = NULL; 326 printf("%s: No PHY found\n", dev->name); 327 328 return 0; 329 } 330 331 priv->phyinfo = curphy; 332 333 phy_run_commands(priv, priv->phyinfo->config); 334 335 return 1; 336 } 337 338 /* 339 * Returns which value to write to the control register. 340 * For 10/100, the value is slightly different 341 */ 342 uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 343 { 344 if (priv->flags & TSEC_GIGABIT) 345 return MIIM_CONTROL_INIT; 346 else 347 return MIIM_CR_INIT; 348 } 349 350 /* Parse the status register for link, and then do 351 * auto-negotiation 352 */ 353 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 354 { 355 /* 356 * Wait if the link is up, and autonegotiation is in progress 357 * (ie - we're capable and it's not done) 358 */ 359 mii_reg = read_phy_reg(priv, MIIM_STATUS); 360 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) 361 && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 362 int i = 0; 363 364 puts("Waiting for PHY auto negotiation to complete"); 365 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 366 /* 367 * Timeout reached ? 368 */ 369 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 370 puts(" TIMEOUT !\n"); 371 priv->link = 0; 372 return 0; 373 } 374 375 if ((i++ % 1000) == 0) { 376 putc('.'); 377 } 378 udelay(1000); /* 1 ms */ 379 mii_reg = read_phy_reg(priv, MIIM_STATUS); 380 } 381 puts(" done\n"); 382 priv->link = 1; 383 udelay(500000); /* another 500 ms (results in faster booting) */ 384 } else { 385 if (mii_reg & MIIM_STATUS_LINK) 386 priv->link = 1; 387 else 388 priv->link = 0; 389 } 390 391 return 0; 392 } 393 394 /* Generic function which updates the speed and duplex. If 395 * autonegotiation is enabled, it uses the AND of the link 396 * partner's advertised capabilities and our advertised 397 * capabilities. If autonegotiation is disabled, we use the 398 * appropriate bits in the control register. 399 * 400 * Stolen from Linux's mii.c and phy_device.c 401 */ 402 uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 403 { 404 /* We're using autonegotiation */ 405 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 406 uint lpa = 0; 407 uint gblpa = 0; 408 409 /* Check for gigabit capability */ 410 if (mii_reg & PHY_BMSR_EXT) { 411 /* We want a list of states supported by 412 * both PHYs in the link 413 */ 414 gblpa = read_phy_reg(priv, PHY_1000BTSR); 415 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 416 } 417 418 /* Set the baseline so we only have to set them 419 * if they're different 420 */ 421 priv->speed = 10; 422 priv->duplexity = 0; 423 424 /* Check the gigabit fields */ 425 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 426 priv->speed = 1000; 427 428 if (gblpa & PHY_1000BTSR_1000FD) 429 priv->duplexity = 1; 430 431 /* We're done! */ 432 return 0; 433 } 434 435 lpa = read_phy_reg(priv, PHY_ANAR); 436 lpa &= read_phy_reg(priv, PHY_ANLPAR); 437 438 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 439 priv->speed = 100; 440 441 if (lpa & PHY_ANLPAR_TXFD) 442 priv->duplexity = 1; 443 444 } else if (lpa & PHY_ANLPAR_10FD) 445 priv->duplexity = 1; 446 } else { 447 uint bmcr = read_phy_reg(priv, PHY_BMCR); 448 449 priv->speed = 10; 450 priv->duplexity = 0; 451 452 if (bmcr & PHY_BMCR_DPLX) 453 priv->duplexity = 1; 454 455 if (bmcr & PHY_BMCR_1000_MBPS) 456 priv->speed = 1000; 457 else if (bmcr & PHY_BMCR_100_MBPS) 458 priv->speed = 100; 459 } 460 461 return 0; 462 } 463 464 /* 465 * Parse the BCM54xx status register for speed and duplex information. 466 * The linux sungem_phy has this information, but in a table format. 467 */ 468 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 469 { 470 471 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ 472 473 case 1: 474 printf("Enet starting in 10BT/HD\n"); 475 priv->duplexity = 0; 476 priv->speed = 10; 477 break; 478 479 case 2: 480 printf("Enet starting in 10BT/FD\n"); 481 priv->duplexity = 1; 482 priv->speed = 10; 483 break; 484 485 case 3: 486 printf("Enet starting in 100BT/HD\n"); 487 priv->duplexity = 0; 488 priv->speed = 100; 489 break; 490 491 case 5: 492 printf("Enet starting in 100BT/FD\n"); 493 priv->duplexity = 1; 494 priv->speed = 100; 495 break; 496 497 case 6: 498 printf("Enet starting in 1000BT/HD\n"); 499 priv->duplexity = 0; 500 priv->speed = 1000; 501 break; 502 503 case 7: 504 printf("Enet starting in 1000BT/FD\n"); 505 priv->duplexity = 1; 506 priv->speed = 1000; 507 break; 508 509 default: 510 printf("Auto-neg error, defaulting to 10BT/HD\n"); 511 priv->duplexity = 0; 512 priv->speed = 10; 513 break; 514 } 515 516 return 0; 517 518 } 519 /* Parse the 88E1011's status register for speed and duplex 520 * information 521 */ 522 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 523 { 524 uint speed; 525 526 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 527 528 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 529 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 530 int i = 0; 531 532 puts("Waiting for PHY realtime link"); 533 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 534 /* Timeout reached ? */ 535 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 536 puts(" TIMEOUT !\n"); 537 priv->link = 0; 538 break; 539 } 540 541 if ((i++ % 1000) == 0) { 542 putc('.'); 543 } 544 udelay(1000); /* 1 ms */ 545 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 546 } 547 puts(" done\n"); 548 udelay(500000); /* another 500 ms (results in faster booting) */ 549 } else { 550 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 551 priv->link = 1; 552 else 553 priv->link = 0; 554 } 555 556 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 557 priv->duplexity = 1; 558 else 559 priv->duplexity = 0; 560 561 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 562 563 switch (speed) { 564 case MIIM_88E1011_PHYSTAT_GBIT: 565 priv->speed = 1000; 566 break; 567 case MIIM_88E1011_PHYSTAT_100: 568 priv->speed = 100; 569 break; 570 default: 571 priv->speed = 10; 572 } 573 574 return 0; 575 } 576 577 /* Parse the RTL8211B's status register for speed and duplex 578 * information 579 */ 580 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 581 { 582 uint speed; 583 584 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 585 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 586 int i = 0; 587 588 /* in case of timeout ->link is cleared */ 589 priv->link = 1; 590 puts("Waiting for PHY realtime link"); 591 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 592 /* Timeout reached ? */ 593 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 594 puts(" TIMEOUT !\n"); 595 priv->link = 0; 596 break; 597 } 598 599 if ((i++ % 1000) == 0) { 600 putc('.'); 601 } 602 udelay(1000); /* 1 ms */ 603 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 604 } 605 puts(" done\n"); 606 udelay(500000); /* another 500 ms (results in faster booting) */ 607 } else { 608 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 609 priv->link = 1; 610 else 611 priv->link = 0; 612 } 613 614 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 615 priv->duplexity = 1; 616 else 617 priv->duplexity = 0; 618 619 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 620 621 switch (speed) { 622 case MIIM_RTL8211B_PHYSTAT_GBIT: 623 priv->speed = 1000; 624 break; 625 case MIIM_RTL8211B_PHYSTAT_100: 626 priv->speed = 100; 627 break; 628 default: 629 priv->speed = 10; 630 } 631 632 return 0; 633 } 634 635 /* Parse the cis8201's status register for speed and duplex 636 * information 637 */ 638 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 639 { 640 uint speed; 641 642 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 643 priv->duplexity = 1; 644 else 645 priv->duplexity = 0; 646 647 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 648 switch (speed) { 649 case MIIM_CIS8201_AUXCONSTAT_GBIT: 650 priv->speed = 1000; 651 break; 652 case MIIM_CIS8201_AUXCONSTAT_100: 653 priv->speed = 100; 654 break; 655 default: 656 priv->speed = 10; 657 break; 658 } 659 660 return 0; 661 } 662 663 /* Parse the vsc8244's status register for speed and duplex 664 * information 665 */ 666 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 667 { 668 uint speed; 669 670 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 671 priv->duplexity = 1; 672 else 673 priv->duplexity = 0; 674 675 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 676 switch (speed) { 677 case MIIM_VSC8244_AUXCONSTAT_GBIT: 678 priv->speed = 1000; 679 break; 680 case MIIM_VSC8244_AUXCONSTAT_100: 681 priv->speed = 100; 682 break; 683 default: 684 priv->speed = 10; 685 break; 686 } 687 688 return 0; 689 } 690 691 /* Parse the DM9161's status register for speed and duplex 692 * information 693 */ 694 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 695 { 696 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 697 priv->speed = 100; 698 else 699 priv->speed = 10; 700 701 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 702 priv->duplexity = 1; 703 else 704 priv->duplexity = 0; 705 706 return 0; 707 } 708 709 /* 710 * Hack to write all 4 PHYs with the LED values 711 */ 712 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 713 { 714 uint phyid; 715 volatile tsec_t *regbase = priv->phyregs; 716 int timeout = 1000000; 717 718 for (phyid = 0; phyid < 4; phyid++) { 719 regbase->miimadd = (phyid << 8) | mii_reg; 720 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 721 asm("sync"); 722 723 timeout = 1000000; 724 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 725 } 726 727 return MIIM_CIS8204_SLEDCON_INIT; 728 } 729 730 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 731 { 732 if (priv->flags & TSEC_REDUCED) 733 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 734 else 735 return MIIM_CIS8204_EPHYCON_INIT; 736 } 737 738 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 739 { 740 uint mii_data = read_phy_reg(priv, mii_reg); 741 742 if (priv->flags & TSEC_REDUCED) 743 mii_data = (mii_data & 0xfff0) | 0x000b; 744 return mii_data; 745 } 746 747 /* Initialized required registers to appropriate values, zeroing 748 * those we don't care about (unless zero is bad, in which case, 749 * choose a more appropriate value) 750 */ 751 static void init_registers(volatile tsec_t * regs) 752 { 753 /* Clear IEVENT */ 754 regs->ievent = IEVENT_INIT_CLEAR; 755 756 regs->imask = IMASK_INIT_CLEAR; 757 758 regs->hash.iaddr0 = 0; 759 regs->hash.iaddr1 = 0; 760 regs->hash.iaddr2 = 0; 761 regs->hash.iaddr3 = 0; 762 regs->hash.iaddr4 = 0; 763 regs->hash.iaddr5 = 0; 764 regs->hash.iaddr6 = 0; 765 regs->hash.iaddr7 = 0; 766 767 regs->hash.gaddr0 = 0; 768 regs->hash.gaddr1 = 0; 769 regs->hash.gaddr2 = 0; 770 regs->hash.gaddr3 = 0; 771 regs->hash.gaddr4 = 0; 772 regs->hash.gaddr5 = 0; 773 regs->hash.gaddr6 = 0; 774 regs->hash.gaddr7 = 0; 775 776 regs->rctrl = 0x00000000; 777 778 /* Init RMON mib registers */ 779 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 780 781 regs->rmon.cam1 = 0xffffffff; 782 regs->rmon.cam2 = 0xffffffff; 783 784 regs->mrblr = MRBLR_INIT_SETTINGS; 785 786 regs->minflr = MINFLR_INIT_SETTINGS; 787 788 regs->attr = ATTR_INIT_SETTINGS; 789 regs->attreli = ATTRELI_INIT_SETTINGS; 790 791 } 792 793 /* Configure maccfg2 based on negotiated speed and duplex 794 * reported by PHY handling code 795 */ 796 static void adjust_link(struct eth_device *dev) 797 { 798 struct tsec_private *priv = (struct tsec_private *)dev->priv; 799 volatile tsec_t *regs = priv->regs; 800 801 if (priv->link) { 802 if (priv->duplexity != 0) 803 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 804 else 805 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 806 807 switch (priv->speed) { 808 case 1000: 809 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 810 | MACCFG2_GMII); 811 break; 812 case 100: 813 case 10: 814 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 815 | MACCFG2_MII); 816 817 /* Set R100 bit in all modes although 818 * it is only used in RGMII mode 819 */ 820 if (priv->speed == 100) 821 regs->ecntrl |= ECNTRL_R100; 822 else 823 regs->ecntrl &= ~(ECNTRL_R100); 824 break; 825 default: 826 printf("%s: Speed was bad\n", dev->name); 827 break; 828 } 829 830 printf("Speed: %d, %s duplex\n", priv->speed, 831 (priv->duplexity) ? "full" : "half"); 832 833 } else { 834 printf("%s: No link.\n", dev->name); 835 } 836 } 837 838 /* Set up the buffers and their descriptors, and bring up the 839 * interface 840 */ 841 static void startup_tsec(struct eth_device *dev) 842 { 843 int i; 844 struct tsec_private *priv = (struct tsec_private *)dev->priv; 845 volatile tsec_t *regs = priv->regs; 846 847 /* Point to the buffer descriptors */ 848 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 849 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 850 851 /* Initialize the Rx Buffer descriptors */ 852 for (i = 0; i < PKTBUFSRX; i++) { 853 rtx.rxbd[i].status = RXBD_EMPTY; 854 rtx.rxbd[i].length = 0; 855 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 856 } 857 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 858 859 /* Initialize the TX Buffer Descriptors */ 860 for (i = 0; i < TX_BUF_CNT; i++) { 861 rtx.txbd[i].status = 0; 862 rtx.txbd[i].length = 0; 863 rtx.txbd[i].bufPtr = 0; 864 } 865 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 866 867 /* Start up the PHY */ 868 if(priv->phyinfo) 869 phy_run_commands(priv, priv->phyinfo->startup); 870 871 adjust_link(dev); 872 873 /* Enable Transmit and Receive */ 874 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 875 876 /* Tell the DMA it is clear to go */ 877 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 878 regs->tstat = TSTAT_CLEAR_THALT; 879 regs->rstat = RSTAT_CLEAR_RHALT; 880 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 881 } 882 883 /* This returns the status bits of the device. The return value 884 * is never checked, and this is what the 8260 driver did, so we 885 * do the same. Presumably, this would be zero if there were no 886 * errors 887 */ 888 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 889 { 890 int i; 891 int result = 0; 892 struct tsec_private *priv = (struct tsec_private *)dev->priv; 893 volatile tsec_t *regs = priv->regs; 894 895 /* Find an empty buffer descriptor */ 896 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 897 if (i >= TOUT_LOOP) { 898 debug("%s: tsec: tx buffers full\n", dev->name); 899 return result; 900 } 901 } 902 903 rtx.txbd[txIdx].bufPtr = (uint) packet; 904 rtx.txbd[txIdx].length = length; 905 rtx.txbd[txIdx].status |= 906 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 907 908 /* Tell the DMA to go */ 909 regs->tstat = TSTAT_CLEAR_THALT; 910 911 /* Wait for buffer to be transmitted */ 912 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 913 if (i >= TOUT_LOOP) { 914 debug("%s: tsec: tx error\n", dev->name); 915 return result; 916 } 917 } 918 919 txIdx = (txIdx + 1) % TX_BUF_CNT; 920 result = rtx.txbd[txIdx].status & TXBD_STATS; 921 922 return result; 923 } 924 925 static int tsec_recv(struct eth_device *dev) 926 { 927 int length; 928 struct tsec_private *priv = (struct tsec_private *)dev->priv; 929 volatile tsec_t *regs = priv->regs; 930 931 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 932 933 length = rtx.rxbd[rxIdx].length; 934 935 /* Send the packet up if there were no errors */ 936 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 937 NetReceive(NetRxPackets[rxIdx], length - 4); 938 } else { 939 printf("Got error %x\n", 940 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 941 } 942 943 rtx.rxbd[rxIdx].length = 0; 944 945 /* Set the wrap bit if this is the last element in the list */ 946 rtx.rxbd[rxIdx].status = 947 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 948 949 rxIdx = (rxIdx + 1) % PKTBUFSRX; 950 } 951 952 if (regs->ievent & IEVENT_BSY) { 953 regs->ievent = IEVENT_BSY; 954 regs->rstat = RSTAT_CLEAR_RHALT; 955 } 956 957 return -1; 958 959 } 960 961 /* Stop the interface */ 962 static void tsec_halt(struct eth_device *dev) 963 { 964 struct tsec_private *priv = (struct tsec_private *)dev->priv; 965 volatile tsec_t *regs = priv->regs; 966 967 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 968 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 969 970 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 971 972 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 973 974 /* Shut down the PHY, as needed */ 975 if(priv->phyinfo) 976 phy_run_commands(priv, priv->phyinfo->shutdown); 977 } 978 979 struct phy_info phy_info_M88E1149S = { 980 0x1410ca, 981 "Marvell 88E1149S", 982 4, 983 (struct phy_cmd[]){ /* config */ 984 /* Reset and configure the PHY */ 985 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 986 {0x1d, 0x1f, NULL}, 987 {0x1e, 0x200c, NULL}, 988 {0x1d, 0x5, NULL}, 989 {0x1e, 0x0, NULL}, 990 {0x1e, 0x100, NULL}, 991 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 992 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 993 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 994 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 995 {miim_end,} 996 }, 997 (struct phy_cmd[]){ /* startup */ 998 /* Status is read once to clear old link state */ 999 {MIIM_STATUS, miim_read, NULL}, 1000 /* Auto-negotiate */ 1001 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1002 /* Read the status */ 1003 {MIIM_88E1011_PHY_STATUS, miim_read, 1004 &mii_parse_88E1011_psr}, 1005 {miim_end,} 1006 }, 1007 (struct phy_cmd[]){ /* shutdown */ 1008 {miim_end,} 1009 }, 1010 }; 1011 1012 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1013 struct phy_info phy_info_BCM5461S = { 1014 0x02060c1, /* 5461 ID */ 1015 "Broadcom BCM5461S", 1016 0, /* not clear to me what minor revisions we can shift away */ 1017 (struct phy_cmd[]) { /* config */ 1018 /* Reset and configure the PHY */ 1019 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1020 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1021 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1022 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1023 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1024 {miim_end,} 1025 }, 1026 (struct phy_cmd[]) { /* startup */ 1027 /* Status is read once to clear old link state */ 1028 {MIIM_STATUS, miim_read, NULL}, 1029 /* Auto-negotiate */ 1030 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1031 /* Read the status */ 1032 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1033 {miim_end,} 1034 }, 1035 (struct phy_cmd[]) { /* shutdown */ 1036 {miim_end,} 1037 }, 1038 }; 1039 1040 struct phy_info phy_info_BCM5464S = { 1041 0x02060b1, /* 5464 ID */ 1042 "Broadcom BCM5464S", 1043 0, /* not clear to me what minor revisions we can shift away */ 1044 (struct phy_cmd[]) { /* config */ 1045 /* Reset and configure the PHY */ 1046 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1047 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1048 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1049 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1050 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1051 {miim_end,} 1052 }, 1053 (struct phy_cmd[]) { /* startup */ 1054 /* Status is read once to clear old link state */ 1055 {MIIM_STATUS, miim_read, NULL}, 1056 /* Auto-negotiate */ 1057 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1058 /* Read the status */ 1059 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1060 {miim_end,} 1061 }, 1062 (struct phy_cmd[]) { /* shutdown */ 1063 {miim_end,} 1064 }, 1065 }; 1066 1067 struct phy_info phy_info_M88E1011S = { 1068 0x01410c6, 1069 "Marvell 88E1011S", 1070 4, 1071 (struct phy_cmd[]){ /* config */ 1072 /* Reset and configure the PHY */ 1073 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1074 {0x1d, 0x1f, NULL}, 1075 {0x1e, 0x200c, NULL}, 1076 {0x1d, 0x5, NULL}, 1077 {0x1e, 0x0, NULL}, 1078 {0x1e, 0x100, NULL}, 1079 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1080 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1081 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1082 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1083 {miim_end,} 1084 }, 1085 (struct phy_cmd[]){ /* startup */ 1086 /* Status is read once to clear old link state */ 1087 {MIIM_STATUS, miim_read, NULL}, 1088 /* Auto-negotiate */ 1089 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1090 /* Read the status */ 1091 {MIIM_88E1011_PHY_STATUS, miim_read, 1092 &mii_parse_88E1011_psr}, 1093 {miim_end,} 1094 }, 1095 (struct phy_cmd[]){ /* shutdown */ 1096 {miim_end,} 1097 }, 1098 }; 1099 1100 struct phy_info phy_info_M88E1111S = { 1101 0x01410cc, 1102 "Marvell 88E1111S", 1103 4, 1104 (struct phy_cmd[]){ /* config */ 1105 /* Reset and configure the PHY */ 1106 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1107 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1108 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1109 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1110 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1111 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1112 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1113 {miim_end,} 1114 }, 1115 (struct phy_cmd[]){ /* startup */ 1116 /* Status is read once to clear old link state */ 1117 {MIIM_STATUS, miim_read, NULL}, 1118 /* Auto-negotiate */ 1119 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1120 /* Read the status */ 1121 {MIIM_88E1011_PHY_STATUS, miim_read, 1122 &mii_parse_88E1011_psr}, 1123 {miim_end,} 1124 }, 1125 (struct phy_cmd[]){ /* shutdown */ 1126 {miim_end,} 1127 }, 1128 }; 1129 1130 struct phy_info phy_info_M88E1118 = { 1131 0x01410e1, 1132 "Marvell 88E1118", 1133 4, 1134 (struct phy_cmd[]){ /* config */ 1135 /* Reset and configure the PHY */ 1136 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1137 {0x16, 0x0002, NULL}, /* Change Page Number */ 1138 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1139 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1140 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1141 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1142 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1143 {miim_end,} 1144 }, 1145 (struct phy_cmd[]){ /* startup */ 1146 {0x16, 0x0000, NULL}, /* Change Page Number */ 1147 /* Status is read once to clear old link state */ 1148 {MIIM_STATUS, miim_read, NULL}, 1149 /* Auto-negotiate */ 1150 /* Read the status */ 1151 {MIIM_88E1011_PHY_STATUS, miim_read, 1152 &mii_parse_88E1011_psr}, 1153 {miim_end,} 1154 }, 1155 (struct phy_cmd[]){ /* shutdown */ 1156 {miim_end,} 1157 }, 1158 }; 1159 1160 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1161 { 1162 uint mii_data = read_phy_reg(priv, mii_reg); 1163 1164 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1165 if (priv->flags & TSEC_REDUCED) 1166 return mii_data | 1167 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1168 else 1169 return mii_data; 1170 } 1171 1172 static struct phy_info phy_info_M88E1145 = { 1173 0x01410cd, 1174 "Marvell 88E1145", 1175 4, 1176 (struct phy_cmd[]){ /* config */ 1177 /* Reset the PHY */ 1178 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1179 1180 /* Errata E0, E1 */ 1181 {29, 0x001b, NULL}, 1182 {30, 0x418f, NULL}, 1183 {29, 0x0016, NULL}, 1184 {30, 0xa2da, NULL}, 1185 1186 /* Configure the PHY */ 1187 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1188 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1189 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, 1190 NULL}, 1191 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1192 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1193 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1194 {miim_end,} 1195 }, 1196 (struct phy_cmd[]){ /* startup */ 1197 /* Status is read once to clear old link state */ 1198 {MIIM_STATUS, miim_read, NULL}, 1199 /* Auto-negotiate */ 1200 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1201 {MIIM_88E1111_PHY_LED_CONTROL, 1202 MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1203 /* Read the Status */ 1204 {MIIM_88E1011_PHY_STATUS, miim_read, 1205 &mii_parse_88E1011_psr}, 1206 {miim_end,} 1207 }, 1208 (struct phy_cmd[]){ /* shutdown */ 1209 {miim_end,} 1210 }, 1211 }; 1212 1213 struct phy_info phy_info_cis8204 = { 1214 0x3f11, 1215 "Cicada Cis8204", 1216 6, 1217 (struct phy_cmd[]){ /* config */ 1218 /* Override PHY config settings */ 1219 {MIIM_CIS8201_AUX_CONSTAT, 1220 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1221 /* Configure some basic stuff */ 1222 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1223 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1224 &mii_cis8204_fixled}, 1225 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1226 &mii_cis8204_setmode}, 1227 {miim_end,} 1228 }, 1229 (struct phy_cmd[]){ /* startup */ 1230 /* Read the Status (2x to make sure link is right) */ 1231 {MIIM_STATUS, miim_read, NULL}, 1232 /* Auto-negotiate */ 1233 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1234 /* Read the status */ 1235 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1236 &mii_parse_cis8201}, 1237 {miim_end,} 1238 }, 1239 (struct phy_cmd[]){ /* shutdown */ 1240 {miim_end,} 1241 }, 1242 }; 1243 1244 /* Cicada 8201 */ 1245 struct phy_info phy_info_cis8201 = { 1246 0xfc41, 1247 "CIS8201", 1248 4, 1249 (struct phy_cmd[]){ /* config */ 1250 /* Override PHY config settings */ 1251 {MIIM_CIS8201_AUX_CONSTAT, 1252 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1253 /* Set up the interface mode */ 1254 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, 1255 NULL}, 1256 /* Configure some basic stuff */ 1257 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1258 {miim_end,} 1259 }, 1260 (struct phy_cmd[]){ /* startup */ 1261 /* Read the Status (2x to make sure link is right) */ 1262 {MIIM_STATUS, miim_read, NULL}, 1263 /* Auto-negotiate */ 1264 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1265 /* Read the status */ 1266 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1267 &mii_parse_cis8201}, 1268 {miim_end,} 1269 }, 1270 (struct phy_cmd[]){ /* shutdown */ 1271 {miim_end,} 1272 }, 1273 }; 1274 struct phy_info phy_info_VSC8244 = { 1275 0x3f1b, 1276 "Vitesse VSC8244", 1277 6, 1278 (struct phy_cmd[]){ /* config */ 1279 /* Override PHY config settings */ 1280 /* Configure some basic stuff */ 1281 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1282 {miim_end,} 1283 }, 1284 (struct phy_cmd[]){ /* startup */ 1285 /* Read the Status (2x to make sure link is right) */ 1286 {MIIM_STATUS, miim_read, NULL}, 1287 /* Auto-negotiate */ 1288 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1289 /* Read the status */ 1290 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1291 &mii_parse_vsc8244}, 1292 {miim_end,} 1293 }, 1294 (struct phy_cmd[]){ /* shutdown */ 1295 {miim_end,} 1296 }, 1297 }; 1298 1299 struct phy_info phy_info_VSC8601 = { 1300 0x00007042, 1301 "Vitesse VSC8601", 1302 4, 1303 (struct phy_cmd[]){ /* config */ 1304 /* Override PHY config settings */ 1305 /* Configure some basic stuff */ 1306 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1307 #ifdef CFG_VSC8601_SKEWFIX 1308 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1309 #if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX) 1310 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1311 #define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12) 1312 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1313 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1314 #endif 1315 #endif 1316 {miim_end,} 1317 }, 1318 (struct phy_cmd[]){ /* startup */ 1319 /* Read the Status (2x to make sure link is right) */ 1320 {MIIM_STATUS, miim_read, NULL}, 1321 /* Auto-negotiate */ 1322 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1323 /* Read the status */ 1324 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1325 &mii_parse_vsc8244}, 1326 {miim_end,} 1327 }, 1328 (struct phy_cmd[]){ /* shutdown */ 1329 {miim_end,} 1330 }, 1331 }; 1332 1333 1334 struct phy_info phy_info_dm9161 = { 1335 0x0181b88, 1336 "Davicom DM9161E", 1337 4, 1338 (struct phy_cmd[]){ /* config */ 1339 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1340 /* Do not bypass the scrambler/descrambler */ 1341 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1342 /* Clear 10BTCSR to default */ 1343 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, 1344 NULL}, 1345 /* Configure some basic stuff */ 1346 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1347 /* Restart Auto Negotiation */ 1348 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1349 {miim_end,} 1350 }, 1351 (struct phy_cmd[]){ /* startup */ 1352 /* Status is read once to clear old link state */ 1353 {MIIM_STATUS, miim_read, NULL}, 1354 /* Auto-negotiate */ 1355 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1356 /* Read the status */ 1357 {MIIM_DM9161_SCSR, miim_read, 1358 &mii_parse_dm9161_scsr}, 1359 {miim_end,} 1360 }, 1361 (struct phy_cmd[]){ /* shutdown */ 1362 {miim_end,} 1363 }, 1364 }; 1365 /* a generic flavor. */ 1366 struct phy_info phy_info_generic = { 1367 0, 1368 "Unknown/Generic PHY", 1369 32, 1370 (struct phy_cmd[]) { /* config */ 1371 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1372 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1373 {miim_end,} 1374 }, 1375 (struct phy_cmd[]) { /* startup */ 1376 {PHY_BMSR, miim_read, NULL}, 1377 {PHY_BMSR, miim_read, &mii_parse_sr}, 1378 {PHY_BMSR, miim_read, &mii_parse_link}, 1379 {miim_end,} 1380 }, 1381 (struct phy_cmd[]) { /* shutdown */ 1382 {miim_end,} 1383 } 1384 }; 1385 1386 1387 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1388 { 1389 unsigned int speed; 1390 if (priv->link) { 1391 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1392 1393 switch (speed) { 1394 case MIIM_LXT971_SR2_10HDX: 1395 priv->speed = 10; 1396 priv->duplexity = 0; 1397 break; 1398 case MIIM_LXT971_SR2_10FDX: 1399 priv->speed = 10; 1400 priv->duplexity = 1; 1401 break; 1402 case MIIM_LXT971_SR2_100HDX: 1403 priv->speed = 100; 1404 priv->duplexity = 0; 1405 break; 1406 default: 1407 priv->speed = 100; 1408 priv->duplexity = 1; 1409 } 1410 } else { 1411 priv->speed = 0; 1412 priv->duplexity = 0; 1413 } 1414 1415 return 0; 1416 } 1417 1418 static struct phy_info phy_info_lxt971 = { 1419 0x0001378e, 1420 "LXT971", 1421 4, 1422 (struct phy_cmd[]){ /* config */ 1423 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1424 {miim_end,} 1425 }, 1426 (struct phy_cmd[]){ /* startup - enable interrupts */ 1427 /* { 0x12, 0x00f2, NULL }, */ 1428 {MIIM_STATUS, miim_read, NULL}, 1429 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1430 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1431 {miim_end,} 1432 }, 1433 (struct phy_cmd[]){ /* shutdown - disable interrupts */ 1434 {miim_end,} 1435 }, 1436 }; 1437 1438 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1439 * information 1440 */ 1441 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1442 { 1443 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1444 1445 case MIIM_DP83865_SPD_1000: 1446 priv->speed = 1000; 1447 break; 1448 1449 case MIIM_DP83865_SPD_100: 1450 priv->speed = 100; 1451 break; 1452 1453 default: 1454 priv->speed = 10; 1455 break; 1456 1457 } 1458 1459 if (mii_reg & MIIM_DP83865_DPX_FULL) 1460 priv->duplexity = 1; 1461 else 1462 priv->duplexity = 0; 1463 1464 return 0; 1465 } 1466 1467 struct phy_info phy_info_dp83865 = { 1468 0x20005c7, 1469 "NatSemi DP83865", 1470 4, 1471 (struct phy_cmd[]){ /* config */ 1472 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1473 {miim_end,} 1474 }, 1475 (struct phy_cmd[]){ /* startup */ 1476 /* Status is read once to clear old link state */ 1477 {MIIM_STATUS, miim_read, NULL}, 1478 /* Auto-negotiate */ 1479 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1480 /* Read the link and auto-neg status */ 1481 {MIIM_DP83865_LANR, miim_read, 1482 &mii_parse_dp83865_lanr}, 1483 {miim_end,} 1484 }, 1485 (struct phy_cmd[]){ /* shutdown */ 1486 {miim_end,} 1487 }, 1488 }; 1489 1490 struct phy_info phy_info_rtl8211b = { 1491 0x001cc91, 1492 "RealTek RTL8211B", 1493 4, 1494 (struct phy_cmd[]){ /* config */ 1495 /* Reset and configure the PHY */ 1496 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1497 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1498 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1499 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1500 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1501 {miim_end,} 1502 }, 1503 (struct phy_cmd[]){ /* startup */ 1504 /* Status is read once to clear old link state */ 1505 {MIIM_STATUS, miim_read, NULL}, 1506 /* Auto-negotiate */ 1507 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1508 /* Read the status */ 1509 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1510 {miim_end,} 1511 }, 1512 (struct phy_cmd[]){ /* shutdown */ 1513 {miim_end,} 1514 }, 1515 }; 1516 1517 struct phy_info *phy_info[] = { 1518 &phy_info_cis8204, 1519 &phy_info_cis8201, 1520 &phy_info_BCM5461S, 1521 &phy_info_BCM5464S, 1522 &phy_info_M88E1011S, 1523 &phy_info_M88E1111S, 1524 &phy_info_M88E1118, 1525 &phy_info_M88E1145, 1526 &phy_info_M88E1149S, 1527 &phy_info_dm9161, 1528 &phy_info_lxt971, 1529 &phy_info_VSC8244, 1530 &phy_info_VSC8601, 1531 &phy_info_dp83865, 1532 &phy_info_rtl8211b, 1533 &phy_info_generic, 1534 NULL 1535 }; 1536 1537 /* Grab the identifier of the device's PHY, and search through 1538 * all of the known PHYs to see if one matches. If so, return 1539 * it, if not, return NULL 1540 */ 1541 struct phy_info *get_phy_info(struct eth_device *dev) 1542 { 1543 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1544 uint phy_reg, phy_ID; 1545 int i; 1546 struct phy_info *theInfo = NULL; 1547 1548 /* Grab the bits from PHYIR1, and put them in the upper half */ 1549 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1550 phy_ID = (phy_reg & 0xffff) << 16; 1551 1552 /* Grab the bits from PHYIR2, and put them in the lower half */ 1553 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1554 phy_ID |= (phy_reg & 0xffff); 1555 1556 /* loop through all the known PHY types, and find one that */ 1557 /* matches the ID we read from the PHY. */ 1558 for (i = 0; phy_info[i]; i++) { 1559 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1560 theInfo = phy_info[i]; 1561 break; 1562 } 1563 } 1564 1565 if (theInfo == NULL) { 1566 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); 1567 return NULL; 1568 } else { 1569 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1570 } 1571 1572 return theInfo; 1573 } 1574 1575 /* Execute the given series of commands on the given device's 1576 * PHY, running functions as necessary 1577 */ 1578 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1579 { 1580 int i; 1581 uint result; 1582 volatile tsec_t *phyregs = priv->phyregs; 1583 1584 phyregs->miimcfg = MIIMCFG_RESET; 1585 1586 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1587 1588 while (phyregs->miimind & MIIMIND_BUSY) ; 1589 1590 for (i = 0; cmd->mii_reg != miim_end; i++) { 1591 if (cmd->mii_data == miim_read) { 1592 result = read_phy_reg(priv, cmd->mii_reg); 1593 1594 if (cmd->funct != NULL) 1595 (*(cmd->funct)) (result, priv); 1596 1597 } else { 1598 if (cmd->funct != NULL) 1599 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1600 else 1601 result = cmd->mii_data; 1602 1603 write_phy_reg(priv, cmd->mii_reg, result); 1604 1605 } 1606 cmd++; 1607 } 1608 } 1609 1610 /* Relocate the function pointers in the phy cmd lists */ 1611 static void relocate_cmds(void) 1612 { 1613 struct phy_cmd **cmdlistptr; 1614 struct phy_cmd *cmd; 1615 int i, j, k; 1616 1617 for (i = 0; phy_info[i]; i++) { 1618 /* First thing's first: relocate the pointers to the 1619 * PHY command structures (the structs were done) */ 1620 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 1621 + gd->reloc_off); 1622 phy_info[i]->name += gd->reloc_off; 1623 phy_info[i]->config = 1624 (struct phy_cmd *)((uint) phy_info[i]->config 1625 + gd->reloc_off); 1626 phy_info[i]->startup = 1627 (struct phy_cmd *)((uint) phy_info[i]->startup 1628 + gd->reloc_off); 1629 phy_info[i]->shutdown = 1630 (struct phy_cmd *)((uint) phy_info[i]->shutdown 1631 + gd->reloc_off); 1632 1633 cmdlistptr = &phy_info[i]->config; 1634 j = 0; 1635 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { 1636 k = 0; 1637 for (cmd = *cmdlistptr; 1638 cmd->mii_reg != miim_end; 1639 cmd++) { 1640 /* Only relocate non-NULL pointers */ 1641 if (cmd->funct) 1642 cmd->funct += gd->reloc_off; 1643 1644 k++; 1645 } 1646 j++; 1647 } 1648 } 1649 1650 relocated = 1; 1651 } 1652 1653 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1654 && !defined(BITBANGMII) 1655 1656 /* 1657 * Read a MII PHY register. 1658 * 1659 * Returns: 1660 * 0 on success 1661 */ 1662 static int tsec_miiphy_read(char *devname, unsigned char addr, 1663 unsigned char reg, unsigned short *value) 1664 { 1665 unsigned short ret; 1666 struct tsec_private *priv = privlist[0]; 1667 1668 if (NULL == priv) { 1669 printf("Can't read PHY at address %d\n", addr); 1670 return -1; 1671 } 1672 1673 ret = (unsigned short)read_any_phy_reg(priv, addr, reg); 1674 *value = ret; 1675 1676 return 0; 1677 } 1678 1679 /* 1680 * Write a MII PHY register. 1681 * 1682 * Returns: 1683 * 0 on success 1684 */ 1685 static int tsec_miiphy_write(char *devname, unsigned char addr, 1686 unsigned char reg, unsigned short value) 1687 { 1688 struct tsec_private *priv = privlist[0]; 1689 1690 if (NULL == priv) { 1691 printf("Can't write PHY at address %d\n", addr); 1692 return -1; 1693 } 1694 1695 write_any_phy_reg(priv, addr, reg, value); 1696 1697 return 0; 1698 } 1699 1700 #endif 1701 1702 #ifdef CONFIG_MCAST_TFTP 1703 1704 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1705 1706 /* Set the appropriate hash bit for the given addr */ 1707 1708 /* The algorithm works like so: 1709 * 1) Take the Destination Address (ie the multicast address), and 1710 * do a CRC on it (little endian), and reverse the bits of the 1711 * result. 1712 * 2) Use the 8 most significant bits as a hash into a 256-entry 1713 * table. The table is controlled through 8 32-bit registers: 1714 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1715 * gaddr7. This means that the 3 most significant bits in the 1716 * hash index which gaddr register to use, and the 5 other bits 1717 * indicate which bit (assuming an IBM numbering scheme, which 1718 * for PowerPC (tm) is usually the case) in the tregister holds 1719 * the entry. */ 1720 static int 1721 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1722 { 1723 struct tsec_private *priv = privlist[1]; 1724 volatile tsec_t *regs = priv->regs; 1725 volatile u32 *reg_array, value; 1726 u8 result, whichbit, whichreg; 1727 1728 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1729 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1730 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1731 value = (1 << (31-whichbit)); 1732 1733 reg_array = &(regs->hash.gaddr0); 1734 1735 if (set) { 1736 reg_array[whichreg] |= value; 1737 } else { 1738 reg_array[whichreg] &= ~value; 1739 } 1740 return 0; 1741 } 1742 #endif /* Multicast TFTP ? */ 1743