1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. All rights reserved. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 21 #include "miiphy.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define TX_BUF_CNT 2 26 27 static uint rxIdx; /* index of the current RX buffer */ 28 static uint txIdx; /* index of the current TX buffer */ 29 30 typedef volatile struct rtxbd { 31 txbd8_t txbd[TX_BUF_CNT]; 32 rxbd8_t rxbd[PKTBUFSRX]; 33 } RTXBD; 34 35 #define MAXCONTROLLERS (8) 36 37 static int relocated = 0; 38 39 static struct tsec_private *privlist[MAXCONTROLLERS]; 40 static int num_tsecs = 0; 41 42 #ifdef __GNUC__ 43 static RTXBD rtx __attribute__ ((aligned(8))); 44 #else 45 #error "rtx must be 64-bit aligned" 46 #endif 47 48 static int tsec_send(struct eth_device *dev, 49 volatile void *packet, int length); 50 static int tsec_recv(struct eth_device *dev); 51 static int tsec_init(struct eth_device *dev, bd_t * bd); 52 static void tsec_halt(struct eth_device *dev); 53 static void init_registers(volatile tsec_t * regs); 54 static void startup_tsec(struct eth_device *dev); 55 static int init_phy(struct eth_device *dev); 56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 57 uint read_phy_reg(struct tsec_private *priv, uint regnum); 58 struct phy_info *get_phy_info(struct eth_device *dev); 59 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 60 static void adjust_link(struct eth_device *dev); 61 static void relocate_cmds(void); 62 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 63 && !defined(BITBANGMII) 64 static int tsec_miiphy_write(char *devname, unsigned char addr, 65 unsigned char reg, unsigned short value); 66 static int tsec_miiphy_read(char *devname, unsigned char addr, 67 unsigned char reg, unsigned short *value); 68 #endif 69 #ifdef CONFIG_MCAST_TFTP 70 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 71 #endif 72 73 /* Default initializations for TSEC controllers. */ 74 75 static struct tsec_info_struct tsec_info[] = { 76 #ifdef CONFIG_TSEC1 77 STD_TSEC_INFO(1), /* TSEC1 */ 78 #endif 79 #ifdef CONFIG_TSEC2 80 STD_TSEC_INFO(2), /* TSEC2 */ 81 #endif 82 #ifdef CONFIG_MPC85XX_FEC 83 { 84 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 85 .miiregs = (tsec_t *)(TSEC_BASE_ADDR), 86 .devname = CONFIG_MPC85XX_FEC_NAME, 87 .phyaddr = FEC_PHY_ADDR, 88 .flags = FEC_FLAGS 89 }, /* FEC */ 90 #endif 91 #ifdef CONFIG_TSEC3 92 STD_TSEC_INFO(3), /* TSEC3 */ 93 #endif 94 #ifdef CONFIG_TSEC4 95 STD_TSEC_INFO(4), /* TSEC4 */ 96 #endif 97 }; 98 99 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 100 { 101 int i; 102 103 for (i = 0; i < num; i++) 104 tsec_initialize(bis, &tsecs[i]); 105 106 return 0; 107 } 108 109 int tsec_standard_init(bd_t *bis) 110 { 111 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 112 } 113 114 /* Initialize device structure. Returns success if PHY 115 * initialization succeeded (i.e. if it recognizes the PHY) 116 */ 117 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) 118 { 119 struct eth_device *dev; 120 int i; 121 struct tsec_private *priv; 122 123 dev = (struct eth_device *)malloc(sizeof *dev); 124 125 if (NULL == dev) 126 return 0; 127 128 memset(dev, 0, sizeof *dev); 129 130 priv = (struct tsec_private *)malloc(sizeof(*priv)); 131 132 if (NULL == priv) 133 return 0; 134 135 privlist[num_tsecs++] = priv; 136 priv->regs = tsec_info->regs; 137 priv->phyregs = tsec_info->miiregs; 138 139 priv->phyaddr = tsec_info->phyaddr; 140 priv->flags = tsec_info->flags; 141 142 sprintf(dev->name, tsec_info->devname); 143 dev->iobase = 0; 144 dev->priv = priv; 145 dev->init = tsec_init; 146 dev->halt = tsec_halt; 147 dev->send = tsec_send; 148 dev->recv = tsec_recv; 149 #ifdef CONFIG_MCAST_TFTP 150 dev->mcast = tsec_mcast_addr; 151 #endif 152 153 /* Tell u-boot to get the addr from the env */ 154 for (i = 0; i < 6; i++) 155 dev->enetaddr[i] = 0; 156 157 eth_register(dev); 158 159 /* Reset the MAC */ 160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 161 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ 162 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 163 164 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 165 && !defined(BITBANGMII) 166 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 167 #endif 168 169 /* Try to initialize PHY here, and return */ 170 return init_phy(dev); 171 } 172 173 /* Initializes data structures and registers for the controller, 174 * and brings the interface up. Returns the link status, meaning 175 * that it returns success if the link is up, failure otherwise. 176 * This allows u-boot to find the first active controller. 177 */ 178 int tsec_init(struct eth_device *dev, bd_t * bd) 179 { 180 uint tempval; 181 char tmpbuf[MAC_ADDR_LEN]; 182 int i; 183 struct tsec_private *priv = (struct tsec_private *)dev->priv; 184 volatile tsec_t *regs = priv->regs; 185 186 /* Make sure the controller is stopped */ 187 tsec_halt(dev); 188 189 /* Init MACCFG2. Defaults to GMII */ 190 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 191 192 /* Init ECNTRL */ 193 regs->ecntrl = ECNTRL_INIT_SETTINGS; 194 195 /* Copy the station address into the address registers. 196 * Backwards, because little endian MACS are dumb */ 197 for (i = 0; i < MAC_ADDR_LEN; i++) { 198 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 199 } 200 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | 201 tmpbuf[3]; 202 203 regs->macstnaddr1 = tempval; 204 205 tempval = *((uint *) (tmpbuf + 4)); 206 207 regs->macstnaddr2 = tempval; 208 209 /* reset the indices to zero */ 210 rxIdx = 0; 211 txIdx = 0; 212 213 /* Clear out (for the most part) the other registers */ 214 init_registers(regs); 215 216 /* Ready the device for tx/rx */ 217 startup_tsec(dev); 218 219 /* If there's no link, fail */ 220 return (priv->link ? 0 : -1); 221 } 222 223 /* Writes the given phy's reg with value, using the specified MDIO regs */ 224 static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, 225 uint reg, uint value) 226 { 227 int timeout = 1000000; 228 229 phyregs->miimadd = (addr << 8) | reg; 230 phyregs->miimcon = value; 231 asm("sync"); 232 233 timeout = 1000000; 234 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ; 235 } 236 237 238 /* Provide the default behavior of writing the PHY of this ethernet device */ 239 #define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) 240 241 /* Reads register regnum on the device's PHY through the 242 * specified registers. It lowers and raises the read 243 * command, and waits for the data to become valid (miimind 244 * notvalid bit cleared), and the bus to cease activity (miimind 245 * busy bit cleared), and then returns the value 246 */ 247 uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) 248 { 249 uint value; 250 251 /* Put the address of the phy, and the register 252 * number into MIIMADD */ 253 phyregs->miimadd = (phyid << 8) | regnum; 254 255 /* Clear the command register, and wait */ 256 phyregs->miimcom = 0; 257 asm("sync"); 258 259 /* Initiate a read command, and wait */ 260 phyregs->miimcom = MIIM_READ_COMMAND; 261 asm("sync"); 262 263 /* Wait for the the indication that the read is done */ 264 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 265 266 /* Grab the value read from the PHY */ 267 value = phyregs->miimstat; 268 269 return value; 270 } 271 272 /* #define to provide old read_phy_reg functionality without duplicating code */ 273 #define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) 274 275 #define TBIANA_SETTINGS ( \ 276 TBIANA_ASYMMETRIC_PAUSE \ 277 | TBIANA_SYMMETRIC_PAUSE \ 278 | TBIANA_FULL_DUPLEX \ 279 ) 280 281 #define TBICR_SETTINGS ( \ 282 TBICR_PHY_RESET \ 283 | TBICR_ANEG_ENABLE \ 284 | TBICR_FULL_DUPLEX \ 285 | TBICR_SPEED1_SET \ 286 ) 287 /* Configure the TBI for SGMII operation */ 288 static void tsec_configure_serdes(struct tsec_private *priv) 289 { 290 /* Access TBI PHY registers at given TSEC register offset as opposed to the 291 * register offset used for external PHY accesses */ 292 tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, 293 TBIANA_SETTINGS); 294 tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, 295 TBICON_CLK_SELECT); 296 tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, 297 TBICR_SETTINGS); 298 } 299 300 /* Discover which PHY is attached to the device, and configure it 301 * properly. If the PHY is not recognized, then return 0 302 * (failure). Otherwise, return 1 303 */ 304 static int init_phy(struct eth_device *dev) 305 { 306 struct tsec_private *priv = (struct tsec_private *)dev->priv; 307 struct phy_info *curphy; 308 volatile tsec_t *phyregs = priv->phyregs; 309 volatile tsec_t *regs = priv->regs; 310 311 /* Assign a Physical address to the TBI */ 312 regs->tbipa = CONFIG_SYS_TBIPA_VALUE; 313 phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE; 314 asm("sync"); 315 316 /* Reset MII (due to new addresses) */ 317 priv->phyregs->miimcfg = MIIMCFG_RESET; 318 asm("sync"); 319 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 320 asm("sync"); 321 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 322 323 if (0 == relocated) 324 relocate_cmds(); 325 326 /* Get the cmd structure corresponding to the attached 327 * PHY */ 328 curphy = get_phy_info(dev); 329 330 if (curphy == NULL) { 331 priv->phyinfo = NULL; 332 printf("%s: No PHY found\n", dev->name); 333 334 return 0; 335 } 336 337 if (regs->ecntrl & ECNTRL_SGMII_MODE) 338 tsec_configure_serdes(priv); 339 340 priv->phyinfo = curphy; 341 342 phy_run_commands(priv, priv->phyinfo->config); 343 344 return 1; 345 } 346 347 /* 348 * Returns which value to write to the control register. 349 * For 10/100, the value is slightly different 350 */ 351 uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 352 { 353 if (priv->flags & TSEC_GIGABIT) 354 return MIIM_CONTROL_INIT; 355 else 356 return MIIM_CR_INIT; 357 } 358 359 /* Parse the status register for link, and then do 360 * auto-negotiation 361 */ 362 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 363 { 364 /* 365 * Wait if the link is up, and autonegotiation is in progress 366 * (ie - we're capable and it's not done) 367 */ 368 mii_reg = read_phy_reg(priv, MIIM_STATUS); 369 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) 370 && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 371 int i = 0; 372 373 puts("Waiting for PHY auto negotiation to complete"); 374 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 375 /* 376 * Timeout reached ? 377 */ 378 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 379 puts(" TIMEOUT !\n"); 380 priv->link = 0; 381 return 0; 382 } 383 384 if ((i++ % 1000) == 0) { 385 putc('.'); 386 } 387 udelay(1000); /* 1 ms */ 388 mii_reg = read_phy_reg(priv, MIIM_STATUS); 389 } 390 puts(" done\n"); 391 priv->link = 1; 392 udelay(500000); /* another 500 ms (results in faster booting) */ 393 } else { 394 if (mii_reg & MIIM_STATUS_LINK) 395 priv->link = 1; 396 else 397 priv->link = 0; 398 } 399 400 return 0; 401 } 402 403 /* Generic function which updates the speed and duplex. If 404 * autonegotiation is enabled, it uses the AND of the link 405 * partner's advertised capabilities and our advertised 406 * capabilities. If autonegotiation is disabled, we use the 407 * appropriate bits in the control register. 408 * 409 * Stolen from Linux's mii.c and phy_device.c 410 */ 411 uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 412 { 413 /* We're using autonegotiation */ 414 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 415 uint lpa = 0; 416 uint gblpa = 0; 417 418 /* Check for gigabit capability */ 419 if (mii_reg & PHY_BMSR_EXT) { 420 /* We want a list of states supported by 421 * both PHYs in the link 422 */ 423 gblpa = read_phy_reg(priv, PHY_1000BTSR); 424 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 425 } 426 427 /* Set the baseline so we only have to set them 428 * if they're different 429 */ 430 priv->speed = 10; 431 priv->duplexity = 0; 432 433 /* Check the gigabit fields */ 434 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 435 priv->speed = 1000; 436 437 if (gblpa & PHY_1000BTSR_1000FD) 438 priv->duplexity = 1; 439 440 /* We're done! */ 441 return 0; 442 } 443 444 lpa = read_phy_reg(priv, PHY_ANAR); 445 lpa &= read_phy_reg(priv, PHY_ANLPAR); 446 447 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 448 priv->speed = 100; 449 450 if (lpa & PHY_ANLPAR_TXFD) 451 priv->duplexity = 1; 452 453 } else if (lpa & PHY_ANLPAR_10FD) 454 priv->duplexity = 1; 455 } else { 456 uint bmcr = read_phy_reg(priv, PHY_BMCR); 457 458 priv->speed = 10; 459 priv->duplexity = 0; 460 461 if (bmcr & PHY_BMCR_DPLX) 462 priv->duplexity = 1; 463 464 if (bmcr & PHY_BMCR_1000_MBPS) 465 priv->speed = 1000; 466 else if (bmcr & PHY_BMCR_100_MBPS) 467 priv->speed = 100; 468 } 469 470 return 0; 471 } 472 473 /* 474 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain 475 * circumstances. eg a gigabit TSEC connected to a gigabit switch with 476 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't 477 * link. "Ethernet@Wirespeed" reduces advertised speed until link 478 * can be achieved. 479 */ 480 uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) 481 { 482 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010; 483 } 484 485 /* 486 * Parse the BCM54xx status register for speed and duplex information. 487 * The linux sungem_phy has this information, but in a table format. 488 */ 489 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 490 { 491 492 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ 493 494 case 1: 495 printf("Enet starting in 10BT/HD\n"); 496 priv->duplexity = 0; 497 priv->speed = 10; 498 break; 499 500 case 2: 501 printf("Enet starting in 10BT/FD\n"); 502 priv->duplexity = 1; 503 priv->speed = 10; 504 break; 505 506 case 3: 507 printf("Enet starting in 100BT/HD\n"); 508 priv->duplexity = 0; 509 priv->speed = 100; 510 break; 511 512 case 5: 513 printf("Enet starting in 100BT/FD\n"); 514 priv->duplexity = 1; 515 priv->speed = 100; 516 break; 517 518 case 6: 519 printf("Enet starting in 1000BT/HD\n"); 520 priv->duplexity = 0; 521 priv->speed = 1000; 522 break; 523 524 case 7: 525 printf("Enet starting in 1000BT/FD\n"); 526 priv->duplexity = 1; 527 priv->speed = 1000; 528 break; 529 530 default: 531 printf("Auto-neg error, defaulting to 10BT/HD\n"); 532 priv->duplexity = 0; 533 priv->speed = 10; 534 break; 535 } 536 537 return 0; 538 539 } 540 /* Parse the 88E1011's status register for speed and duplex 541 * information 542 */ 543 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 544 { 545 uint speed; 546 547 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 548 549 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 550 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 551 int i = 0; 552 553 puts("Waiting for PHY realtime link"); 554 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 555 /* Timeout reached ? */ 556 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 557 puts(" TIMEOUT !\n"); 558 priv->link = 0; 559 break; 560 } 561 562 if ((i++ % 1000) == 0) { 563 putc('.'); 564 } 565 udelay(1000); /* 1 ms */ 566 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 567 } 568 puts(" done\n"); 569 udelay(500000); /* another 500 ms (results in faster booting) */ 570 } else { 571 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 572 priv->link = 1; 573 else 574 priv->link = 0; 575 } 576 577 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 578 priv->duplexity = 1; 579 else 580 priv->duplexity = 0; 581 582 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 583 584 switch (speed) { 585 case MIIM_88E1011_PHYSTAT_GBIT: 586 priv->speed = 1000; 587 break; 588 case MIIM_88E1011_PHYSTAT_100: 589 priv->speed = 100; 590 break; 591 default: 592 priv->speed = 10; 593 } 594 595 return 0; 596 } 597 598 /* Parse the RTL8211B's status register for speed and duplex 599 * information 600 */ 601 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 602 { 603 uint speed; 604 605 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 606 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 607 int i = 0; 608 609 /* in case of timeout ->link is cleared */ 610 priv->link = 1; 611 puts("Waiting for PHY realtime link"); 612 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 613 /* Timeout reached ? */ 614 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 615 puts(" TIMEOUT !\n"); 616 priv->link = 0; 617 break; 618 } 619 620 if ((i++ % 1000) == 0) { 621 putc('.'); 622 } 623 udelay(1000); /* 1 ms */ 624 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 625 } 626 puts(" done\n"); 627 udelay(500000); /* another 500 ms (results in faster booting) */ 628 } else { 629 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 630 priv->link = 1; 631 else 632 priv->link = 0; 633 } 634 635 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 636 priv->duplexity = 1; 637 else 638 priv->duplexity = 0; 639 640 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 641 642 switch (speed) { 643 case MIIM_RTL8211B_PHYSTAT_GBIT: 644 priv->speed = 1000; 645 break; 646 case MIIM_RTL8211B_PHYSTAT_100: 647 priv->speed = 100; 648 break; 649 default: 650 priv->speed = 10; 651 } 652 653 return 0; 654 } 655 656 /* Parse the cis8201's status register for speed and duplex 657 * information 658 */ 659 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 660 { 661 uint speed; 662 663 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 664 priv->duplexity = 1; 665 else 666 priv->duplexity = 0; 667 668 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 669 switch (speed) { 670 case MIIM_CIS8201_AUXCONSTAT_GBIT: 671 priv->speed = 1000; 672 break; 673 case MIIM_CIS8201_AUXCONSTAT_100: 674 priv->speed = 100; 675 break; 676 default: 677 priv->speed = 10; 678 break; 679 } 680 681 return 0; 682 } 683 684 /* Parse the vsc8244's status register for speed and duplex 685 * information 686 */ 687 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 688 { 689 uint speed; 690 691 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 692 priv->duplexity = 1; 693 else 694 priv->duplexity = 0; 695 696 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 697 switch (speed) { 698 case MIIM_VSC8244_AUXCONSTAT_GBIT: 699 priv->speed = 1000; 700 break; 701 case MIIM_VSC8244_AUXCONSTAT_100: 702 priv->speed = 100; 703 break; 704 default: 705 priv->speed = 10; 706 break; 707 } 708 709 return 0; 710 } 711 712 /* Parse the DM9161's status register for speed and duplex 713 * information 714 */ 715 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 716 { 717 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 718 priv->speed = 100; 719 else 720 priv->speed = 10; 721 722 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 723 priv->duplexity = 1; 724 else 725 priv->duplexity = 0; 726 727 return 0; 728 } 729 730 /* 731 * Hack to write all 4 PHYs with the LED values 732 */ 733 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 734 { 735 uint phyid; 736 volatile tsec_t *regbase = priv->phyregs; 737 int timeout = 1000000; 738 739 for (phyid = 0; phyid < 4; phyid++) { 740 regbase->miimadd = (phyid << 8) | mii_reg; 741 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 742 asm("sync"); 743 744 timeout = 1000000; 745 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 746 } 747 748 return MIIM_CIS8204_SLEDCON_INIT; 749 } 750 751 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 752 { 753 if (priv->flags & TSEC_REDUCED) 754 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 755 else 756 return MIIM_CIS8204_EPHYCON_INIT; 757 } 758 759 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 760 { 761 uint mii_data = read_phy_reg(priv, mii_reg); 762 763 if (priv->flags & TSEC_REDUCED) 764 mii_data = (mii_data & 0xfff0) | 0x000b; 765 return mii_data; 766 } 767 768 /* Initialized required registers to appropriate values, zeroing 769 * those we don't care about (unless zero is bad, in which case, 770 * choose a more appropriate value) 771 */ 772 static void init_registers(volatile tsec_t * regs) 773 { 774 /* Clear IEVENT */ 775 regs->ievent = IEVENT_INIT_CLEAR; 776 777 regs->imask = IMASK_INIT_CLEAR; 778 779 regs->hash.iaddr0 = 0; 780 regs->hash.iaddr1 = 0; 781 regs->hash.iaddr2 = 0; 782 regs->hash.iaddr3 = 0; 783 regs->hash.iaddr4 = 0; 784 regs->hash.iaddr5 = 0; 785 regs->hash.iaddr6 = 0; 786 regs->hash.iaddr7 = 0; 787 788 regs->hash.gaddr0 = 0; 789 regs->hash.gaddr1 = 0; 790 regs->hash.gaddr2 = 0; 791 regs->hash.gaddr3 = 0; 792 regs->hash.gaddr4 = 0; 793 regs->hash.gaddr5 = 0; 794 regs->hash.gaddr6 = 0; 795 regs->hash.gaddr7 = 0; 796 797 regs->rctrl = 0x00000000; 798 799 /* Init RMON mib registers */ 800 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 801 802 regs->rmon.cam1 = 0xffffffff; 803 regs->rmon.cam2 = 0xffffffff; 804 805 regs->mrblr = MRBLR_INIT_SETTINGS; 806 807 regs->minflr = MINFLR_INIT_SETTINGS; 808 809 regs->attr = ATTR_INIT_SETTINGS; 810 regs->attreli = ATTRELI_INIT_SETTINGS; 811 812 } 813 814 /* Configure maccfg2 based on negotiated speed and duplex 815 * reported by PHY handling code 816 */ 817 static void adjust_link(struct eth_device *dev) 818 { 819 struct tsec_private *priv = (struct tsec_private *)dev->priv; 820 volatile tsec_t *regs = priv->regs; 821 822 if (priv->link) { 823 if (priv->duplexity != 0) 824 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 825 else 826 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 827 828 switch (priv->speed) { 829 case 1000: 830 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 831 | MACCFG2_GMII); 832 break; 833 case 100: 834 case 10: 835 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 836 | MACCFG2_MII); 837 838 /* Set R100 bit in all modes although 839 * it is only used in RGMII mode 840 */ 841 if (priv->speed == 100) 842 regs->ecntrl |= ECNTRL_R100; 843 else 844 regs->ecntrl &= ~(ECNTRL_R100); 845 break; 846 default: 847 printf("%s: Speed was bad\n", dev->name); 848 break; 849 } 850 851 printf("Speed: %d, %s duplex\n", priv->speed, 852 (priv->duplexity) ? "full" : "half"); 853 854 } else { 855 printf("%s: No link.\n", dev->name); 856 } 857 } 858 859 /* Set up the buffers and their descriptors, and bring up the 860 * interface 861 */ 862 static void startup_tsec(struct eth_device *dev) 863 { 864 int i; 865 struct tsec_private *priv = (struct tsec_private *)dev->priv; 866 volatile tsec_t *regs = priv->regs; 867 868 /* Point to the buffer descriptors */ 869 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 870 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 871 872 /* Initialize the Rx Buffer descriptors */ 873 for (i = 0; i < PKTBUFSRX; i++) { 874 rtx.rxbd[i].status = RXBD_EMPTY; 875 rtx.rxbd[i].length = 0; 876 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 877 } 878 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 879 880 /* Initialize the TX Buffer Descriptors */ 881 for (i = 0; i < TX_BUF_CNT; i++) { 882 rtx.txbd[i].status = 0; 883 rtx.txbd[i].length = 0; 884 rtx.txbd[i].bufPtr = 0; 885 } 886 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 887 888 /* Start up the PHY */ 889 if(priv->phyinfo) 890 phy_run_commands(priv, priv->phyinfo->startup); 891 892 adjust_link(dev); 893 894 /* Enable Transmit and Receive */ 895 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 896 897 /* Tell the DMA it is clear to go */ 898 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 899 regs->tstat = TSTAT_CLEAR_THALT; 900 regs->rstat = RSTAT_CLEAR_RHALT; 901 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 902 } 903 904 /* This returns the status bits of the device. The return value 905 * is never checked, and this is what the 8260 driver did, so we 906 * do the same. Presumably, this would be zero if there were no 907 * errors 908 */ 909 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 910 { 911 int i; 912 int result = 0; 913 struct tsec_private *priv = (struct tsec_private *)dev->priv; 914 volatile tsec_t *regs = priv->regs; 915 916 /* Find an empty buffer descriptor */ 917 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 918 if (i >= TOUT_LOOP) { 919 debug("%s: tsec: tx buffers full\n", dev->name); 920 return result; 921 } 922 } 923 924 rtx.txbd[txIdx].bufPtr = (uint) packet; 925 rtx.txbd[txIdx].length = length; 926 rtx.txbd[txIdx].status |= 927 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 928 929 /* Tell the DMA to go */ 930 regs->tstat = TSTAT_CLEAR_THALT; 931 932 /* Wait for buffer to be transmitted */ 933 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 934 if (i >= TOUT_LOOP) { 935 debug("%s: tsec: tx error\n", dev->name); 936 return result; 937 } 938 } 939 940 txIdx = (txIdx + 1) % TX_BUF_CNT; 941 result = rtx.txbd[txIdx].status & TXBD_STATS; 942 943 return result; 944 } 945 946 static int tsec_recv(struct eth_device *dev) 947 { 948 int length; 949 struct tsec_private *priv = (struct tsec_private *)dev->priv; 950 volatile tsec_t *regs = priv->regs; 951 952 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 953 954 length = rtx.rxbd[rxIdx].length; 955 956 /* Send the packet up if there were no errors */ 957 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 958 NetReceive(NetRxPackets[rxIdx], length - 4); 959 } else { 960 printf("Got error %x\n", 961 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 962 } 963 964 rtx.rxbd[rxIdx].length = 0; 965 966 /* Set the wrap bit if this is the last element in the list */ 967 rtx.rxbd[rxIdx].status = 968 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 969 970 rxIdx = (rxIdx + 1) % PKTBUFSRX; 971 } 972 973 if (regs->ievent & IEVENT_BSY) { 974 regs->ievent = IEVENT_BSY; 975 regs->rstat = RSTAT_CLEAR_RHALT; 976 } 977 978 return -1; 979 980 } 981 982 /* Stop the interface */ 983 static void tsec_halt(struct eth_device *dev) 984 { 985 struct tsec_private *priv = (struct tsec_private *)dev->priv; 986 volatile tsec_t *regs = priv->regs; 987 988 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 989 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 990 991 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 992 993 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 994 995 /* Shut down the PHY, as needed */ 996 if(priv->phyinfo) 997 phy_run_commands(priv, priv->phyinfo->shutdown); 998 } 999 1000 struct phy_info phy_info_M88E1149S = { 1001 0x1410ca, 1002 "Marvell 88E1149S", 1003 4, 1004 (struct phy_cmd[]){ /* config */ 1005 /* Reset and configure the PHY */ 1006 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1007 {0x1d, 0x1f, NULL}, 1008 {0x1e, 0x200c, NULL}, 1009 {0x1d, 0x5, NULL}, 1010 {0x1e, 0x0, NULL}, 1011 {0x1e, 0x100, NULL}, 1012 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1013 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1014 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1015 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1016 {miim_end,} 1017 }, 1018 (struct phy_cmd[]){ /* startup */ 1019 /* Status is read once to clear old link state */ 1020 {MIIM_STATUS, miim_read, NULL}, 1021 /* Auto-negotiate */ 1022 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1023 /* Read the status */ 1024 {MIIM_88E1011_PHY_STATUS, miim_read, 1025 &mii_parse_88E1011_psr}, 1026 {miim_end,} 1027 }, 1028 (struct phy_cmd[]){ /* shutdown */ 1029 {miim_end,} 1030 }, 1031 }; 1032 1033 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1034 struct phy_info phy_info_BCM5461S = { 1035 0x02060c1, /* 5461 ID */ 1036 "Broadcom BCM5461S", 1037 0, /* not clear to me what minor revisions we can shift away */ 1038 (struct phy_cmd[]) { /* config */ 1039 /* Reset and configure the PHY */ 1040 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1041 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1042 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1043 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1044 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1045 {miim_end,} 1046 }, 1047 (struct phy_cmd[]) { /* startup */ 1048 /* Status is read once to clear old link state */ 1049 {MIIM_STATUS, miim_read, NULL}, 1050 /* Auto-negotiate */ 1051 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1052 /* Read the status */ 1053 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1054 {miim_end,} 1055 }, 1056 (struct phy_cmd[]) { /* shutdown */ 1057 {miim_end,} 1058 }, 1059 }; 1060 1061 struct phy_info phy_info_BCM5464S = { 1062 0x02060b1, /* 5464 ID */ 1063 "Broadcom BCM5464S", 1064 0, /* not clear to me what minor revisions we can shift away */ 1065 (struct phy_cmd[]) { /* config */ 1066 /* Reset and configure the PHY */ 1067 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1068 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1069 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1070 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1071 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1072 {miim_end,} 1073 }, 1074 (struct phy_cmd[]) { /* startup */ 1075 /* Status is read once to clear old link state */ 1076 {MIIM_STATUS, miim_read, NULL}, 1077 /* Auto-negotiate */ 1078 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1079 /* Read the status */ 1080 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1081 {miim_end,} 1082 }, 1083 (struct phy_cmd[]) { /* shutdown */ 1084 {miim_end,} 1085 }, 1086 }; 1087 1088 struct phy_info phy_info_BCM5482S = { 1089 0x0143bcb, 1090 "Broadcom BCM5482S", 1091 4, 1092 (struct phy_cmd[]) { /* config */ 1093 /* Reset and configure the PHY */ 1094 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1095 /* Setup read from auxilary control shadow register 7 */ 1096 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL}, 1097 /* Read Misc Control register and or in Ethernet@Wirespeed */ 1098 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed}, 1099 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1100 {miim_end,} 1101 }, 1102 (struct phy_cmd[]) { /* startup */ 1103 /* Status is read once to clear old link state */ 1104 {MIIM_STATUS, miim_read, NULL}, 1105 /* Auto-negotiate */ 1106 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1107 /* Read the status */ 1108 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1109 {miim_end,} 1110 }, 1111 (struct phy_cmd[]) { /* shutdown */ 1112 {miim_end,} 1113 }, 1114 }; 1115 1116 struct phy_info phy_info_M88E1011S = { 1117 0x01410c6, 1118 "Marvell 88E1011S", 1119 4, 1120 (struct phy_cmd[]){ /* config */ 1121 /* Reset and configure the PHY */ 1122 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1123 {0x1d, 0x1f, NULL}, 1124 {0x1e, 0x200c, NULL}, 1125 {0x1d, 0x5, NULL}, 1126 {0x1e, 0x0, NULL}, 1127 {0x1e, 0x100, NULL}, 1128 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1129 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1130 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1131 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1132 {miim_end,} 1133 }, 1134 (struct phy_cmd[]){ /* startup */ 1135 /* Status is read once to clear old link state */ 1136 {MIIM_STATUS, miim_read, NULL}, 1137 /* Auto-negotiate */ 1138 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1139 /* Read the status */ 1140 {MIIM_88E1011_PHY_STATUS, miim_read, 1141 &mii_parse_88E1011_psr}, 1142 {miim_end,} 1143 }, 1144 (struct phy_cmd[]){ /* shutdown */ 1145 {miim_end,} 1146 }, 1147 }; 1148 1149 struct phy_info phy_info_M88E1111S = { 1150 0x01410cc, 1151 "Marvell 88E1111S", 1152 4, 1153 (struct phy_cmd[]){ /* config */ 1154 /* Reset and configure the PHY */ 1155 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1156 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1157 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1158 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1159 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1160 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1161 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1162 {miim_end,} 1163 }, 1164 (struct phy_cmd[]){ /* startup */ 1165 /* Status is read once to clear old link state */ 1166 {MIIM_STATUS, miim_read, NULL}, 1167 /* Auto-negotiate */ 1168 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1169 /* Read the status */ 1170 {MIIM_88E1011_PHY_STATUS, miim_read, 1171 &mii_parse_88E1011_psr}, 1172 {miim_end,} 1173 }, 1174 (struct phy_cmd[]){ /* shutdown */ 1175 {miim_end,} 1176 }, 1177 }; 1178 1179 struct phy_info phy_info_M88E1118 = { 1180 0x01410e1, 1181 "Marvell 88E1118", 1182 4, 1183 (struct phy_cmd[]){ /* config */ 1184 /* Reset and configure the PHY */ 1185 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1186 {0x16, 0x0002, NULL}, /* Change Page Number */ 1187 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1188 {0x16, 0x0003, NULL}, /* Change Page Number */ 1189 {0x10, 0x021e, NULL}, /* Adjust LED control */ 1190 {0x16, 0x0000, NULL}, /* Change Page Number */ 1191 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1192 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1193 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1194 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1195 {miim_end,} 1196 }, 1197 (struct phy_cmd[]){ /* startup */ 1198 {0x16, 0x0000, NULL}, /* Change Page Number */ 1199 /* Status is read once to clear old link state */ 1200 {MIIM_STATUS, miim_read, NULL}, 1201 /* Auto-negotiate */ 1202 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1203 /* Read the status */ 1204 {MIIM_88E1011_PHY_STATUS, miim_read, 1205 &mii_parse_88E1011_psr}, 1206 {miim_end,} 1207 }, 1208 (struct phy_cmd[]){ /* shutdown */ 1209 {miim_end,} 1210 }, 1211 }; 1212 1213 /* 1214 * Since to access LED register we need do switch the page, we 1215 * do LED configuring in the miim_read-like function as follows 1216 */ 1217 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) 1218 { 1219 uint pg; 1220 1221 /* Switch the page to access the led register */ 1222 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE); 1223 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE); 1224 1225 /* Configure leds */ 1226 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL, 1227 MIIM_88E1121_PHY_LED_DEF); 1228 1229 /* Restore the page pointer */ 1230 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg); 1231 return 0; 1232 } 1233 1234 struct phy_info phy_info_M88E1121R = { 1235 0x01410cb, 1236 "Marvell 88E1121R", 1237 4, 1238 (struct phy_cmd[]){ /* config */ 1239 /* Reset and configure the PHY */ 1240 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1241 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1242 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1243 /* Configure leds */ 1244 {MIIM_88E1121_PHY_LED_CTRL, miim_read, 1245 &mii_88E1121_set_led}, 1246 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1247 /* Disable IRQs and de-assert interrupt */ 1248 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, 1249 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, 1250 {miim_end,} 1251 }, 1252 (struct phy_cmd[]){ /* startup */ 1253 /* Status is read once to clear old link state */ 1254 {MIIM_STATUS, miim_read, NULL}, 1255 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1256 {MIIM_STATUS, miim_read, &mii_parse_link}, 1257 {miim_end,} 1258 }, 1259 (struct phy_cmd[]){ /* shutdown */ 1260 {miim_end,} 1261 }, 1262 }; 1263 1264 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1265 { 1266 uint mii_data = read_phy_reg(priv, mii_reg); 1267 1268 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1269 if (priv->flags & TSEC_REDUCED) 1270 return mii_data | 1271 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1272 else 1273 return mii_data; 1274 } 1275 1276 static struct phy_info phy_info_M88E1145 = { 1277 0x01410cd, 1278 "Marvell 88E1145", 1279 4, 1280 (struct phy_cmd[]){ /* config */ 1281 /* Reset the PHY */ 1282 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1283 1284 /* Errata E0, E1 */ 1285 {29, 0x001b, NULL}, 1286 {30, 0x418f, NULL}, 1287 {29, 0x0016, NULL}, 1288 {30, 0xa2da, NULL}, 1289 1290 /* Configure the PHY */ 1291 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1292 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1293 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, 1294 NULL}, 1295 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1296 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1297 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1298 {miim_end,} 1299 }, 1300 (struct phy_cmd[]){ /* startup */ 1301 /* Status is read once to clear old link state */ 1302 {MIIM_STATUS, miim_read, NULL}, 1303 /* Auto-negotiate */ 1304 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1305 {MIIM_88E1111_PHY_LED_CONTROL, 1306 MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1307 /* Read the Status */ 1308 {MIIM_88E1011_PHY_STATUS, miim_read, 1309 &mii_parse_88E1011_psr}, 1310 {miim_end,} 1311 }, 1312 (struct phy_cmd[]){ /* shutdown */ 1313 {miim_end,} 1314 }, 1315 }; 1316 1317 struct phy_info phy_info_cis8204 = { 1318 0x3f11, 1319 "Cicada Cis8204", 1320 6, 1321 (struct phy_cmd[]){ /* config */ 1322 /* Override PHY config settings */ 1323 {MIIM_CIS8201_AUX_CONSTAT, 1324 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1325 /* Configure some basic stuff */ 1326 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1327 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1328 &mii_cis8204_fixled}, 1329 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1330 &mii_cis8204_setmode}, 1331 {miim_end,} 1332 }, 1333 (struct phy_cmd[]){ /* startup */ 1334 /* Read the Status (2x to make sure link is right) */ 1335 {MIIM_STATUS, miim_read, NULL}, 1336 /* Auto-negotiate */ 1337 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1338 /* Read the status */ 1339 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1340 &mii_parse_cis8201}, 1341 {miim_end,} 1342 }, 1343 (struct phy_cmd[]){ /* shutdown */ 1344 {miim_end,} 1345 }, 1346 }; 1347 1348 /* Cicada 8201 */ 1349 struct phy_info phy_info_cis8201 = { 1350 0xfc41, 1351 "CIS8201", 1352 4, 1353 (struct phy_cmd[]){ /* config */ 1354 /* Override PHY config settings */ 1355 {MIIM_CIS8201_AUX_CONSTAT, 1356 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1357 /* Set up the interface mode */ 1358 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, 1359 NULL}, 1360 /* Configure some basic stuff */ 1361 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1362 {miim_end,} 1363 }, 1364 (struct phy_cmd[]){ /* startup */ 1365 /* Read the Status (2x to make sure link is right) */ 1366 {MIIM_STATUS, miim_read, NULL}, 1367 /* Auto-negotiate */ 1368 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1369 /* Read the status */ 1370 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1371 &mii_parse_cis8201}, 1372 {miim_end,} 1373 }, 1374 (struct phy_cmd[]){ /* shutdown */ 1375 {miim_end,} 1376 }, 1377 }; 1378 struct phy_info phy_info_VSC8211 = { 1379 0xfc4b, 1380 "Vitesse VSC8211", 1381 4, 1382 (struct phy_cmd[]) { /* config */ 1383 /* Override PHY config settings */ 1384 {MIIM_CIS8201_AUX_CONSTAT, 1385 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1386 /* Set up the interface mode */ 1387 {MIIM_CIS8201_EXT_CON1, 1388 MIIM_CIS8201_EXTCON1_INIT, NULL}, 1389 /* Configure some basic stuff */ 1390 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1391 {miim_end,} 1392 }, 1393 (struct phy_cmd[]) { /* startup */ 1394 /* Read the Status (2x to make sure link is right) */ 1395 {MIIM_STATUS, miim_read, NULL}, 1396 /* Auto-negotiate */ 1397 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1398 /* Read the status */ 1399 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1400 &mii_parse_cis8201}, 1401 {miim_end,} 1402 }, 1403 (struct phy_cmd[]) { /* shutdown */ 1404 {miim_end,} 1405 }, 1406 }; 1407 struct phy_info phy_info_VSC8244 = { 1408 0x3f1b, 1409 "Vitesse VSC8244", 1410 6, 1411 (struct phy_cmd[]){ /* config */ 1412 /* Override PHY config settings */ 1413 /* Configure some basic stuff */ 1414 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1415 {miim_end,} 1416 }, 1417 (struct phy_cmd[]){ /* startup */ 1418 /* Read the Status (2x to make sure link is right) */ 1419 {MIIM_STATUS, miim_read, NULL}, 1420 /* Auto-negotiate */ 1421 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1422 /* Read the status */ 1423 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1424 &mii_parse_vsc8244}, 1425 {miim_end,} 1426 }, 1427 (struct phy_cmd[]){ /* shutdown */ 1428 {miim_end,} 1429 }, 1430 }; 1431 1432 struct phy_info phy_info_VSC8641 = { 1433 0x7043, 1434 "Vitesse VSC8641", 1435 4, 1436 (struct phy_cmd[]){ /* config */ 1437 /* Configure some basic stuff */ 1438 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1439 {miim_end,} 1440 }, 1441 (struct phy_cmd[]){ /* startup */ 1442 /* Read the Status (2x to make sure link is right) */ 1443 {MIIM_STATUS, miim_read, NULL}, 1444 /* Auto-negotiate */ 1445 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1446 /* Read the status */ 1447 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1448 &mii_parse_vsc8244}, 1449 {miim_end,} 1450 }, 1451 (struct phy_cmd[]){ /* shutdown */ 1452 {miim_end,} 1453 }, 1454 }; 1455 1456 struct phy_info phy_info_VSC8221 = { 1457 0xfc55, 1458 "Vitesse VSC8221", 1459 4, 1460 (struct phy_cmd[]){ /* config */ 1461 /* Configure some basic stuff */ 1462 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1463 {miim_end,} 1464 }, 1465 (struct phy_cmd[]){ /* startup */ 1466 /* Read the Status (2x to make sure link is right) */ 1467 {MIIM_STATUS, miim_read, NULL}, 1468 /* Auto-negotiate */ 1469 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1470 /* Read the status */ 1471 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1472 &mii_parse_vsc8244}, 1473 {miim_end,} 1474 }, 1475 (struct phy_cmd[]){ /* shutdown */ 1476 {miim_end,} 1477 }, 1478 }; 1479 1480 struct phy_info phy_info_VSC8601 = { 1481 0x00007042, 1482 "Vitesse VSC8601", 1483 4, 1484 (struct phy_cmd[]){ /* config */ 1485 /* Override PHY config settings */ 1486 /* Configure some basic stuff */ 1487 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1488 #ifdef CONFIG_SYS_VSC8601_SKEWFIX 1489 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1490 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) 1491 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1492 #define VSC8101_SKEW (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12) 1493 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1494 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1495 #endif 1496 #endif 1497 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1498 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, 1499 {miim_end,} 1500 }, 1501 (struct phy_cmd[]){ /* startup */ 1502 /* Read the Status (2x to make sure link is right) */ 1503 {MIIM_STATUS, miim_read, NULL}, 1504 /* Auto-negotiate */ 1505 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1506 /* Read the status */ 1507 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1508 &mii_parse_vsc8244}, 1509 {miim_end,} 1510 }, 1511 (struct phy_cmd[]){ /* shutdown */ 1512 {miim_end,} 1513 }, 1514 }; 1515 1516 1517 struct phy_info phy_info_dm9161 = { 1518 0x0181b88, 1519 "Davicom DM9161E", 1520 4, 1521 (struct phy_cmd[]){ /* config */ 1522 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1523 /* Do not bypass the scrambler/descrambler */ 1524 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1525 /* Clear 10BTCSR to default */ 1526 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, 1527 NULL}, 1528 /* Configure some basic stuff */ 1529 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1530 /* Restart Auto Negotiation */ 1531 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1532 {miim_end,} 1533 }, 1534 (struct phy_cmd[]){ /* startup */ 1535 /* Status is read once to clear old link state */ 1536 {MIIM_STATUS, miim_read, NULL}, 1537 /* Auto-negotiate */ 1538 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1539 /* Read the status */ 1540 {MIIM_DM9161_SCSR, miim_read, 1541 &mii_parse_dm9161_scsr}, 1542 {miim_end,} 1543 }, 1544 (struct phy_cmd[]){ /* shutdown */ 1545 {miim_end,} 1546 }, 1547 }; 1548 /* a generic flavor. */ 1549 struct phy_info phy_info_generic = { 1550 0, 1551 "Unknown/Generic PHY", 1552 32, 1553 (struct phy_cmd[]) { /* config */ 1554 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1555 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1556 {miim_end,} 1557 }, 1558 (struct phy_cmd[]) { /* startup */ 1559 {PHY_BMSR, miim_read, NULL}, 1560 {PHY_BMSR, miim_read, &mii_parse_sr}, 1561 {PHY_BMSR, miim_read, &mii_parse_link}, 1562 {miim_end,} 1563 }, 1564 (struct phy_cmd[]) { /* shutdown */ 1565 {miim_end,} 1566 } 1567 }; 1568 1569 1570 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1571 { 1572 unsigned int speed; 1573 if (priv->link) { 1574 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1575 1576 switch (speed) { 1577 case MIIM_LXT971_SR2_10HDX: 1578 priv->speed = 10; 1579 priv->duplexity = 0; 1580 break; 1581 case MIIM_LXT971_SR2_10FDX: 1582 priv->speed = 10; 1583 priv->duplexity = 1; 1584 break; 1585 case MIIM_LXT971_SR2_100HDX: 1586 priv->speed = 100; 1587 priv->duplexity = 0; 1588 break; 1589 default: 1590 priv->speed = 100; 1591 priv->duplexity = 1; 1592 } 1593 } else { 1594 priv->speed = 0; 1595 priv->duplexity = 0; 1596 } 1597 1598 return 0; 1599 } 1600 1601 static struct phy_info phy_info_lxt971 = { 1602 0x0001378e, 1603 "LXT971", 1604 4, 1605 (struct phy_cmd[]){ /* config */ 1606 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1607 {miim_end,} 1608 }, 1609 (struct phy_cmd[]){ /* startup - enable interrupts */ 1610 /* { 0x12, 0x00f2, NULL }, */ 1611 {MIIM_STATUS, miim_read, NULL}, 1612 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1613 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1614 {miim_end,} 1615 }, 1616 (struct phy_cmd[]){ /* shutdown - disable interrupts */ 1617 {miim_end,} 1618 }, 1619 }; 1620 1621 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1622 * information 1623 */ 1624 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1625 { 1626 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1627 1628 case MIIM_DP83865_SPD_1000: 1629 priv->speed = 1000; 1630 break; 1631 1632 case MIIM_DP83865_SPD_100: 1633 priv->speed = 100; 1634 break; 1635 1636 default: 1637 priv->speed = 10; 1638 break; 1639 1640 } 1641 1642 if (mii_reg & MIIM_DP83865_DPX_FULL) 1643 priv->duplexity = 1; 1644 else 1645 priv->duplexity = 0; 1646 1647 return 0; 1648 } 1649 1650 struct phy_info phy_info_dp83865 = { 1651 0x20005c7, 1652 "NatSemi DP83865", 1653 4, 1654 (struct phy_cmd[]){ /* config */ 1655 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1656 {miim_end,} 1657 }, 1658 (struct phy_cmd[]){ /* startup */ 1659 /* Status is read once to clear old link state */ 1660 {MIIM_STATUS, miim_read, NULL}, 1661 /* Auto-negotiate */ 1662 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1663 /* Read the link and auto-neg status */ 1664 {MIIM_DP83865_LANR, miim_read, 1665 &mii_parse_dp83865_lanr}, 1666 {miim_end,} 1667 }, 1668 (struct phy_cmd[]){ /* shutdown */ 1669 {miim_end,} 1670 }, 1671 }; 1672 1673 struct phy_info phy_info_rtl8211b = { 1674 0x001cc91, 1675 "RealTek RTL8211B", 1676 4, 1677 (struct phy_cmd[]){ /* config */ 1678 /* Reset and configure the PHY */ 1679 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1680 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1681 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1682 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1683 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1684 {miim_end,} 1685 }, 1686 (struct phy_cmd[]){ /* startup */ 1687 /* Status is read once to clear old link state */ 1688 {MIIM_STATUS, miim_read, NULL}, 1689 /* Auto-negotiate */ 1690 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1691 /* Read the status */ 1692 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1693 {miim_end,} 1694 }, 1695 (struct phy_cmd[]){ /* shutdown */ 1696 {miim_end,} 1697 }, 1698 }; 1699 1700 struct phy_info *phy_info[] = { 1701 &phy_info_cis8204, 1702 &phy_info_cis8201, 1703 &phy_info_BCM5461S, 1704 &phy_info_BCM5464S, 1705 &phy_info_BCM5482S, 1706 &phy_info_M88E1011S, 1707 &phy_info_M88E1111S, 1708 &phy_info_M88E1118, 1709 &phy_info_M88E1121R, 1710 &phy_info_M88E1145, 1711 &phy_info_M88E1149S, 1712 &phy_info_dm9161, 1713 &phy_info_lxt971, 1714 &phy_info_VSC8211, 1715 &phy_info_VSC8244, 1716 &phy_info_VSC8601, 1717 &phy_info_VSC8641, 1718 &phy_info_VSC8221, 1719 &phy_info_dp83865, 1720 &phy_info_rtl8211b, 1721 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */ 1722 NULL 1723 }; 1724 1725 /* Grab the identifier of the device's PHY, and search through 1726 * all of the known PHYs to see if one matches. If so, return 1727 * it, if not, return NULL 1728 */ 1729 struct phy_info *get_phy_info(struct eth_device *dev) 1730 { 1731 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1732 uint phy_reg, phy_ID; 1733 int i; 1734 struct phy_info *theInfo = NULL; 1735 1736 /* Grab the bits from PHYIR1, and put them in the upper half */ 1737 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1738 phy_ID = (phy_reg & 0xffff) << 16; 1739 1740 /* Grab the bits from PHYIR2, and put them in the lower half */ 1741 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1742 phy_ID |= (phy_reg & 0xffff); 1743 1744 /* loop through all the known PHY types, and find one that */ 1745 /* matches the ID we read from the PHY. */ 1746 for (i = 0; phy_info[i]; i++) { 1747 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1748 theInfo = phy_info[i]; 1749 break; 1750 } 1751 } 1752 1753 if (theInfo == &phy_info_generic) { 1754 printf("%s: No support for PHY id %x; assuming generic\n", dev->name, phy_ID); 1755 } else { 1756 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1757 } 1758 1759 return theInfo; 1760 } 1761 1762 /* Execute the given series of commands on the given device's 1763 * PHY, running functions as necessary 1764 */ 1765 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1766 { 1767 int i; 1768 uint result; 1769 volatile tsec_t *phyregs = priv->phyregs; 1770 1771 phyregs->miimcfg = MIIMCFG_RESET; 1772 1773 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1774 1775 while (phyregs->miimind & MIIMIND_BUSY) ; 1776 1777 for (i = 0; cmd->mii_reg != miim_end; i++) { 1778 if (cmd->mii_data == miim_read) { 1779 result = read_phy_reg(priv, cmd->mii_reg); 1780 1781 if (cmd->funct != NULL) 1782 (*(cmd->funct)) (result, priv); 1783 1784 } else { 1785 if (cmd->funct != NULL) 1786 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1787 else 1788 result = cmd->mii_data; 1789 1790 write_phy_reg(priv, cmd->mii_reg, result); 1791 1792 } 1793 cmd++; 1794 } 1795 } 1796 1797 /* Relocate the function pointers in the phy cmd lists */ 1798 static void relocate_cmds(void) 1799 { 1800 struct phy_cmd **cmdlistptr; 1801 struct phy_cmd *cmd; 1802 int i, j, k; 1803 1804 for (i = 0; phy_info[i]; i++) { 1805 /* First thing's first: relocate the pointers to the 1806 * PHY command structures (the structs were done) */ 1807 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 1808 + gd->reloc_off); 1809 phy_info[i]->name += gd->reloc_off; 1810 phy_info[i]->config = 1811 (struct phy_cmd *)((uint) phy_info[i]->config 1812 + gd->reloc_off); 1813 phy_info[i]->startup = 1814 (struct phy_cmd *)((uint) phy_info[i]->startup 1815 + gd->reloc_off); 1816 phy_info[i]->shutdown = 1817 (struct phy_cmd *)((uint) phy_info[i]->shutdown 1818 + gd->reloc_off); 1819 1820 cmdlistptr = &phy_info[i]->config; 1821 j = 0; 1822 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { 1823 k = 0; 1824 for (cmd = *cmdlistptr; 1825 cmd->mii_reg != miim_end; 1826 cmd++) { 1827 /* Only relocate non-NULL pointers */ 1828 if (cmd->funct) 1829 cmd->funct += gd->reloc_off; 1830 1831 k++; 1832 } 1833 j++; 1834 } 1835 } 1836 1837 relocated = 1; 1838 } 1839 1840 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1841 && !defined(BITBANGMII) 1842 1843 /* 1844 * Read a MII PHY register. 1845 * 1846 * Returns: 1847 * 0 on success 1848 */ 1849 static int tsec_miiphy_read(char *devname, unsigned char addr, 1850 unsigned char reg, unsigned short *value) 1851 { 1852 unsigned short ret; 1853 struct tsec_private *priv = privlist[0]; 1854 1855 if (NULL == priv) { 1856 printf("Can't read PHY at address %d\n", addr); 1857 return -1; 1858 } 1859 1860 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg); 1861 *value = ret; 1862 1863 return 0; 1864 } 1865 1866 /* 1867 * Write a MII PHY register. 1868 * 1869 * Returns: 1870 * 0 on success 1871 */ 1872 static int tsec_miiphy_write(char *devname, unsigned char addr, 1873 unsigned char reg, unsigned short value) 1874 { 1875 struct tsec_private *priv = privlist[0]; 1876 1877 if (NULL == priv) { 1878 printf("Can't write PHY at address %d\n", addr); 1879 return -1; 1880 } 1881 1882 tsec_local_mdio_write(priv->phyregs, addr, reg, value); 1883 1884 return 0; 1885 } 1886 1887 #endif 1888 1889 #ifdef CONFIG_MCAST_TFTP 1890 1891 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1892 1893 /* Set the appropriate hash bit for the given addr */ 1894 1895 /* The algorithm works like so: 1896 * 1) Take the Destination Address (ie the multicast address), and 1897 * do a CRC on it (little endian), and reverse the bits of the 1898 * result. 1899 * 2) Use the 8 most significant bits as a hash into a 256-entry 1900 * table. The table is controlled through 8 32-bit registers: 1901 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1902 * gaddr7. This means that the 3 most significant bits in the 1903 * hash index which gaddr register to use, and the 5 other bits 1904 * indicate which bit (assuming an IBM numbering scheme, which 1905 * for PowerPC (tm) is usually the case) in the tregister holds 1906 * the entry. */ 1907 static int 1908 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1909 { 1910 struct tsec_private *priv = privlist[1]; 1911 volatile tsec_t *regs = priv->regs; 1912 volatile u32 *reg_array, value; 1913 u8 result, whichbit, whichreg; 1914 1915 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1916 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1917 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1918 value = (1 << (31-whichbit)); 1919 1920 reg_array = &(regs->hash.gaddr0); 1921 1922 if (set) { 1923 reg_array[whichreg] |= value; 1924 } else { 1925 reg_array[whichreg] &= ~value; 1926 } 1927 return 0; 1928 } 1929 #endif /* Multicast TFTP ? */ 1930