1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004-2011 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 #include <fsl_mdio.h> 21 #include <asm/errno.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define TX_BUF_CNT 2 26 27 static uint rxIdx; /* index of the current RX buffer */ 28 static uint txIdx; /* index of the current TX buffer */ 29 30 typedef volatile struct rtxbd { 31 txbd8_t txbd[TX_BUF_CNT]; 32 rxbd8_t rxbd[PKTBUFSRX]; 33 } RTXBD; 34 35 #define MAXCONTROLLERS (8) 36 37 static struct tsec_private *privlist[MAXCONTROLLERS]; 38 static int num_tsecs = 0; 39 40 #ifdef __GNUC__ 41 static RTXBD rtx __attribute__ ((aligned(8))); 42 #else 43 #error "rtx must be 64-bit aligned" 44 #endif 45 46 /* Default initializations for TSEC controllers. */ 47 48 static struct tsec_info_struct tsec_info[] = { 49 #ifdef CONFIG_TSEC1 50 STD_TSEC_INFO(1), /* TSEC1 */ 51 #endif 52 #ifdef CONFIG_TSEC2 53 STD_TSEC_INFO(2), /* TSEC2 */ 54 #endif 55 #ifdef CONFIG_MPC85XX_FEC 56 { 57 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 58 .devname = CONFIG_MPC85XX_FEC_NAME, 59 .phyaddr = FEC_PHY_ADDR, 60 .flags = FEC_FLAGS, 61 .mii_devname = DEFAULT_MII_NAME 62 }, /* FEC */ 63 #endif 64 #ifdef CONFIG_TSEC3 65 STD_TSEC_INFO(3), /* TSEC3 */ 66 #endif 67 #ifdef CONFIG_TSEC4 68 STD_TSEC_INFO(4), /* TSEC4 */ 69 #endif 70 }; 71 72 #define TBIANA_SETTINGS ( \ 73 TBIANA_ASYMMETRIC_PAUSE \ 74 | TBIANA_SYMMETRIC_PAUSE \ 75 | TBIANA_FULL_DUPLEX \ 76 ) 77 78 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ 79 #ifndef CONFIG_TSEC_TBICR_SETTINGS 80 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 81 TBICR_PHY_RESET \ 82 | TBICR_ANEG_ENABLE \ 83 | TBICR_FULL_DUPLEX \ 84 | TBICR_SPEED1_SET \ 85 ) 86 #endif /* CONFIG_TSEC_TBICR_SETTINGS */ 87 88 /* Configure the TBI for SGMII operation */ 89 static void tsec_configure_serdes(struct tsec_private *priv) 90 { 91 /* Access TBI PHY registers at given TSEC register offset as opposed 92 * to the register offset used for external PHY accesses */ 93 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 94 0, TBI_ANA, TBIANA_SETTINGS); 95 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 96 0, TBI_TBICON, TBICON_CLK_SELECT); 97 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 98 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS); 99 } 100 101 #ifdef CONFIG_MCAST_TFTP 102 103 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 104 105 /* Set the appropriate hash bit for the given addr */ 106 107 /* The algorithm works like so: 108 * 1) Take the Destination Address (ie the multicast address), and 109 * do a CRC on it (little endian), and reverse the bits of the 110 * result. 111 * 2) Use the 8 most significant bits as a hash into a 256-entry 112 * table. The table is controlled through 8 32-bit registers: 113 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 114 * gaddr7. This means that the 3 most significant bits in the 115 * hash index which gaddr register to use, and the 5 other bits 116 * indicate which bit (assuming an IBM numbering scheme, which 117 * for PowerPC (tm) is usually the case) in the tregister holds 118 * the entry. */ 119 static int 120 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 121 { 122 struct tsec_private *priv = privlist[1]; 123 volatile tsec_t *regs = priv->regs; 124 volatile u32 *reg_array, value; 125 u8 result, whichbit, whichreg; 126 127 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 128 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 129 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 130 value = (1 << (31-whichbit)); 131 132 reg_array = &(regs->hash.gaddr0); 133 134 if (set) { 135 reg_array[whichreg] |= value; 136 } else { 137 reg_array[whichreg] &= ~value; 138 } 139 return 0; 140 } 141 #endif /* Multicast TFTP ? */ 142 143 /* Initialized required registers to appropriate values, zeroing 144 * those we don't care about (unless zero is bad, in which case, 145 * choose a more appropriate value) 146 */ 147 static void init_registers(tsec_t *regs) 148 { 149 /* Clear IEVENT */ 150 out_be32(®s->ievent, IEVENT_INIT_CLEAR); 151 152 out_be32(®s->imask, IMASK_INIT_CLEAR); 153 154 out_be32(®s->hash.iaddr0, 0); 155 out_be32(®s->hash.iaddr1, 0); 156 out_be32(®s->hash.iaddr2, 0); 157 out_be32(®s->hash.iaddr3, 0); 158 out_be32(®s->hash.iaddr4, 0); 159 out_be32(®s->hash.iaddr5, 0); 160 out_be32(®s->hash.iaddr6, 0); 161 out_be32(®s->hash.iaddr7, 0); 162 163 out_be32(®s->hash.gaddr0, 0); 164 out_be32(®s->hash.gaddr1, 0); 165 out_be32(®s->hash.gaddr2, 0); 166 out_be32(®s->hash.gaddr3, 0); 167 out_be32(®s->hash.gaddr4, 0); 168 out_be32(®s->hash.gaddr5, 0); 169 out_be32(®s->hash.gaddr6, 0); 170 out_be32(®s->hash.gaddr7, 0); 171 172 out_be32(®s->rctrl, 0x00000000); 173 174 /* Init RMON mib registers */ 175 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 176 177 out_be32(®s->rmon.cam1, 0xffffffff); 178 out_be32(®s->rmon.cam2, 0xffffffff); 179 180 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS); 181 182 out_be32(®s->minflr, MINFLR_INIT_SETTINGS); 183 184 out_be32(®s->attr, ATTR_INIT_SETTINGS); 185 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS); 186 187 } 188 189 /* Configure maccfg2 based on negotiated speed and duplex 190 * reported by PHY handling code 191 */ 192 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) 193 { 194 tsec_t *regs = priv->regs; 195 u32 ecntrl, maccfg2; 196 197 if (!phydev->link) { 198 printf("%s: No link.\n", phydev->dev->name); 199 return; 200 } 201 202 /* clear all bits relative with interface mode */ 203 ecntrl = in_be32(®s->ecntrl); 204 ecntrl &= ~ECNTRL_R100; 205 206 maccfg2 = in_be32(®s->maccfg2); 207 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX); 208 209 if (phydev->duplex) 210 maccfg2 |= MACCFG2_FULL_DUPLEX; 211 212 switch (phydev->speed) { 213 case 1000: 214 maccfg2 |= MACCFG2_GMII; 215 break; 216 case 100: 217 case 10: 218 maccfg2 |= MACCFG2_MII; 219 220 /* Set R100 bit in all modes although 221 * it is only used in RGMII mode 222 */ 223 if (phydev->speed == 100) 224 ecntrl |= ECNTRL_R100; 225 break; 226 default: 227 printf("%s: Speed was bad\n", phydev->dev->name); 228 break; 229 } 230 231 out_be32(®s->ecntrl, ecntrl); 232 out_be32(®s->maccfg2, maccfg2); 233 234 printf("Speed: %d, %s duplex%s\n", phydev->speed, 235 (phydev->duplex) ? "full" : "half", 236 (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); 237 } 238 239 /* Set up the buffers and their descriptors, and bring up the 240 * interface 241 */ 242 static void startup_tsec(struct eth_device *dev) 243 { 244 int i; 245 struct tsec_private *priv = (struct tsec_private *)dev->priv; 246 tsec_t *regs = priv->regs; 247 248 /* reset the indices to zero */ 249 rxIdx = 0; 250 txIdx = 0; 251 252 /* Point to the buffer descriptors */ 253 out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx])); 254 out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx])); 255 256 /* Initialize the Rx Buffer descriptors */ 257 for (i = 0; i < PKTBUFSRX; i++) { 258 rtx.rxbd[i].status = RXBD_EMPTY; 259 rtx.rxbd[i].length = 0; 260 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 261 } 262 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 263 264 /* Initialize the TX Buffer Descriptors */ 265 for (i = 0; i < TX_BUF_CNT; i++) { 266 rtx.txbd[i].status = 0; 267 rtx.txbd[i].length = 0; 268 rtx.txbd[i].bufPtr = 0; 269 } 270 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 271 272 /* Enable Transmit and Receive */ 273 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); 274 275 /* Tell the DMA it is clear to go */ 276 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); 277 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 278 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 279 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 280 } 281 282 /* This returns the status bits of the device. The return value 283 * is never checked, and this is what the 8260 driver did, so we 284 * do the same. Presumably, this would be zero if there were no 285 * errors 286 */ 287 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 288 { 289 int i; 290 int result = 0; 291 struct tsec_private *priv = (struct tsec_private *)dev->priv; 292 tsec_t *regs = priv->regs; 293 294 /* Find an empty buffer descriptor */ 295 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 296 if (i >= TOUT_LOOP) { 297 debug("%s: tsec: tx buffers full\n", dev->name); 298 return result; 299 } 300 } 301 302 rtx.txbd[txIdx].bufPtr = (uint) packet; 303 rtx.txbd[txIdx].length = length; 304 rtx.txbd[txIdx].status |= 305 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 306 307 /* Tell the DMA to go */ 308 out_be32(®s->tstat, TSTAT_CLEAR_THALT); 309 310 /* Wait for buffer to be transmitted */ 311 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 312 if (i >= TOUT_LOOP) { 313 debug("%s: tsec: tx error\n", dev->name); 314 return result; 315 } 316 } 317 318 txIdx = (txIdx + 1) % TX_BUF_CNT; 319 result = rtx.txbd[txIdx].status & TXBD_STATS; 320 321 return result; 322 } 323 324 static int tsec_recv(struct eth_device *dev) 325 { 326 int length; 327 struct tsec_private *priv = (struct tsec_private *)dev->priv; 328 tsec_t *regs = priv->regs; 329 330 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 331 332 length = rtx.rxbd[rxIdx].length; 333 334 /* Send the packet up if there were no errors */ 335 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 336 NetReceive(NetRxPackets[rxIdx], length - 4); 337 } else { 338 printf("Got error %x\n", 339 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 340 } 341 342 rtx.rxbd[rxIdx].length = 0; 343 344 /* Set the wrap bit if this is the last element in the list */ 345 rtx.rxbd[rxIdx].status = 346 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 347 348 rxIdx = (rxIdx + 1) % PKTBUFSRX; 349 } 350 351 if (in_be32(®s->ievent) & IEVENT_BSY) { 352 out_be32(®s->ievent, IEVENT_BSY); 353 out_be32(®s->rstat, RSTAT_CLEAR_RHALT); 354 } 355 356 return -1; 357 358 } 359 360 /* Stop the interface */ 361 static void tsec_halt(struct eth_device *dev) 362 { 363 struct tsec_private *priv = (struct tsec_private *)dev->priv; 364 tsec_t *regs = priv->regs; 365 366 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 367 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); 368 369 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) 370 != (IEVENT_GRSC | IEVENT_GTSC)) 371 ; 372 373 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); 374 375 /* Shut down the PHY, as needed */ 376 phy_shutdown(priv->phydev); 377 } 378 379 /* Initializes data structures and registers for the controller, 380 * and brings the interface up. Returns the link status, meaning 381 * that it returns success if the link is up, failure otherwise. 382 * This allows u-boot to find the first active controller. 383 */ 384 static int tsec_init(struct eth_device *dev, bd_t * bd) 385 { 386 uint tempval; 387 char tmpbuf[MAC_ADDR_LEN]; 388 int i; 389 struct tsec_private *priv = (struct tsec_private *)dev->priv; 390 tsec_t *regs = priv->regs; 391 392 /* Make sure the controller is stopped */ 393 tsec_halt(dev); 394 395 /* Init MACCFG2. Defaults to GMII */ 396 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS); 397 398 /* Init ECNTRL */ 399 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); 400 401 /* Copy the station address into the address registers. 402 * Backwards, because little endian MACS are dumb */ 403 for (i = 0; i < MAC_ADDR_LEN; i++) 404 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 405 406 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | 407 tmpbuf[3]; 408 409 out_be32(®s->macstnaddr1, tempval); 410 411 tempval = *((uint *) (tmpbuf + 4)); 412 413 out_be32(®s->macstnaddr2, tempval); 414 415 /* Clear out (for the most part) the other registers */ 416 init_registers(regs); 417 418 /* Ready the device for tx/rx */ 419 startup_tsec(dev); 420 421 /* Start up the PHY */ 422 phy_startup(priv->phydev); 423 424 adjust_link(priv, priv->phydev); 425 426 /* If there's no link, fail */ 427 return priv->phydev->link ? 0 : -1; 428 } 429 430 static phy_interface_t tsec_get_interface(struct tsec_private *priv) 431 { 432 tsec_t *regs = priv->regs; 433 u32 ecntrl; 434 435 ecntrl = in_be32(®s->ecntrl); 436 437 if (ecntrl & ECNTRL_SGMII_MODE) 438 return PHY_INTERFACE_MODE_SGMII; 439 440 if (ecntrl & ECNTRL_TBI_MODE) { 441 if (ecntrl & ECNTRL_REDUCED_MODE) 442 return PHY_INTERFACE_MODE_RTBI; 443 else 444 return PHY_INTERFACE_MODE_TBI; 445 } 446 447 if (ecntrl & ECNTRL_REDUCED_MODE) { 448 if (ecntrl & ECNTRL_REDUCED_MII_MODE) 449 return PHY_INTERFACE_MODE_RMII; 450 else { 451 phy_interface_t interface = priv->interface; 452 453 /* 454 * This isn't autodetected, so it must 455 * be set by the platform code. 456 */ 457 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) || 458 (interface == PHY_INTERFACE_MODE_RGMII_TXID) || 459 (interface == PHY_INTERFACE_MODE_RGMII_RXID)) 460 return interface; 461 462 return PHY_INTERFACE_MODE_RGMII; 463 } 464 } 465 466 if (priv->flags & TSEC_GIGABIT) 467 return PHY_INTERFACE_MODE_GMII; 468 469 return PHY_INTERFACE_MODE_MII; 470 } 471 472 473 /* Discover which PHY is attached to the device, and configure it 474 * properly. If the PHY is not recognized, then return 0 475 * (failure). Otherwise, return 1 476 */ 477 static int init_phy(struct eth_device *dev) 478 { 479 struct tsec_private *priv = (struct tsec_private *)dev->priv; 480 struct phy_device *phydev; 481 tsec_t *regs = priv->regs; 482 u32 supported = (SUPPORTED_10baseT_Half | 483 SUPPORTED_10baseT_Full | 484 SUPPORTED_100baseT_Half | 485 SUPPORTED_100baseT_Full); 486 487 if (priv->flags & TSEC_GIGABIT) 488 supported |= SUPPORTED_1000baseT_Full; 489 490 /* Assign a Physical address to the TBI */ 491 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); 492 493 priv->interface = tsec_get_interface(priv); 494 495 if (priv->interface == PHY_INTERFACE_MODE_SGMII) 496 tsec_configure_serdes(priv); 497 498 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); 499 500 phydev->supported &= supported; 501 phydev->advertising = phydev->supported; 502 503 priv->phydev = phydev; 504 505 phy_config(phydev); 506 507 return 1; 508 } 509 510 /* Initialize device structure. Returns success if PHY 511 * initialization succeeded (i.e. if it recognizes the PHY) 512 */ 513 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) 514 { 515 struct eth_device *dev; 516 int i; 517 struct tsec_private *priv; 518 519 dev = (struct eth_device *)malloc(sizeof *dev); 520 521 if (NULL == dev) 522 return 0; 523 524 memset(dev, 0, sizeof *dev); 525 526 priv = (struct tsec_private *)malloc(sizeof(*priv)); 527 528 if (NULL == priv) 529 return 0; 530 531 privlist[num_tsecs++] = priv; 532 priv->regs = tsec_info->regs; 533 priv->phyregs_sgmii = tsec_info->miiregs_sgmii; 534 535 priv->phyaddr = tsec_info->phyaddr; 536 priv->flags = tsec_info->flags; 537 538 sprintf(dev->name, tsec_info->devname); 539 priv->interface = tsec_info->interface; 540 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); 541 dev->iobase = 0; 542 dev->priv = priv; 543 dev->init = tsec_init; 544 dev->halt = tsec_halt; 545 dev->send = tsec_send; 546 dev->recv = tsec_recv; 547 #ifdef CONFIG_MCAST_TFTP 548 dev->mcast = tsec_mcast_addr; 549 #endif 550 551 /* Tell u-boot to get the addr from the env */ 552 for (i = 0; i < 6; i++) 553 dev->enetaddr[i] = 0; 554 555 eth_register(dev); 556 557 /* Reset the MAC */ 558 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); 559 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ 560 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); 561 562 /* Try to initialize PHY here, and return */ 563 return init_phy(dev); 564 } 565 566 /* 567 * Initialize all the TSEC devices 568 * 569 * Returns the number of TSEC devices that were initialized 570 */ 571 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 572 { 573 int i; 574 int ret, count = 0; 575 576 for (i = 0; i < num; i++) { 577 ret = tsec_initialize(bis, &tsecs[i]); 578 if (ret > 0) 579 count += ret; 580 } 581 582 return count; 583 } 584 585 int tsec_standard_init(bd_t *bis) 586 { 587 struct fsl_pq_mdio_info info; 588 589 info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 590 info.name = DEFAULT_MII_NAME; 591 592 fsl_pq_mdio_init(bis, &info); 593 594 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 595 } 596