1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 21 #include "miiphy.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define TX_BUF_CNT 2 26 27 static uint rxIdx; /* index of the current RX buffer */ 28 static uint txIdx; /* index of the current TX buffer */ 29 30 typedef volatile struct rtxbd { 31 txbd8_t txbd[TX_BUF_CNT]; 32 rxbd8_t rxbd[PKTBUFSRX]; 33 } RTXBD; 34 35 #define MAXCONTROLLERS (8) 36 37 static int relocated = 0; 38 39 static struct tsec_private *privlist[MAXCONTROLLERS]; 40 static int num_tsecs = 0; 41 42 #ifdef __GNUC__ 43 static RTXBD rtx __attribute__ ((aligned(8))); 44 #else 45 #error "rtx must be 64-bit aligned" 46 #endif 47 48 static int tsec_send(struct eth_device *dev, 49 volatile void *packet, int length); 50 static int tsec_recv(struct eth_device *dev); 51 static int tsec_init(struct eth_device *dev, bd_t * bd); 52 static void tsec_halt(struct eth_device *dev); 53 static void init_registers(volatile tsec_t * regs); 54 static void startup_tsec(struct eth_device *dev); 55 static int init_phy(struct eth_device *dev); 56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 57 uint read_phy_reg(struct tsec_private *priv, uint regnum); 58 struct phy_info *get_phy_info(struct eth_device *dev); 59 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 60 static void adjust_link(struct eth_device *dev); 61 static void relocate_cmds(void); 62 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 63 && !defined(BITBANGMII) 64 static int tsec_miiphy_write(char *devname, unsigned char addr, 65 unsigned char reg, unsigned short value); 66 static int tsec_miiphy_read(char *devname, unsigned char addr, 67 unsigned char reg, unsigned short *value); 68 #endif 69 #ifdef CONFIG_MCAST_TFTP 70 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 71 #endif 72 73 /* Default initializations for TSEC controllers. */ 74 75 static struct tsec_info_struct tsec_info[] = { 76 #ifdef CONFIG_TSEC1 77 STD_TSEC_INFO(1), /* TSEC1 */ 78 #endif 79 #ifdef CONFIG_TSEC2 80 STD_TSEC_INFO(2), /* TSEC2 */ 81 #endif 82 #ifdef CONFIG_MPC85XX_FEC 83 { 84 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 85 .miiregs = (tsec_t *)(TSEC_BASE_ADDR), 86 .devname = CONFIG_MPC85XX_FEC_NAME, 87 .phyaddr = FEC_PHY_ADDR, 88 .flags = FEC_FLAGS 89 }, /* FEC */ 90 #endif 91 #ifdef CONFIG_TSEC3 92 STD_TSEC_INFO(3), /* TSEC3 */ 93 #endif 94 #ifdef CONFIG_TSEC4 95 STD_TSEC_INFO(4), /* TSEC4 */ 96 #endif 97 }; 98 99 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 100 { 101 int i; 102 103 for (i = 0; i < num; i++) 104 tsec_initialize(bis, &tsecs[i]); 105 106 return 0; 107 } 108 109 int tsec_standard_init(bd_t *bis) 110 { 111 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 112 } 113 114 /* Initialize device structure. Returns success if PHY 115 * initialization succeeded (i.e. if it recognizes the PHY) 116 */ 117 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) 118 { 119 struct eth_device *dev; 120 int i; 121 struct tsec_private *priv; 122 123 dev = (struct eth_device *)malloc(sizeof *dev); 124 125 if (NULL == dev) 126 return 0; 127 128 memset(dev, 0, sizeof *dev); 129 130 priv = (struct tsec_private *)malloc(sizeof(*priv)); 131 132 if (NULL == priv) 133 return 0; 134 135 privlist[num_tsecs++] = priv; 136 priv->regs = tsec_info->regs; 137 priv->phyregs = tsec_info->miiregs; 138 139 priv->phyaddr = tsec_info->phyaddr; 140 priv->flags = tsec_info->flags; 141 142 sprintf(dev->name, tsec_info->devname); 143 dev->iobase = 0; 144 dev->priv = priv; 145 dev->init = tsec_init; 146 dev->halt = tsec_halt; 147 dev->send = tsec_send; 148 dev->recv = tsec_recv; 149 #ifdef CONFIG_MCAST_TFTP 150 dev->mcast = tsec_mcast_addr; 151 #endif 152 153 /* Tell u-boot to get the addr from the env */ 154 for (i = 0; i < 6; i++) 155 dev->enetaddr[i] = 0; 156 157 eth_register(dev); 158 159 /* Reset the MAC */ 160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 161 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 162 163 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 164 && !defined(BITBANGMII) 165 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 166 #endif 167 168 /* Try to initialize PHY here, and return */ 169 return init_phy(dev); 170 } 171 172 /* Initializes data structures and registers for the controller, 173 * and brings the interface up. Returns the link status, meaning 174 * that it returns success if the link is up, failure otherwise. 175 * This allows u-boot to find the first active controller. 176 */ 177 int tsec_init(struct eth_device *dev, bd_t * bd) 178 { 179 uint tempval; 180 char tmpbuf[MAC_ADDR_LEN]; 181 int i; 182 struct tsec_private *priv = (struct tsec_private *)dev->priv; 183 volatile tsec_t *regs = priv->regs; 184 185 /* Make sure the controller is stopped */ 186 tsec_halt(dev); 187 188 /* Init MACCFG2. Defaults to GMII */ 189 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 190 191 /* Init ECNTRL */ 192 regs->ecntrl = ECNTRL_INIT_SETTINGS; 193 194 /* Copy the station address into the address registers. 195 * Backwards, because little endian MACS are dumb */ 196 for (i = 0; i < MAC_ADDR_LEN; i++) { 197 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 198 } 199 regs->macstnaddr1 = *((uint *) (tmpbuf)); 200 201 tempval = *((uint *) (tmpbuf + 4)); 202 203 regs->macstnaddr2 = tempval; 204 205 /* reset the indices to zero */ 206 rxIdx = 0; 207 txIdx = 0; 208 209 /* Clear out (for the most part) the other registers */ 210 init_registers(regs); 211 212 /* Ready the device for tx/rx */ 213 startup_tsec(dev); 214 215 /* If there's no link, fail */ 216 return (priv->link ? 0 : -1); 217 } 218 219 /* Writes the given phy's reg with value, using the specified MDIO regs */ 220 static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, 221 uint reg, uint value) 222 { 223 int timeout = 1000000; 224 225 phyregs->miimadd = (addr << 8) | reg; 226 phyregs->miimcon = value; 227 asm("sync"); 228 229 timeout = 1000000; 230 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ; 231 } 232 233 234 /* Provide the default behavior of writing the PHY of this ethernet device */ 235 #define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) 236 237 /* Reads register regnum on the device's PHY through the 238 * specified registers. It lowers and raises the read 239 * command, and waits for the data to become valid (miimind 240 * notvalid bit cleared), and the bus to cease activity (miimind 241 * busy bit cleared), and then returns the value 242 */ 243 uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) 244 { 245 uint value; 246 247 /* Put the address of the phy, and the register 248 * number into MIIMADD */ 249 phyregs->miimadd = (phyid << 8) | regnum; 250 251 /* Clear the command register, and wait */ 252 phyregs->miimcom = 0; 253 asm("sync"); 254 255 /* Initiate a read command, and wait */ 256 phyregs->miimcom = MIIM_READ_COMMAND; 257 asm("sync"); 258 259 /* Wait for the the indication that the read is done */ 260 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 261 262 /* Grab the value read from the PHY */ 263 value = phyregs->miimstat; 264 265 return value; 266 } 267 268 /* #define to provide old read_phy_reg functionality without duplicating code */ 269 #define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) 270 271 #define TBIANA_SETTINGS ( \ 272 TBIANA_ASYMMETRIC_PAUSE \ 273 | TBIANA_SYMMETRIC_PAUSE \ 274 | TBIANA_FULL_DUPLEX \ 275 ) 276 277 #define TBICR_SETTINGS ( \ 278 TBICR_PHY_RESET \ 279 | TBICR_ANEG_ENABLE \ 280 | TBICR_FULL_DUPLEX \ 281 | TBICR_SPEED1_SET \ 282 ) 283 /* Configure the TBI for SGMII operation */ 284 static void tsec_configure_serdes(struct tsec_private *priv) 285 { 286 /* Access TBI PHY registers at given TSEC register offset as opposed to the 287 * register offset used for external PHY accesses */ 288 tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, 289 TBIANA_SETTINGS); 290 tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, 291 TBICON_CLK_SELECT); 292 tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, 293 TBICR_SETTINGS); 294 } 295 296 /* Discover which PHY is attached to the device, and configure it 297 * properly. If the PHY is not recognized, then return 0 298 * (failure). Otherwise, return 1 299 */ 300 static int init_phy(struct eth_device *dev) 301 { 302 struct tsec_private *priv = (struct tsec_private *)dev->priv; 303 struct phy_info *curphy; 304 volatile tsec_t *phyregs = priv->phyregs; 305 volatile tsec_t *regs = priv->regs; 306 307 /* Assign a Physical address to the TBI */ 308 regs->tbipa = CONFIG_SYS_TBIPA_VALUE; 309 phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE; 310 asm("sync"); 311 312 /* Reset MII (due to new addresses) */ 313 priv->phyregs->miimcfg = MIIMCFG_RESET; 314 asm("sync"); 315 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 316 asm("sync"); 317 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 318 319 if (0 == relocated) 320 relocate_cmds(); 321 322 /* Get the cmd structure corresponding to the attached 323 * PHY */ 324 curphy = get_phy_info(dev); 325 326 if (curphy == NULL) { 327 priv->phyinfo = NULL; 328 printf("%s: No PHY found\n", dev->name); 329 330 return 0; 331 } 332 333 if (regs->ecntrl & ECNTRL_SGMII_MODE) 334 tsec_configure_serdes(priv); 335 336 priv->phyinfo = curphy; 337 338 phy_run_commands(priv, priv->phyinfo->config); 339 340 return 1; 341 } 342 343 /* 344 * Returns which value to write to the control register. 345 * For 10/100, the value is slightly different 346 */ 347 uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 348 { 349 if (priv->flags & TSEC_GIGABIT) 350 return MIIM_CONTROL_INIT; 351 else 352 return MIIM_CR_INIT; 353 } 354 355 /* Parse the status register for link, and then do 356 * auto-negotiation 357 */ 358 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 359 { 360 /* 361 * Wait if the link is up, and autonegotiation is in progress 362 * (ie - we're capable and it's not done) 363 */ 364 mii_reg = read_phy_reg(priv, MIIM_STATUS); 365 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) 366 && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 367 int i = 0; 368 369 puts("Waiting for PHY auto negotiation to complete"); 370 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 371 /* 372 * Timeout reached ? 373 */ 374 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 375 puts(" TIMEOUT !\n"); 376 priv->link = 0; 377 return 0; 378 } 379 380 if ((i++ % 1000) == 0) { 381 putc('.'); 382 } 383 udelay(1000); /* 1 ms */ 384 mii_reg = read_phy_reg(priv, MIIM_STATUS); 385 } 386 puts(" done\n"); 387 priv->link = 1; 388 udelay(500000); /* another 500 ms (results in faster booting) */ 389 } else { 390 if (mii_reg & MIIM_STATUS_LINK) 391 priv->link = 1; 392 else 393 priv->link = 0; 394 } 395 396 return 0; 397 } 398 399 /* Generic function which updates the speed and duplex. If 400 * autonegotiation is enabled, it uses the AND of the link 401 * partner's advertised capabilities and our advertised 402 * capabilities. If autonegotiation is disabled, we use the 403 * appropriate bits in the control register. 404 * 405 * Stolen from Linux's mii.c and phy_device.c 406 */ 407 uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 408 { 409 /* We're using autonegotiation */ 410 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 411 uint lpa = 0; 412 uint gblpa = 0; 413 414 /* Check for gigabit capability */ 415 if (mii_reg & PHY_BMSR_EXT) { 416 /* We want a list of states supported by 417 * both PHYs in the link 418 */ 419 gblpa = read_phy_reg(priv, PHY_1000BTSR); 420 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 421 } 422 423 /* Set the baseline so we only have to set them 424 * if they're different 425 */ 426 priv->speed = 10; 427 priv->duplexity = 0; 428 429 /* Check the gigabit fields */ 430 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 431 priv->speed = 1000; 432 433 if (gblpa & PHY_1000BTSR_1000FD) 434 priv->duplexity = 1; 435 436 /* We're done! */ 437 return 0; 438 } 439 440 lpa = read_phy_reg(priv, PHY_ANAR); 441 lpa &= read_phy_reg(priv, PHY_ANLPAR); 442 443 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 444 priv->speed = 100; 445 446 if (lpa & PHY_ANLPAR_TXFD) 447 priv->duplexity = 1; 448 449 } else if (lpa & PHY_ANLPAR_10FD) 450 priv->duplexity = 1; 451 } else { 452 uint bmcr = read_phy_reg(priv, PHY_BMCR); 453 454 priv->speed = 10; 455 priv->duplexity = 0; 456 457 if (bmcr & PHY_BMCR_DPLX) 458 priv->duplexity = 1; 459 460 if (bmcr & PHY_BMCR_1000_MBPS) 461 priv->speed = 1000; 462 else if (bmcr & PHY_BMCR_100_MBPS) 463 priv->speed = 100; 464 } 465 466 return 0; 467 } 468 469 /* 470 * Parse the BCM54xx status register for speed and duplex information. 471 * The linux sungem_phy has this information, but in a table format. 472 */ 473 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 474 { 475 476 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ 477 478 case 1: 479 printf("Enet starting in 10BT/HD\n"); 480 priv->duplexity = 0; 481 priv->speed = 10; 482 break; 483 484 case 2: 485 printf("Enet starting in 10BT/FD\n"); 486 priv->duplexity = 1; 487 priv->speed = 10; 488 break; 489 490 case 3: 491 printf("Enet starting in 100BT/HD\n"); 492 priv->duplexity = 0; 493 priv->speed = 100; 494 break; 495 496 case 5: 497 printf("Enet starting in 100BT/FD\n"); 498 priv->duplexity = 1; 499 priv->speed = 100; 500 break; 501 502 case 6: 503 printf("Enet starting in 1000BT/HD\n"); 504 priv->duplexity = 0; 505 priv->speed = 1000; 506 break; 507 508 case 7: 509 printf("Enet starting in 1000BT/FD\n"); 510 priv->duplexity = 1; 511 priv->speed = 1000; 512 break; 513 514 default: 515 printf("Auto-neg error, defaulting to 10BT/HD\n"); 516 priv->duplexity = 0; 517 priv->speed = 10; 518 break; 519 } 520 521 return 0; 522 523 } 524 /* Parse the 88E1011's status register for speed and duplex 525 * information 526 */ 527 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 528 { 529 uint speed; 530 531 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 532 533 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 534 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 535 int i = 0; 536 537 puts("Waiting for PHY realtime link"); 538 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 539 /* Timeout reached ? */ 540 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 541 puts(" TIMEOUT !\n"); 542 priv->link = 0; 543 break; 544 } 545 546 if ((i++ % 1000) == 0) { 547 putc('.'); 548 } 549 udelay(1000); /* 1 ms */ 550 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 551 } 552 puts(" done\n"); 553 udelay(500000); /* another 500 ms (results in faster booting) */ 554 } else { 555 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 556 priv->link = 1; 557 else 558 priv->link = 0; 559 } 560 561 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 562 priv->duplexity = 1; 563 else 564 priv->duplexity = 0; 565 566 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 567 568 switch (speed) { 569 case MIIM_88E1011_PHYSTAT_GBIT: 570 priv->speed = 1000; 571 break; 572 case MIIM_88E1011_PHYSTAT_100: 573 priv->speed = 100; 574 break; 575 default: 576 priv->speed = 10; 577 } 578 579 return 0; 580 } 581 582 /* Parse the RTL8211B's status register for speed and duplex 583 * information 584 */ 585 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 586 { 587 uint speed; 588 589 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 590 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 591 int i = 0; 592 593 /* in case of timeout ->link is cleared */ 594 priv->link = 1; 595 puts("Waiting for PHY realtime link"); 596 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 597 /* Timeout reached ? */ 598 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 599 puts(" TIMEOUT !\n"); 600 priv->link = 0; 601 break; 602 } 603 604 if ((i++ % 1000) == 0) { 605 putc('.'); 606 } 607 udelay(1000); /* 1 ms */ 608 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 609 } 610 puts(" done\n"); 611 udelay(500000); /* another 500 ms (results in faster booting) */ 612 } else { 613 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 614 priv->link = 1; 615 else 616 priv->link = 0; 617 } 618 619 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 620 priv->duplexity = 1; 621 else 622 priv->duplexity = 0; 623 624 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 625 626 switch (speed) { 627 case MIIM_RTL8211B_PHYSTAT_GBIT: 628 priv->speed = 1000; 629 break; 630 case MIIM_RTL8211B_PHYSTAT_100: 631 priv->speed = 100; 632 break; 633 default: 634 priv->speed = 10; 635 } 636 637 return 0; 638 } 639 640 /* Parse the cis8201's status register for speed and duplex 641 * information 642 */ 643 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 644 { 645 uint speed; 646 647 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 648 priv->duplexity = 1; 649 else 650 priv->duplexity = 0; 651 652 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 653 switch (speed) { 654 case MIIM_CIS8201_AUXCONSTAT_GBIT: 655 priv->speed = 1000; 656 break; 657 case MIIM_CIS8201_AUXCONSTAT_100: 658 priv->speed = 100; 659 break; 660 default: 661 priv->speed = 10; 662 break; 663 } 664 665 return 0; 666 } 667 668 /* Parse the vsc8244's status register for speed and duplex 669 * information 670 */ 671 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 672 { 673 uint speed; 674 675 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 676 priv->duplexity = 1; 677 else 678 priv->duplexity = 0; 679 680 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 681 switch (speed) { 682 case MIIM_VSC8244_AUXCONSTAT_GBIT: 683 priv->speed = 1000; 684 break; 685 case MIIM_VSC8244_AUXCONSTAT_100: 686 priv->speed = 100; 687 break; 688 default: 689 priv->speed = 10; 690 break; 691 } 692 693 return 0; 694 } 695 696 /* Parse the DM9161's status register for speed and duplex 697 * information 698 */ 699 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 700 { 701 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 702 priv->speed = 100; 703 else 704 priv->speed = 10; 705 706 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 707 priv->duplexity = 1; 708 else 709 priv->duplexity = 0; 710 711 return 0; 712 } 713 714 /* 715 * Hack to write all 4 PHYs with the LED values 716 */ 717 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 718 { 719 uint phyid; 720 volatile tsec_t *regbase = priv->phyregs; 721 int timeout = 1000000; 722 723 for (phyid = 0; phyid < 4; phyid++) { 724 regbase->miimadd = (phyid << 8) | mii_reg; 725 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 726 asm("sync"); 727 728 timeout = 1000000; 729 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 730 } 731 732 return MIIM_CIS8204_SLEDCON_INIT; 733 } 734 735 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 736 { 737 if (priv->flags & TSEC_REDUCED) 738 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 739 else 740 return MIIM_CIS8204_EPHYCON_INIT; 741 } 742 743 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 744 { 745 uint mii_data = read_phy_reg(priv, mii_reg); 746 747 if (priv->flags & TSEC_REDUCED) 748 mii_data = (mii_data & 0xfff0) | 0x000b; 749 return mii_data; 750 } 751 752 /* Initialized required registers to appropriate values, zeroing 753 * those we don't care about (unless zero is bad, in which case, 754 * choose a more appropriate value) 755 */ 756 static void init_registers(volatile tsec_t * regs) 757 { 758 /* Clear IEVENT */ 759 regs->ievent = IEVENT_INIT_CLEAR; 760 761 regs->imask = IMASK_INIT_CLEAR; 762 763 regs->hash.iaddr0 = 0; 764 regs->hash.iaddr1 = 0; 765 regs->hash.iaddr2 = 0; 766 regs->hash.iaddr3 = 0; 767 regs->hash.iaddr4 = 0; 768 regs->hash.iaddr5 = 0; 769 regs->hash.iaddr6 = 0; 770 regs->hash.iaddr7 = 0; 771 772 regs->hash.gaddr0 = 0; 773 regs->hash.gaddr1 = 0; 774 regs->hash.gaddr2 = 0; 775 regs->hash.gaddr3 = 0; 776 regs->hash.gaddr4 = 0; 777 regs->hash.gaddr5 = 0; 778 regs->hash.gaddr6 = 0; 779 regs->hash.gaddr7 = 0; 780 781 regs->rctrl = 0x00000000; 782 783 /* Init RMON mib registers */ 784 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 785 786 regs->rmon.cam1 = 0xffffffff; 787 regs->rmon.cam2 = 0xffffffff; 788 789 regs->mrblr = MRBLR_INIT_SETTINGS; 790 791 regs->minflr = MINFLR_INIT_SETTINGS; 792 793 regs->attr = ATTR_INIT_SETTINGS; 794 regs->attreli = ATTRELI_INIT_SETTINGS; 795 796 } 797 798 /* Configure maccfg2 based on negotiated speed and duplex 799 * reported by PHY handling code 800 */ 801 static void adjust_link(struct eth_device *dev) 802 { 803 struct tsec_private *priv = (struct tsec_private *)dev->priv; 804 volatile tsec_t *regs = priv->regs; 805 806 if (priv->link) { 807 if (priv->duplexity != 0) 808 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 809 else 810 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 811 812 switch (priv->speed) { 813 case 1000: 814 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 815 | MACCFG2_GMII); 816 break; 817 case 100: 818 case 10: 819 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 820 | MACCFG2_MII); 821 822 /* Set R100 bit in all modes although 823 * it is only used in RGMII mode 824 */ 825 if (priv->speed == 100) 826 regs->ecntrl |= ECNTRL_R100; 827 else 828 regs->ecntrl &= ~(ECNTRL_R100); 829 break; 830 default: 831 printf("%s: Speed was bad\n", dev->name); 832 break; 833 } 834 835 printf("Speed: %d, %s duplex\n", priv->speed, 836 (priv->duplexity) ? "full" : "half"); 837 838 } else { 839 printf("%s: No link.\n", dev->name); 840 } 841 } 842 843 /* Set up the buffers and their descriptors, and bring up the 844 * interface 845 */ 846 static void startup_tsec(struct eth_device *dev) 847 { 848 int i; 849 struct tsec_private *priv = (struct tsec_private *)dev->priv; 850 volatile tsec_t *regs = priv->regs; 851 852 /* Point to the buffer descriptors */ 853 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 854 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 855 856 /* Initialize the Rx Buffer descriptors */ 857 for (i = 0; i < PKTBUFSRX; i++) { 858 rtx.rxbd[i].status = RXBD_EMPTY; 859 rtx.rxbd[i].length = 0; 860 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 861 } 862 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 863 864 /* Initialize the TX Buffer Descriptors */ 865 for (i = 0; i < TX_BUF_CNT; i++) { 866 rtx.txbd[i].status = 0; 867 rtx.txbd[i].length = 0; 868 rtx.txbd[i].bufPtr = 0; 869 } 870 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 871 872 /* Start up the PHY */ 873 if(priv->phyinfo) 874 phy_run_commands(priv, priv->phyinfo->startup); 875 876 adjust_link(dev); 877 878 /* Enable Transmit and Receive */ 879 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 880 881 /* Tell the DMA it is clear to go */ 882 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 883 regs->tstat = TSTAT_CLEAR_THALT; 884 regs->rstat = RSTAT_CLEAR_RHALT; 885 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 886 } 887 888 /* This returns the status bits of the device. The return value 889 * is never checked, and this is what the 8260 driver did, so we 890 * do the same. Presumably, this would be zero if there were no 891 * errors 892 */ 893 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 894 { 895 int i; 896 int result = 0; 897 struct tsec_private *priv = (struct tsec_private *)dev->priv; 898 volatile tsec_t *regs = priv->regs; 899 900 /* Find an empty buffer descriptor */ 901 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 902 if (i >= TOUT_LOOP) { 903 debug("%s: tsec: tx buffers full\n", dev->name); 904 return result; 905 } 906 } 907 908 rtx.txbd[txIdx].bufPtr = (uint) packet; 909 rtx.txbd[txIdx].length = length; 910 rtx.txbd[txIdx].status |= 911 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 912 913 /* Tell the DMA to go */ 914 regs->tstat = TSTAT_CLEAR_THALT; 915 916 /* Wait for buffer to be transmitted */ 917 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 918 if (i >= TOUT_LOOP) { 919 debug("%s: tsec: tx error\n", dev->name); 920 return result; 921 } 922 } 923 924 txIdx = (txIdx + 1) % TX_BUF_CNT; 925 result = rtx.txbd[txIdx].status & TXBD_STATS; 926 927 return result; 928 } 929 930 static int tsec_recv(struct eth_device *dev) 931 { 932 int length; 933 struct tsec_private *priv = (struct tsec_private *)dev->priv; 934 volatile tsec_t *regs = priv->regs; 935 936 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 937 938 length = rtx.rxbd[rxIdx].length; 939 940 /* Send the packet up if there were no errors */ 941 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 942 NetReceive(NetRxPackets[rxIdx], length - 4); 943 } else { 944 printf("Got error %x\n", 945 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 946 } 947 948 rtx.rxbd[rxIdx].length = 0; 949 950 /* Set the wrap bit if this is the last element in the list */ 951 rtx.rxbd[rxIdx].status = 952 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 953 954 rxIdx = (rxIdx + 1) % PKTBUFSRX; 955 } 956 957 if (regs->ievent & IEVENT_BSY) { 958 regs->ievent = IEVENT_BSY; 959 regs->rstat = RSTAT_CLEAR_RHALT; 960 } 961 962 return -1; 963 964 } 965 966 /* Stop the interface */ 967 static void tsec_halt(struct eth_device *dev) 968 { 969 struct tsec_private *priv = (struct tsec_private *)dev->priv; 970 volatile tsec_t *regs = priv->regs; 971 972 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 973 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 974 975 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 976 977 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 978 979 /* Shut down the PHY, as needed */ 980 if(priv->phyinfo) 981 phy_run_commands(priv, priv->phyinfo->shutdown); 982 } 983 984 struct phy_info phy_info_M88E1149S = { 985 0x1410ca, 986 "Marvell 88E1149S", 987 4, 988 (struct phy_cmd[]){ /* config */ 989 /* Reset and configure the PHY */ 990 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 991 {0x1d, 0x1f, NULL}, 992 {0x1e, 0x200c, NULL}, 993 {0x1d, 0x5, NULL}, 994 {0x1e, 0x0, NULL}, 995 {0x1e, 0x100, NULL}, 996 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 997 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 998 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 999 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1000 {miim_end,} 1001 }, 1002 (struct phy_cmd[]){ /* startup */ 1003 /* Status is read once to clear old link state */ 1004 {MIIM_STATUS, miim_read, NULL}, 1005 /* Auto-negotiate */ 1006 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1007 /* Read the status */ 1008 {MIIM_88E1011_PHY_STATUS, miim_read, 1009 &mii_parse_88E1011_psr}, 1010 {miim_end,} 1011 }, 1012 (struct phy_cmd[]){ /* shutdown */ 1013 {miim_end,} 1014 }, 1015 }; 1016 1017 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1018 struct phy_info phy_info_BCM5461S = { 1019 0x02060c1, /* 5461 ID */ 1020 "Broadcom BCM5461S", 1021 0, /* not clear to me what minor revisions we can shift away */ 1022 (struct phy_cmd[]) { /* config */ 1023 /* Reset and configure the PHY */ 1024 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1025 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1026 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1027 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1028 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1029 {miim_end,} 1030 }, 1031 (struct phy_cmd[]) { /* startup */ 1032 /* Status is read once to clear old link state */ 1033 {MIIM_STATUS, miim_read, NULL}, 1034 /* Auto-negotiate */ 1035 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1036 /* Read the status */ 1037 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1038 {miim_end,} 1039 }, 1040 (struct phy_cmd[]) { /* shutdown */ 1041 {miim_end,} 1042 }, 1043 }; 1044 1045 struct phy_info phy_info_BCM5464S = { 1046 0x02060b1, /* 5464 ID */ 1047 "Broadcom BCM5464S", 1048 0, /* not clear to me what minor revisions we can shift away */ 1049 (struct phy_cmd[]) { /* config */ 1050 /* Reset and configure the PHY */ 1051 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1052 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1053 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1054 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1055 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1056 {miim_end,} 1057 }, 1058 (struct phy_cmd[]) { /* startup */ 1059 /* Status is read once to clear old link state */ 1060 {MIIM_STATUS, miim_read, NULL}, 1061 /* Auto-negotiate */ 1062 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1063 /* Read the status */ 1064 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1065 {miim_end,} 1066 }, 1067 (struct phy_cmd[]) { /* shutdown */ 1068 {miim_end,} 1069 }, 1070 }; 1071 1072 struct phy_info phy_info_M88E1011S = { 1073 0x01410c6, 1074 "Marvell 88E1011S", 1075 4, 1076 (struct phy_cmd[]){ /* config */ 1077 /* Reset and configure the PHY */ 1078 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1079 {0x1d, 0x1f, NULL}, 1080 {0x1e, 0x200c, NULL}, 1081 {0x1d, 0x5, NULL}, 1082 {0x1e, 0x0, NULL}, 1083 {0x1e, 0x100, NULL}, 1084 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1085 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1086 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1087 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1088 {miim_end,} 1089 }, 1090 (struct phy_cmd[]){ /* startup */ 1091 /* Status is read once to clear old link state */ 1092 {MIIM_STATUS, miim_read, NULL}, 1093 /* Auto-negotiate */ 1094 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1095 /* Read the status */ 1096 {MIIM_88E1011_PHY_STATUS, miim_read, 1097 &mii_parse_88E1011_psr}, 1098 {miim_end,} 1099 }, 1100 (struct phy_cmd[]){ /* shutdown */ 1101 {miim_end,} 1102 }, 1103 }; 1104 1105 struct phy_info phy_info_M88E1111S = { 1106 0x01410cc, 1107 "Marvell 88E1111S", 1108 4, 1109 (struct phy_cmd[]){ /* config */ 1110 /* Reset and configure the PHY */ 1111 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1112 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1113 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1114 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1115 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1116 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1117 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1118 {miim_end,} 1119 }, 1120 (struct phy_cmd[]){ /* startup */ 1121 /* Status is read once to clear old link state */ 1122 {MIIM_STATUS, miim_read, NULL}, 1123 /* Auto-negotiate */ 1124 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1125 /* Read the status */ 1126 {MIIM_88E1011_PHY_STATUS, miim_read, 1127 &mii_parse_88E1011_psr}, 1128 {miim_end,} 1129 }, 1130 (struct phy_cmd[]){ /* shutdown */ 1131 {miim_end,} 1132 }, 1133 }; 1134 1135 struct phy_info phy_info_M88E1118 = { 1136 0x01410e1, 1137 "Marvell 88E1118", 1138 4, 1139 (struct phy_cmd[]){ /* config */ 1140 /* Reset and configure the PHY */ 1141 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1142 {0x16, 0x0002, NULL}, /* Change Page Number */ 1143 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1144 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1145 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1146 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1147 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1148 {miim_end,} 1149 }, 1150 (struct phy_cmd[]){ /* startup */ 1151 {0x16, 0x0000, NULL}, /* Change Page Number */ 1152 /* Status is read once to clear old link state */ 1153 {MIIM_STATUS, miim_read, NULL}, 1154 /* Auto-negotiate */ 1155 /* Read the status */ 1156 {MIIM_88E1011_PHY_STATUS, miim_read, 1157 &mii_parse_88E1011_psr}, 1158 {miim_end,} 1159 }, 1160 (struct phy_cmd[]){ /* shutdown */ 1161 {miim_end,} 1162 }, 1163 }; 1164 1165 /* 1166 * Since to access LED register we need do switch the page, we 1167 * do LED configuring in the miim_read-like function as follows 1168 */ 1169 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) 1170 { 1171 uint pg; 1172 1173 /* Switch the page to access the led register */ 1174 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE); 1175 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE); 1176 1177 /* Configure leds */ 1178 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL, 1179 MIIM_88E1121_PHY_LED_DEF); 1180 1181 /* Restore the page pointer */ 1182 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg); 1183 return 0; 1184 } 1185 1186 struct phy_info phy_info_M88E1121R = { 1187 0x01410cb, 1188 "Marvell 88E1121R", 1189 4, 1190 (struct phy_cmd[]){ /* config */ 1191 /* Reset and configure the PHY */ 1192 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1193 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1194 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1195 /* Configure leds */ 1196 {MIIM_88E1121_PHY_LED_CTRL, miim_read, 1197 &mii_88E1121_set_led}, 1198 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1199 /* Disable IRQs and de-assert interrupt */ 1200 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, 1201 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, 1202 {miim_end,} 1203 }, 1204 (struct phy_cmd[]){ /* startup */ 1205 /* Status is read once to clear old link state */ 1206 {MIIM_STATUS, miim_read, NULL}, 1207 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1208 {MIIM_STATUS, miim_read, &mii_parse_link}, 1209 {miim_end,} 1210 }, 1211 (struct phy_cmd[]){ /* shutdown */ 1212 {miim_end,} 1213 }, 1214 }; 1215 1216 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1217 { 1218 uint mii_data = read_phy_reg(priv, mii_reg); 1219 1220 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1221 if (priv->flags & TSEC_REDUCED) 1222 return mii_data | 1223 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1224 else 1225 return mii_data; 1226 } 1227 1228 static struct phy_info phy_info_M88E1145 = { 1229 0x01410cd, 1230 "Marvell 88E1145", 1231 4, 1232 (struct phy_cmd[]){ /* config */ 1233 /* Reset the PHY */ 1234 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1235 1236 /* Errata E0, E1 */ 1237 {29, 0x001b, NULL}, 1238 {30, 0x418f, NULL}, 1239 {29, 0x0016, NULL}, 1240 {30, 0xa2da, NULL}, 1241 1242 /* Configure the PHY */ 1243 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1244 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1245 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, 1246 NULL}, 1247 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1248 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1249 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1250 {miim_end,} 1251 }, 1252 (struct phy_cmd[]){ /* startup */ 1253 /* Status is read once to clear old link state */ 1254 {MIIM_STATUS, miim_read, NULL}, 1255 /* Auto-negotiate */ 1256 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1257 {MIIM_88E1111_PHY_LED_CONTROL, 1258 MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1259 /* Read the Status */ 1260 {MIIM_88E1011_PHY_STATUS, miim_read, 1261 &mii_parse_88E1011_psr}, 1262 {miim_end,} 1263 }, 1264 (struct phy_cmd[]){ /* shutdown */ 1265 {miim_end,} 1266 }, 1267 }; 1268 1269 struct phy_info phy_info_cis8204 = { 1270 0x3f11, 1271 "Cicada Cis8204", 1272 6, 1273 (struct phy_cmd[]){ /* config */ 1274 /* Override PHY config settings */ 1275 {MIIM_CIS8201_AUX_CONSTAT, 1276 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1277 /* Configure some basic stuff */ 1278 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1279 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1280 &mii_cis8204_fixled}, 1281 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1282 &mii_cis8204_setmode}, 1283 {miim_end,} 1284 }, 1285 (struct phy_cmd[]){ /* startup */ 1286 /* Read the Status (2x to make sure link is right) */ 1287 {MIIM_STATUS, miim_read, NULL}, 1288 /* Auto-negotiate */ 1289 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1290 /* Read the status */ 1291 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1292 &mii_parse_cis8201}, 1293 {miim_end,} 1294 }, 1295 (struct phy_cmd[]){ /* shutdown */ 1296 {miim_end,} 1297 }, 1298 }; 1299 1300 /* Cicada 8201 */ 1301 struct phy_info phy_info_cis8201 = { 1302 0xfc41, 1303 "CIS8201", 1304 4, 1305 (struct phy_cmd[]){ /* config */ 1306 /* Override PHY config settings */ 1307 {MIIM_CIS8201_AUX_CONSTAT, 1308 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1309 /* Set up the interface mode */ 1310 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, 1311 NULL}, 1312 /* Configure some basic stuff */ 1313 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1314 {miim_end,} 1315 }, 1316 (struct phy_cmd[]){ /* startup */ 1317 /* Read the Status (2x to make sure link is right) */ 1318 {MIIM_STATUS, miim_read, NULL}, 1319 /* Auto-negotiate */ 1320 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1321 /* Read the status */ 1322 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1323 &mii_parse_cis8201}, 1324 {miim_end,} 1325 }, 1326 (struct phy_cmd[]){ /* shutdown */ 1327 {miim_end,} 1328 }, 1329 }; 1330 struct phy_info phy_info_VSC8244 = { 1331 0x3f1b, 1332 "Vitesse VSC8244", 1333 6, 1334 (struct phy_cmd[]){ /* config */ 1335 /* Override PHY config settings */ 1336 /* Configure some basic stuff */ 1337 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1338 {miim_end,} 1339 }, 1340 (struct phy_cmd[]){ /* startup */ 1341 /* Read the Status (2x to make sure link is right) */ 1342 {MIIM_STATUS, miim_read, NULL}, 1343 /* Auto-negotiate */ 1344 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1345 /* Read the status */ 1346 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1347 &mii_parse_vsc8244}, 1348 {miim_end,} 1349 }, 1350 (struct phy_cmd[]){ /* shutdown */ 1351 {miim_end,} 1352 }, 1353 }; 1354 1355 struct phy_info phy_info_VSC8601 = { 1356 0x00007042, 1357 "Vitesse VSC8601", 1358 4, 1359 (struct phy_cmd[]){ /* config */ 1360 /* Override PHY config settings */ 1361 /* Configure some basic stuff */ 1362 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1363 #ifdef CONFIG_SYS_VSC8601_SKEWFIX 1364 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1365 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) 1366 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1367 #define VSC8101_SKEW (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12) 1368 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1369 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1370 #endif 1371 #endif 1372 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1373 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, 1374 {miim_end,} 1375 }, 1376 (struct phy_cmd[]){ /* startup */ 1377 /* Read the Status (2x to make sure link is right) */ 1378 {MIIM_STATUS, miim_read, NULL}, 1379 /* Auto-negotiate */ 1380 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1381 /* Read the status */ 1382 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1383 &mii_parse_vsc8244}, 1384 {miim_end,} 1385 }, 1386 (struct phy_cmd[]){ /* shutdown */ 1387 {miim_end,} 1388 }, 1389 }; 1390 1391 1392 struct phy_info phy_info_dm9161 = { 1393 0x0181b88, 1394 "Davicom DM9161E", 1395 4, 1396 (struct phy_cmd[]){ /* config */ 1397 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1398 /* Do not bypass the scrambler/descrambler */ 1399 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1400 /* Clear 10BTCSR to default */ 1401 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, 1402 NULL}, 1403 /* Configure some basic stuff */ 1404 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1405 /* Restart Auto Negotiation */ 1406 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1407 {miim_end,} 1408 }, 1409 (struct phy_cmd[]){ /* startup */ 1410 /* Status is read once to clear old link state */ 1411 {MIIM_STATUS, miim_read, NULL}, 1412 /* Auto-negotiate */ 1413 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1414 /* Read the status */ 1415 {MIIM_DM9161_SCSR, miim_read, 1416 &mii_parse_dm9161_scsr}, 1417 {miim_end,} 1418 }, 1419 (struct phy_cmd[]){ /* shutdown */ 1420 {miim_end,} 1421 }, 1422 }; 1423 /* a generic flavor. */ 1424 struct phy_info phy_info_generic = { 1425 0, 1426 "Unknown/Generic PHY", 1427 32, 1428 (struct phy_cmd[]) { /* config */ 1429 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1430 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1431 {miim_end,} 1432 }, 1433 (struct phy_cmd[]) { /* startup */ 1434 {PHY_BMSR, miim_read, NULL}, 1435 {PHY_BMSR, miim_read, &mii_parse_sr}, 1436 {PHY_BMSR, miim_read, &mii_parse_link}, 1437 {miim_end,} 1438 }, 1439 (struct phy_cmd[]) { /* shutdown */ 1440 {miim_end,} 1441 } 1442 }; 1443 1444 1445 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1446 { 1447 unsigned int speed; 1448 if (priv->link) { 1449 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1450 1451 switch (speed) { 1452 case MIIM_LXT971_SR2_10HDX: 1453 priv->speed = 10; 1454 priv->duplexity = 0; 1455 break; 1456 case MIIM_LXT971_SR2_10FDX: 1457 priv->speed = 10; 1458 priv->duplexity = 1; 1459 break; 1460 case MIIM_LXT971_SR2_100HDX: 1461 priv->speed = 100; 1462 priv->duplexity = 0; 1463 break; 1464 default: 1465 priv->speed = 100; 1466 priv->duplexity = 1; 1467 } 1468 } else { 1469 priv->speed = 0; 1470 priv->duplexity = 0; 1471 } 1472 1473 return 0; 1474 } 1475 1476 static struct phy_info phy_info_lxt971 = { 1477 0x0001378e, 1478 "LXT971", 1479 4, 1480 (struct phy_cmd[]){ /* config */ 1481 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1482 {miim_end,} 1483 }, 1484 (struct phy_cmd[]){ /* startup - enable interrupts */ 1485 /* { 0x12, 0x00f2, NULL }, */ 1486 {MIIM_STATUS, miim_read, NULL}, 1487 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1488 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1489 {miim_end,} 1490 }, 1491 (struct phy_cmd[]){ /* shutdown - disable interrupts */ 1492 {miim_end,} 1493 }, 1494 }; 1495 1496 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1497 * information 1498 */ 1499 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1500 { 1501 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1502 1503 case MIIM_DP83865_SPD_1000: 1504 priv->speed = 1000; 1505 break; 1506 1507 case MIIM_DP83865_SPD_100: 1508 priv->speed = 100; 1509 break; 1510 1511 default: 1512 priv->speed = 10; 1513 break; 1514 1515 } 1516 1517 if (mii_reg & MIIM_DP83865_DPX_FULL) 1518 priv->duplexity = 1; 1519 else 1520 priv->duplexity = 0; 1521 1522 return 0; 1523 } 1524 1525 struct phy_info phy_info_dp83865 = { 1526 0x20005c7, 1527 "NatSemi DP83865", 1528 4, 1529 (struct phy_cmd[]){ /* config */ 1530 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1531 {miim_end,} 1532 }, 1533 (struct phy_cmd[]){ /* startup */ 1534 /* Status is read once to clear old link state */ 1535 {MIIM_STATUS, miim_read, NULL}, 1536 /* Auto-negotiate */ 1537 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1538 /* Read the link and auto-neg status */ 1539 {MIIM_DP83865_LANR, miim_read, 1540 &mii_parse_dp83865_lanr}, 1541 {miim_end,} 1542 }, 1543 (struct phy_cmd[]){ /* shutdown */ 1544 {miim_end,} 1545 }, 1546 }; 1547 1548 struct phy_info phy_info_rtl8211b = { 1549 0x001cc91, 1550 "RealTek RTL8211B", 1551 4, 1552 (struct phy_cmd[]){ /* config */ 1553 /* Reset and configure the PHY */ 1554 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1555 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1556 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1557 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1558 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1559 {miim_end,} 1560 }, 1561 (struct phy_cmd[]){ /* startup */ 1562 /* Status is read once to clear old link state */ 1563 {MIIM_STATUS, miim_read, NULL}, 1564 /* Auto-negotiate */ 1565 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1566 /* Read the status */ 1567 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1568 {miim_end,} 1569 }, 1570 (struct phy_cmd[]){ /* shutdown */ 1571 {miim_end,} 1572 }, 1573 }; 1574 1575 struct phy_info *phy_info[] = { 1576 &phy_info_cis8204, 1577 &phy_info_cis8201, 1578 &phy_info_BCM5461S, 1579 &phy_info_BCM5464S, 1580 &phy_info_M88E1011S, 1581 &phy_info_M88E1111S, 1582 &phy_info_M88E1118, 1583 &phy_info_M88E1121R, 1584 &phy_info_M88E1145, 1585 &phy_info_M88E1149S, 1586 &phy_info_dm9161, 1587 &phy_info_lxt971, 1588 &phy_info_VSC8244, 1589 &phy_info_VSC8601, 1590 &phy_info_dp83865, 1591 &phy_info_rtl8211b, 1592 &phy_info_generic, 1593 NULL 1594 }; 1595 1596 /* Grab the identifier of the device's PHY, and search through 1597 * all of the known PHYs to see if one matches. If so, return 1598 * it, if not, return NULL 1599 */ 1600 struct phy_info *get_phy_info(struct eth_device *dev) 1601 { 1602 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1603 uint phy_reg, phy_ID; 1604 int i; 1605 struct phy_info *theInfo = NULL; 1606 1607 /* Grab the bits from PHYIR1, and put them in the upper half */ 1608 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1609 phy_ID = (phy_reg & 0xffff) << 16; 1610 1611 /* Grab the bits from PHYIR2, and put them in the lower half */ 1612 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1613 phy_ID |= (phy_reg & 0xffff); 1614 1615 /* loop through all the known PHY types, and find one that */ 1616 /* matches the ID we read from the PHY. */ 1617 for (i = 0; phy_info[i]; i++) { 1618 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1619 theInfo = phy_info[i]; 1620 break; 1621 } 1622 } 1623 1624 if (theInfo == NULL) { 1625 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); 1626 return NULL; 1627 } else { 1628 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1629 } 1630 1631 return theInfo; 1632 } 1633 1634 /* Execute the given series of commands on the given device's 1635 * PHY, running functions as necessary 1636 */ 1637 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1638 { 1639 int i; 1640 uint result; 1641 volatile tsec_t *phyregs = priv->phyregs; 1642 1643 phyregs->miimcfg = MIIMCFG_RESET; 1644 1645 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1646 1647 while (phyregs->miimind & MIIMIND_BUSY) ; 1648 1649 for (i = 0; cmd->mii_reg != miim_end; i++) { 1650 if (cmd->mii_data == miim_read) { 1651 result = read_phy_reg(priv, cmd->mii_reg); 1652 1653 if (cmd->funct != NULL) 1654 (*(cmd->funct)) (result, priv); 1655 1656 } else { 1657 if (cmd->funct != NULL) 1658 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1659 else 1660 result = cmd->mii_data; 1661 1662 write_phy_reg(priv, cmd->mii_reg, result); 1663 1664 } 1665 cmd++; 1666 } 1667 } 1668 1669 /* Relocate the function pointers in the phy cmd lists */ 1670 static void relocate_cmds(void) 1671 { 1672 struct phy_cmd **cmdlistptr; 1673 struct phy_cmd *cmd; 1674 int i, j, k; 1675 1676 for (i = 0; phy_info[i]; i++) { 1677 /* First thing's first: relocate the pointers to the 1678 * PHY command structures (the structs were done) */ 1679 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 1680 + gd->reloc_off); 1681 phy_info[i]->name += gd->reloc_off; 1682 phy_info[i]->config = 1683 (struct phy_cmd *)((uint) phy_info[i]->config 1684 + gd->reloc_off); 1685 phy_info[i]->startup = 1686 (struct phy_cmd *)((uint) phy_info[i]->startup 1687 + gd->reloc_off); 1688 phy_info[i]->shutdown = 1689 (struct phy_cmd *)((uint) phy_info[i]->shutdown 1690 + gd->reloc_off); 1691 1692 cmdlistptr = &phy_info[i]->config; 1693 j = 0; 1694 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { 1695 k = 0; 1696 for (cmd = *cmdlistptr; 1697 cmd->mii_reg != miim_end; 1698 cmd++) { 1699 /* Only relocate non-NULL pointers */ 1700 if (cmd->funct) 1701 cmd->funct += gd->reloc_off; 1702 1703 k++; 1704 } 1705 j++; 1706 } 1707 } 1708 1709 relocated = 1; 1710 } 1711 1712 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1713 && !defined(BITBANGMII) 1714 1715 /* 1716 * Read a MII PHY register. 1717 * 1718 * Returns: 1719 * 0 on success 1720 */ 1721 static int tsec_miiphy_read(char *devname, unsigned char addr, 1722 unsigned char reg, unsigned short *value) 1723 { 1724 unsigned short ret; 1725 struct tsec_private *priv = privlist[0]; 1726 1727 if (NULL == priv) { 1728 printf("Can't read PHY at address %d\n", addr); 1729 return -1; 1730 } 1731 1732 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg); 1733 *value = ret; 1734 1735 return 0; 1736 } 1737 1738 /* 1739 * Write a MII PHY register. 1740 * 1741 * Returns: 1742 * 0 on success 1743 */ 1744 static int tsec_miiphy_write(char *devname, unsigned char addr, 1745 unsigned char reg, unsigned short value) 1746 { 1747 struct tsec_private *priv = privlist[0]; 1748 1749 if (NULL == priv) { 1750 printf("Can't write PHY at address %d\n", addr); 1751 return -1; 1752 } 1753 1754 tsec_local_mdio_write(priv->phyregs, addr, reg, value); 1755 1756 return 0; 1757 } 1758 1759 #endif 1760 1761 #ifdef CONFIG_MCAST_TFTP 1762 1763 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1764 1765 /* Set the appropriate hash bit for the given addr */ 1766 1767 /* The algorithm works like so: 1768 * 1) Take the Destination Address (ie the multicast address), and 1769 * do a CRC on it (little endian), and reverse the bits of the 1770 * result. 1771 * 2) Use the 8 most significant bits as a hash into a 256-entry 1772 * table. The table is controlled through 8 32-bit registers: 1773 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1774 * gaddr7. This means that the 3 most significant bits in the 1775 * hash index which gaddr register to use, and the 5 other bits 1776 * indicate which bit (assuming an IBM numbering scheme, which 1777 * for PowerPC (tm) is usually the case) in the tregister holds 1778 * the entry. */ 1779 static int 1780 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1781 { 1782 struct tsec_private *priv = privlist[1]; 1783 volatile tsec_t *regs = priv->regs; 1784 volatile u32 *reg_array, value; 1785 u8 result, whichbit, whichreg; 1786 1787 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1788 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1789 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1790 value = (1 << (31-whichbit)); 1791 1792 reg_array = &(regs->hash.gaddr0); 1793 1794 if (set) { 1795 reg_array[whichreg] |= value; 1796 } else { 1797 reg_array[whichreg] &= ~value; 1798 } 1799 return 0; 1800 } 1801 #endif /* Multicast TFTP ? */ 1802