1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004-2009 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 #include <asm/errno.h> 21 22 #include "miiphy.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define TX_BUF_CNT 2 27 28 static uint rxIdx; /* index of the current RX buffer */ 29 static uint txIdx; /* index of the current TX buffer */ 30 31 typedef volatile struct rtxbd { 32 txbd8_t txbd[TX_BUF_CNT]; 33 rxbd8_t rxbd[PKTBUFSRX]; 34 } RTXBD; 35 36 #define MAXCONTROLLERS (8) 37 38 static struct tsec_private *privlist[MAXCONTROLLERS]; 39 static int num_tsecs = 0; 40 41 #ifdef __GNUC__ 42 static RTXBD rtx __attribute__ ((aligned(8))); 43 #else 44 #error "rtx must be 64-bit aligned" 45 #endif 46 47 static int tsec_send(struct eth_device *dev, 48 volatile void *packet, int length); 49 static int tsec_recv(struct eth_device *dev); 50 static int tsec_init(struct eth_device *dev, bd_t * bd); 51 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); 52 static void tsec_halt(struct eth_device *dev); 53 static void init_registers(volatile tsec_t * regs); 54 static void startup_tsec(struct eth_device *dev); 55 static int init_phy(struct eth_device *dev); 56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 57 uint read_phy_reg(struct tsec_private *priv, uint regnum); 58 static struct phy_info *get_phy_info(struct eth_device *dev); 59 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 60 static void adjust_link(struct eth_device *dev); 61 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 62 && !defined(BITBANGMII) 63 static int tsec_miiphy_write(char *devname, unsigned char addr, 64 unsigned char reg, unsigned short value); 65 static int tsec_miiphy_read(char *devname, unsigned char addr, 66 unsigned char reg, unsigned short *value); 67 #endif 68 #ifdef CONFIG_MCAST_TFTP 69 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 70 #endif 71 72 /* Default initializations for TSEC controllers. */ 73 74 static struct tsec_info_struct tsec_info[] = { 75 #ifdef CONFIG_TSEC1 76 STD_TSEC_INFO(1), /* TSEC1 */ 77 #endif 78 #ifdef CONFIG_TSEC2 79 STD_TSEC_INFO(2), /* TSEC2 */ 80 #endif 81 #ifdef CONFIG_MPC85XX_FEC 82 { 83 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 84 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), 85 .devname = CONFIG_MPC85XX_FEC_NAME, 86 .phyaddr = FEC_PHY_ADDR, 87 .flags = FEC_FLAGS 88 }, /* FEC */ 89 #endif 90 #ifdef CONFIG_TSEC3 91 STD_TSEC_INFO(3), /* TSEC3 */ 92 #endif 93 #ifdef CONFIG_TSEC4 94 STD_TSEC_INFO(4), /* TSEC4 */ 95 #endif 96 }; 97 98 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 99 { 100 int i; 101 102 for (i = 0; i < num; i++) 103 tsec_initialize(bis, &tsecs[i]); 104 105 return 0; 106 } 107 108 int tsec_standard_init(bd_t *bis) 109 { 110 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 111 } 112 113 /* Initialize device structure. Returns success if PHY 114 * initialization succeeded (i.e. if it recognizes the PHY) 115 */ 116 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) 117 { 118 struct eth_device *dev; 119 int i; 120 struct tsec_private *priv; 121 122 dev = (struct eth_device *)malloc(sizeof *dev); 123 124 if (NULL == dev) 125 return 0; 126 127 memset(dev, 0, sizeof *dev); 128 129 priv = (struct tsec_private *)malloc(sizeof(*priv)); 130 131 if (NULL == priv) 132 return 0; 133 134 privlist[num_tsecs++] = priv; 135 priv->regs = tsec_info->regs; 136 priv->phyregs = tsec_info->miiregs; 137 priv->phyregs_sgmii = tsec_info->miiregs_sgmii; 138 139 priv->phyaddr = tsec_info->phyaddr; 140 priv->flags = tsec_info->flags; 141 142 sprintf(dev->name, tsec_info->devname); 143 dev->iobase = 0; 144 dev->priv = priv; 145 dev->init = tsec_init; 146 dev->halt = tsec_halt; 147 dev->send = tsec_send; 148 dev->recv = tsec_recv; 149 #ifdef CONFIG_MCAST_TFTP 150 dev->mcast = tsec_mcast_addr; 151 #endif 152 153 /* Tell u-boot to get the addr from the env */ 154 for (i = 0; i < 6; i++) 155 dev->enetaddr[i] = 0; 156 157 eth_register(dev); 158 159 /* Reset the MAC */ 160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 161 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ 162 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 163 164 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 165 && !defined(BITBANGMII) 166 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 167 #endif 168 169 /* Try to initialize PHY here, and return */ 170 return init_phy(dev); 171 } 172 173 /* Initializes data structures and registers for the controller, 174 * and brings the interface up. Returns the link status, meaning 175 * that it returns success if the link is up, failure otherwise. 176 * This allows u-boot to find the first active controller. 177 */ 178 static int tsec_init(struct eth_device *dev, bd_t * bd) 179 { 180 uint tempval; 181 char tmpbuf[MAC_ADDR_LEN]; 182 int i; 183 struct tsec_private *priv = (struct tsec_private *)dev->priv; 184 volatile tsec_t *regs = priv->regs; 185 186 /* Make sure the controller is stopped */ 187 tsec_halt(dev); 188 189 /* Init MACCFG2. Defaults to GMII */ 190 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 191 192 /* Init ECNTRL */ 193 regs->ecntrl = ECNTRL_INIT_SETTINGS; 194 195 /* Copy the station address into the address registers. 196 * Backwards, because little endian MACS are dumb */ 197 for (i = 0; i < MAC_ADDR_LEN; i++) { 198 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 199 } 200 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | 201 tmpbuf[3]; 202 203 regs->macstnaddr1 = tempval; 204 205 tempval = *((uint *) (tmpbuf + 4)); 206 207 regs->macstnaddr2 = tempval; 208 209 /* reset the indices to zero */ 210 rxIdx = 0; 211 txIdx = 0; 212 213 /* Clear out (for the most part) the other registers */ 214 init_registers(regs); 215 216 /* Ready the device for tx/rx */ 217 startup_tsec(dev); 218 219 /* If there's no link, fail */ 220 return (priv->link ? 0 : -1); 221 } 222 223 /* Writes the given phy's reg with value, using the specified MDIO regs */ 224 static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, 225 uint reg, uint value) 226 { 227 int timeout = 1000000; 228 229 phyregs->miimadd = (addr << 8) | reg; 230 phyregs->miimcon = value; 231 asm("sync"); 232 233 timeout = 1000000; 234 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ; 235 } 236 237 238 /* Provide the default behavior of writing the PHY of this ethernet device */ 239 #define write_phy_reg(priv, regnum, value) \ 240 tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) 241 242 /* Reads register regnum on the device's PHY through the 243 * specified registers. It lowers and raises the read 244 * command, and waits for the data to become valid (miimind 245 * notvalid bit cleared), and the bus to cease activity (miimind 246 * busy bit cleared), and then returns the value 247 */ 248 static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, 249 uint phyid, uint regnum) 250 { 251 uint value; 252 253 /* Put the address of the phy, and the register 254 * number into MIIMADD */ 255 phyregs->miimadd = (phyid << 8) | regnum; 256 257 /* Clear the command register, and wait */ 258 phyregs->miimcom = 0; 259 asm("sync"); 260 261 /* Initiate a read command, and wait */ 262 phyregs->miimcom = MIIM_READ_COMMAND; 263 asm("sync"); 264 265 /* Wait for the the indication that the read is done */ 266 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 267 268 /* Grab the value read from the PHY */ 269 value = phyregs->miimstat; 270 271 return value; 272 } 273 274 /* #define to provide old read_phy_reg functionality without duplicating code */ 275 #define read_phy_reg(priv,regnum) \ 276 tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) 277 278 #define TBIANA_SETTINGS ( \ 279 TBIANA_ASYMMETRIC_PAUSE \ 280 | TBIANA_SYMMETRIC_PAUSE \ 281 | TBIANA_FULL_DUPLEX \ 282 ) 283 284 /* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ 285 #define TBICR_SETTINGS ( \ 286 TBICR_PHY_RESET \ 287 | TBICR_FULL_DUPLEX \ 288 | TBICR_SPEED1_SET \ 289 ) 290 291 /* Configure the TBI for SGMII operation */ 292 static void tsec_configure_serdes(struct tsec_private *priv) 293 { 294 /* Access TBI PHY registers at given TSEC register offset as opposed 295 * to the register offset used for external PHY accesses */ 296 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, 297 TBIANA_SETTINGS); 298 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, 299 TBICON_CLK_SELECT); 300 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, 301 TBICR_SETTINGS); 302 } 303 304 /* Discover which PHY is attached to the device, and configure it 305 * properly. If the PHY is not recognized, then return 0 306 * (failure). Otherwise, return 1 307 */ 308 static int init_phy(struct eth_device *dev) 309 { 310 struct tsec_private *priv = (struct tsec_private *)dev->priv; 311 struct phy_info *curphy; 312 volatile tsec_t *regs = priv->regs; 313 314 /* Assign a Physical address to the TBI */ 315 regs->tbipa = CONFIG_SYS_TBIPA_VALUE; 316 asm("sync"); 317 318 /* Reset MII (due to new addresses) */ 319 priv->phyregs->miimcfg = MIIMCFG_RESET; 320 asm("sync"); 321 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 322 asm("sync"); 323 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 324 325 /* Get the cmd structure corresponding to the attached 326 * PHY */ 327 curphy = get_phy_info(dev); 328 329 if (curphy == NULL) { 330 priv->phyinfo = NULL; 331 printf("%s: No PHY found\n", dev->name); 332 333 return 0; 334 } 335 336 if (regs->ecntrl & ECNTRL_SGMII_MODE) 337 tsec_configure_serdes(priv); 338 339 priv->phyinfo = curphy; 340 341 phy_run_commands(priv, priv->phyinfo->config); 342 343 return 1; 344 } 345 346 /* 347 * Returns which value to write to the control register. 348 * For 10/100, the value is slightly different 349 */ 350 static uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 351 { 352 if (priv->flags & TSEC_GIGABIT) 353 return MIIM_CONTROL_INIT; 354 else 355 return MIIM_CR_INIT; 356 } 357 358 /* 359 * Wait for auto-negotiation to complete, then determine link 360 */ 361 static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 362 { 363 /* 364 * Wait if the link is up, and autonegotiation is in progress 365 * (ie - we're capable and it's not done) 366 */ 367 mii_reg = read_phy_reg(priv, MIIM_STATUS); 368 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 369 int i = 0; 370 371 puts("Waiting for PHY auto negotiation to complete"); 372 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 373 /* 374 * Timeout reached ? 375 */ 376 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 377 puts(" TIMEOUT !\n"); 378 priv->link = 0; 379 return 0; 380 } 381 382 if (ctrlc()) { 383 puts("user interrupt!\n"); 384 priv->link = 0; 385 return -EINTR; 386 } 387 388 if ((i++ % 1000) == 0) { 389 putc('.'); 390 } 391 udelay(1000); /* 1 ms */ 392 mii_reg = read_phy_reg(priv, MIIM_STATUS); 393 } 394 puts(" done\n"); 395 396 /* Link status bit is latched low, read it again */ 397 mii_reg = read_phy_reg(priv, MIIM_STATUS); 398 399 udelay(500000); /* another 500 ms (results in faster booting) */ 400 } 401 402 priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0; 403 404 return 0; 405 } 406 407 /* Generic function which updates the speed and duplex. If 408 * autonegotiation is enabled, it uses the AND of the link 409 * partner's advertised capabilities and our advertised 410 * capabilities. If autonegotiation is disabled, we use the 411 * appropriate bits in the control register. 412 * 413 * Stolen from Linux's mii.c and phy_device.c 414 */ 415 static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 416 { 417 /* We're using autonegotiation */ 418 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 419 uint lpa = 0; 420 uint gblpa = 0; 421 422 /* Check for gigabit capability */ 423 if (mii_reg & PHY_BMSR_EXT) { 424 /* We want a list of states supported by 425 * both PHYs in the link 426 */ 427 gblpa = read_phy_reg(priv, PHY_1000BTSR); 428 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 429 } 430 431 /* Set the baseline so we only have to set them 432 * if they're different 433 */ 434 priv->speed = 10; 435 priv->duplexity = 0; 436 437 /* Check the gigabit fields */ 438 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 439 priv->speed = 1000; 440 441 if (gblpa & PHY_1000BTSR_1000FD) 442 priv->duplexity = 1; 443 444 /* We're done! */ 445 return 0; 446 } 447 448 lpa = read_phy_reg(priv, PHY_ANAR); 449 lpa &= read_phy_reg(priv, PHY_ANLPAR); 450 451 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 452 priv->speed = 100; 453 454 if (lpa & PHY_ANLPAR_TXFD) 455 priv->duplexity = 1; 456 457 } else if (lpa & PHY_ANLPAR_10FD) 458 priv->duplexity = 1; 459 } else { 460 uint bmcr = read_phy_reg(priv, PHY_BMCR); 461 462 priv->speed = 10; 463 priv->duplexity = 0; 464 465 if (bmcr & PHY_BMCR_DPLX) 466 priv->duplexity = 1; 467 468 if (bmcr & PHY_BMCR_1000_MBPS) 469 priv->speed = 1000; 470 else if (bmcr & PHY_BMCR_100_MBPS) 471 priv->speed = 100; 472 } 473 474 return 0; 475 } 476 477 /* 478 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain 479 * circumstances. eg a gigabit TSEC connected to a gigabit switch with 480 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't 481 * link. "Ethernet@Wirespeed" reduces advertised speed until link 482 * can be achieved. 483 */ 484 static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) 485 { 486 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010; 487 } 488 489 /* 490 * Parse the BCM54xx status register for speed and duplex information. 491 * The linux sungem_phy has this information, but in a table format. 492 */ 493 static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 494 { 495 /* If there is no link, speed and duplex don't matter */ 496 if (!priv->link) 497 return 0; 498 499 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> 500 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { 501 case 1: 502 priv->duplexity = 0; 503 priv->speed = 10; 504 break; 505 case 2: 506 priv->duplexity = 1; 507 priv->speed = 10; 508 break; 509 case 3: 510 priv->duplexity = 0; 511 priv->speed = 100; 512 break; 513 case 5: 514 priv->duplexity = 1; 515 priv->speed = 100; 516 break; 517 case 6: 518 priv->duplexity = 0; 519 priv->speed = 1000; 520 break; 521 case 7: 522 priv->duplexity = 1; 523 priv->speed = 1000; 524 break; 525 default: 526 printf("Auto-neg error, defaulting to 10BT/HD\n"); 527 priv->duplexity = 0; 528 priv->speed = 10; 529 break; 530 } 531 532 return 0; 533 } 534 535 /* 536 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg 537 * 0x42 - "Operating Mode Status Register" 538 */ 539 static int BCM8482_is_serdes(struct tsec_private *priv) 540 { 541 u16 val; 542 int serdes = 0; 543 544 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_ER | 0x42); 545 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); 546 547 switch (val & 0x1f) { 548 case 0x0d: /* RGMII-to-100Base-FX */ 549 case 0x0e: /* RGMII-to-SGMII */ 550 case 0x0f: /* RGMII-to-SerDes */ 551 case 0x12: /* SGMII-to-SerDes */ 552 case 0x13: /* SGMII-to-100Base-FX */ 553 case 0x16: /* SerDes-to-Serdes */ 554 serdes = 1; 555 break; 556 case 0x6: /* RGMII-to-Copper */ 557 case 0x14: /* SGMII-to-Copper */ 558 case 0x17: /* SerDes-to-Copper */ 559 break; 560 default: 561 printf("ERROR, invalid PHY mode (0x%x\n)", val); 562 break; 563 } 564 565 return serdes; 566 } 567 568 /* 569 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating 570 * Mode Status Register" 571 */ 572 uint mii_parse_BCM5482_serdes_sr(struct tsec_private *priv) 573 { 574 u16 val; 575 int i = 0; 576 577 /* Wait 1s for link - Clause 37 autonegotiation happens very fast */ 578 while (1) { 579 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, 580 MIIM_BCM54XX_EXP_SEL_ER | 0x42); 581 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA); 582 583 if (val & 0x8000) 584 break; 585 586 if (i++ > 1000) { 587 priv->link = 0; 588 return 1; 589 } 590 591 udelay(1000); /* 1 ms */ 592 } 593 594 priv->link = 1; 595 switch ((val >> 13) & 0x3) { 596 case (0x00): 597 priv->speed = 10; 598 break; 599 case (0x01): 600 priv->speed = 100; 601 break; 602 case (0x02): 603 priv->speed = 1000; 604 break; 605 } 606 607 priv->duplexity = (val & 0x1000) == 0x1000; 608 609 return 0; 610 } 611 612 /* 613 * Figure out if BCM5482 is in serdes or copper mode and determine link 614 * configuration accordingly 615 */ 616 static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv) 617 { 618 if (BCM8482_is_serdes(priv)) { 619 mii_parse_BCM5482_serdes_sr(priv); 620 priv->flags |= TSEC_FIBER; 621 } else { 622 /* Wait for auto-negotiation to complete or fail */ 623 mii_parse_sr(mii_reg, priv); 624 625 /* Parse BCM54xx copper aux status register */ 626 mii_reg = read_phy_reg(priv, MIIM_BCM54xx_AUXSTATUS); 627 mii_parse_BCM54xx_sr(mii_reg, priv); 628 } 629 630 return 0; 631 } 632 633 /* Parse the 88E1011's status register for speed and duplex 634 * information 635 */ 636 static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 637 { 638 uint speed; 639 640 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 641 642 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 643 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 644 int i = 0; 645 646 puts("Waiting for PHY realtime link"); 647 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 648 /* Timeout reached ? */ 649 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 650 puts(" TIMEOUT !\n"); 651 priv->link = 0; 652 break; 653 } 654 655 if ((i++ % 1000) == 0) { 656 putc('.'); 657 } 658 udelay(1000); /* 1 ms */ 659 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 660 } 661 puts(" done\n"); 662 udelay(500000); /* another 500 ms (results in faster booting) */ 663 } else { 664 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 665 priv->link = 1; 666 else 667 priv->link = 0; 668 } 669 670 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 671 priv->duplexity = 1; 672 else 673 priv->duplexity = 0; 674 675 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 676 677 switch (speed) { 678 case MIIM_88E1011_PHYSTAT_GBIT: 679 priv->speed = 1000; 680 break; 681 case MIIM_88E1011_PHYSTAT_100: 682 priv->speed = 100; 683 break; 684 default: 685 priv->speed = 10; 686 } 687 688 return 0; 689 } 690 691 /* Parse the RTL8211B's status register for speed and duplex 692 * information 693 */ 694 static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 695 { 696 uint speed; 697 698 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 699 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 700 int i = 0; 701 702 /* in case of timeout ->link is cleared */ 703 priv->link = 1; 704 puts("Waiting for PHY realtime link"); 705 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 706 /* Timeout reached ? */ 707 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 708 puts(" TIMEOUT !\n"); 709 priv->link = 0; 710 break; 711 } 712 713 if ((i++ % 1000) == 0) { 714 putc('.'); 715 } 716 udelay(1000); /* 1 ms */ 717 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 718 } 719 puts(" done\n"); 720 udelay(500000); /* another 500 ms (results in faster booting) */ 721 } else { 722 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 723 priv->link = 1; 724 else 725 priv->link = 0; 726 } 727 728 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 729 priv->duplexity = 1; 730 else 731 priv->duplexity = 0; 732 733 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 734 735 switch (speed) { 736 case MIIM_RTL8211B_PHYSTAT_GBIT: 737 priv->speed = 1000; 738 break; 739 case MIIM_RTL8211B_PHYSTAT_100: 740 priv->speed = 100; 741 break; 742 default: 743 priv->speed = 10; 744 } 745 746 return 0; 747 } 748 749 /* Parse the cis8201's status register for speed and duplex 750 * information 751 */ 752 static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 753 { 754 uint speed; 755 756 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 757 priv->duplexity = 1; 758 else 759 priv->duplexity = 0; 760 761 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 762 switch (speed) { 763 case MIIM_CIS8201_AUXCONSTAT_GBIT: 764 priv->speed = 1000; 765 break; 766 case MIIM_CIS8201_AUXCONSTAT_100: 767 priv->speed = 100; 768 break; 769 default: 770 priv->speed = 10; 771 break; 772 } 773 774 return 0; 775 } 776 777 /* Parse the vsc8244's status register for speed and duplex 778 * information 779 */ 780 static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 781 { 782 uint speed; 783 784 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 785 priv->duplexity = 1; 786 else 787 priv->duplexity = 0; 788 789 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 790 switch (speed) { 791 case MIIM_VSC8244_AUXCONSTAT_GBIT: 792 priv->speed = 1000; 793 break; 794 case MIIM_VSC8244_AUXCONSTAT_100: 795 priv->speed = 100; 796 break; 797 default: 798 priv->speed = 10; 799 break; 800 } 801 802 return 0; 803 } 804 805 /* Parse the DM9161's status register for speed and duplex 806 * information 807 */ 808 static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 809 { 810 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 811 priv->speed = 100; 812 else 813 priv->speed = 10; 814 815 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 816 priv->duplexity = 1; 817 else 818 priv->duplexity = 0; 819 820 return 0; 821 } 822 823 /* 824 * Hack to write all 4 PHYs with the LED values 825 */ 826 static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 827 { 828 uint phyid; 829 volatile tsec_mdio_t *regbase = priv->phyregs; 830 int timeout = 1000000; 831 832 for (phyid = 0; phyid < 4; phyid++) { 833 regbase->miimadd = (phyid << 8) | mii_reg; 834 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 835 asm("sync"); 836 837 timeout = 1000000; 838 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 839 } 840 841 return MIIM_CIS8204_SLEDCON_INIT; 842 } 843 844 static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 845 { 846 if (priv->flags & TSEC_REDUCED) 847 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 848 else 849 return MIIM_CIS8204_EPHYCON_INIT; 850 } 851 852 static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 853 { 854 uint mii_data = read_phy_reg(priv, mii_reg); 855 856 if (priv->flags & TSEC_REDUCED) 857 mii_data = (mii_data & 0xfff0) | 0x000b; 858 return mii_data; 859 } 860 861 /* Initialized required registers to appropriate values, zeroing 862 * those we don't care about (unless zero is bad, in which case, 863 * choose a more appropriate value) 864 */ 865 static void init_registers(volatile tsec_t * regs) 866 { 867 /* Clear IEVENT */ 868 regs->ievent = IEVENT_INIT_CLEAR; 869 870 regs->imask = IMASK_INIT_CLEAR; 871 872 regs->hash.iaddr0 = 0; 873 regs->hash.iaddr1 = 0; 874 regs->hash.iaddr2 = 0; 875 regs->hash.iaddr3 = 0; 876 regs->hash.iaddr4 = 0; 877 regs->hash.iaddr5 = 0; 878 regs->hash.iaddr6 = 0; 879 regs->hash.iaddr7 = 0; 880 881 regs->hash.gaddr0 = 0; 882 regs->hash.gaddr1 = 0; 883 regs->hash.gaddr2 = 0; 884 regs->hash.gaddr3 = 0; 885 regs->hash.gaddr4 = 0; 886 regs->hash.gaddr5 = 0; 887 regs->hash.gaddr6 = 0; 888 regs->hash.gaddr7 = 0; 889 890 regs->rctrl = 0x00000000; 891 892 /* Init RMON mib registers */ 893 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 894 895 regs->rmon.cam1 = 0xffffffff; 896 regs->rmon.cam2 = 0xffffffff; 897 898 regs->mrblr = MRBLR_INIT_SETTINGS; 899 900 regs->minflr = MINFLR_INIT_SETTINGS; 901 902 regs->attr = ATTR_INIT_SETTINGS; 903 regs->attreli = ATTRELI_INIT_SETTINGS; 904 905 } 906 907 /* Configure maccfg2 based on negotiated speed and duplex 908 * reported by PHY handling code 909 */ 910 static void adjust_link(struct eth_device *dev) 911 { 912 struct tsec_private *priv = (struct tsec_private *)dev->priv; 913 volatile tsec_t *regs = priv->regs; 914 915 if (priv->link) { 916 if (priv->duplexity != 0) 917 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 918 else 919 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 920 921 switch (priv->speed) { 922 case 1000: 923 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 924 | MACCFG2_GMII); 925 break; 926 case 100: 927 case 10: 928 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 929 | MACCFG2_MII); 930 931 /* Set R100 bit in all modes although 932 * it is only used in RGMII mode 933 */ 934 if (priv->speed == 100) 935 regs->ecntrl |= ECNTRL_R100; 936 else 937 regs->ecntrl &= ~(ECNTRL_R100); 938 break; 939 default: 940 printf("%s: Speed was bad\n", dev->name); 941 break; 942 } 943 944 printf("Speed: %d, %s duplex%s\n", priv->speed, 945 (priv->duplexity) ? "full" : "half", 946 (priv->flags & TSEC_FIBER) ? ", fiber mode" : ""); 947 948 } else { 949 printf("%s: No link.\n", dev->name); 950 } 951 } 952 953 /* Set up the buffers and their descriptors, and bring up the 954 * interface 955 */ 956 static void startup_tsec(struct eth_device *dev) 957 { 958 int i; 959 struct tsec_private *priv = (struct tsec_private *)dev->priv; 960 volatile tsec_t *regs = priv->regs; 961 962 /* Point to the buffer descriptors */ 963 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 964 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 965 966 /* Initialize the Rx Buffer descriptors */ 967 for (i = 0; i < PKTBUFSRX; i++) { 968 rtx.rxbd[i].status = RXBD_EMPTY; 969 rtx.rxbd[i].length = 0; 970 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 971 } 972 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 973 974 /* Initialize the TX Buffer Descriptors */ 975 for (i = 0; i < TX_BUF_CNT; i++) { 976 rtx.txbd[i].status = 0; 977 rtx.txbd[i].length = 0; 978 rtx.txbd[i].bufPtr = 0; 979 } 980 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 981 982 /* Start up the PHY */ 983 if(priv->phyinfo) 984 phy_run_commands(priv, priv->phyinfo->startup); 985 986 adjust_link(dev); 987 988 /* Enable Transmit and Receive */ 989 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 990 991 /* Tell the DMA it is clear to go */ 992 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 993 regs->tstat = TSTAT_CLEAR_THALT; 994 regs->rstat = RSTAT_CLEAR_RHALT; 995 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 996 } 997 998 /* This returns the status bits of the device. The return value 999 * is never checked, and this is what the 8260 driver did, so we 1000 * do the same. Presumably, this would be zero if there were no 1001 * errors 1002 */ 1003 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 1004 { 1005 int i; 1006 int result = 0; 1007 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1008 volatile tsec_t *regs = priv->regs; 1009 1010 /* Find an empty buffer descriptor */ 1011 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 1012 if (i >= TOUT_LOOP) { 1013 debug("%s: tsec: tx buffers full\n", dev->name); 1014 return result; 1015 } 1016 } 1017 1018 rtx.txbd[txIdx].bufPtr = (uint) packet; 1019 rtx.txbd[txIdx].length = length; 1020 rtx.txbd[txIdx].status |= 1021 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 1022 1023 /* Tell the DMA to go */ 1024 regs->tstat = TSTAT_CLEAR_THALT; 1025 1026 /* Wait for buffer to be transmitted */ 1027 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 1028 if (i >= TOUT_LOOP) { 1029 debug("%s: tsec: tx error\n", dev->name); 1030 return result; 1031 } 1032 } 1033 1034 txIdx = (txIdx + 1) % TX_BUF_CNT; 1035 result = rtx.txbd[txIdx].status & TXBD_STATS; 1036 1037 return result; 1038 } 1039 1040 static int tsec_recv(struct eth_device *dev) 1041 { 1042 int length; 1043 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1044 volatile tsec_t *regs = priv->regs; 1045 1046 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 1047 1048 length = rtx.rxbd[rxIdx].length; 1049 1050 /* Send the packet up if there were no errors */ 1051 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 1052 NetReceive(NetRxPackets[rxIdx], length - 4); 1053 } else { 1054 printf("Got error %x\n", 1055 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 1056 } 1057 1058 rtx.rxbd[rxIdx].length = 0; 1059 1060 /* Set the wrap bit if this is the last element in the list */ 1061 rtx.rxbd[rxIdx].status = 1062 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 1063 1064 rxIdx = (rxIdx + 1) % PKTBUFSRX; 1065 } 1066 1067 if (regs->ievent & IEVENT_BSY) { 1068 regs->ievent = IEVENT_BSY; 1069 regs->rstat = RSTAT_CLEAR_RHALT; 1070 } 1071 1072 return -1; 1073 1074 } 1075 1076 /* Stop the interface */ 1077 static void tsec_halt(struct eth_device *dev) 1078 { 1079 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1080 volatile tsec_t *regs = priv->regs; 1081 1082 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 1083 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 1084 1085 while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)) 1086 != (IEVENT_GRSC | IEVENT_GTSC)) ; 1087 1088 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 1089 1090 /* Shut down the PHY, as needed */ 1091 if(priv->phyinfo) 1092 phy_run_commands(priv, priv->phyinfo->shutdown); 1093 } 1094 1095 static struct phy_info phy_info_M88E1149S = { 1096 0x1410ca, 1097 "Marvell 88E1149S", 1098 4, 1099 (struct phy_cmd[]) { /* config */ 1100 /* Reset and configure the PHY */ 1101 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1102 {0x1d, 0x1f, NULL}, 1103 {0x1e, 0x200c, NULL}, 1104 {0x1d, 0x5, NULL}, 1105 {0x1e, 0x0, NULL}, 1106 {0x1e, 0x100, NULL}, 1107 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1108 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1109 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1110 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1111 {miim_end,} 1112 }, 1113 (struct phy_cmd[]) { /* startup */ 1114 /* Status is read once to clear old link state */ 1115 {MIIM_STATUS, miim_read, NULL}, 1116 /* Auto-negotiate */ 1117 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1118 /* Read the status */ 1119 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1120 {miim_end,} 1121 }, 1122 (struct phy_cmd[]) { /* shutdown */ 1123 {miim_end,} 1124 }, 1125 }; 1126 1127 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1128 static struct phy_info phy_info_BCM5461S = { 1129 0x02060c1, /* 5461 ID */ 1130 "Broadcom BCM5461S", 1131 0, /* not clear to me what minor revisions we can shift away */ 1132 (struct phy_cmd[]) { /* config */ 1133 /* Reset and configure the PHY */ 1134 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1135 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1136 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1137 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1138 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1139 {miim_end,} 1140 }, 1141 (struct phy_cmd[]) { /* startup */ 1142 /* Status is read once to clear old link state */ 1143 {MIIM_STATUS, miim_read, NULL}, 1144 /* Auto-negotiate */ 1145 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1146 /* Read the status */ 1147 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1148 {miim_end,} 1149 }, 1150 (struct phy_cmd[]) { /* shutdown */ 1151 {miim_end,} 1152 }, 1153 }; 1154 1155 static struct phy_info phy_info_BCM5464S = { 1156 0x02060b1, /* 5464 ID */ 1157 "Broadcom BCM5464S", 1158 0, /* not clear to me what minor revisions we can shift away */ 1159 (struct phy_cmd[]) { /* config */ 1160 /* Reset and configure the PHY */ 1161 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1162 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1163 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1164 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1165 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1166 {miim_end,} 1167 }, 1168 (struct phy_cmd[]) { /* startup */ 1169 /* Status is read once to clear old link state */ 1170 {MIIM_STATUS, miim_read, NULL}, 1171 /* Auto-negotiate */ 1172 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1173 /* Read the status */ 1174 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1175 {miim_end,} 1176 }, 1177 (struct phy_cmd[]) { /* shutdown */ 1178 {miim_end,} 1179 }, 1180 }; 1181 1182 static struct phy_info phy_info_BCM5482S = { 1183 0x0143bcb, 1184 "Broadcom BCM5482S", 1185 4, 1186 (struct phy_cmd[]) { /* config */ 1187 /* Reset and configure the PHY */ 1188 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1189 /* Setup read from auxilary control shadow register 7 */ 1190 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL}, 1191 /* Read Misc Control register and or in Ethernet@Wirespeed */ 1192 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed}, 1193 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1194 /* Initial config/enable of secondary SerDes interface */ 1195 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL}, 1196 /* Write intial value to secondary SerDes Contol */ 1197 {MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_SSD | 0, NULL}, 1198 {MIIM_BCM54XX_EXP_DATA, MIIM_CONTROL_RESTART, NULL}, 1199 /* Enable copper/fiber auto-detect */ 1200 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)}, 1201 {miim_end,} 1202 }, 1203 (struct phy_cmd[]) { /* startup */ 1204 /* Status is read once to clear old link state */ 1205 {MIIM_STATUS, miim_read, NULL}, 1206 /* Determine copper/fiber, auto-negotiate, and read the result */ 1207 {MIIM_STATUS, miim_read, &mii_parse_BCM5482_sr}, 1208 {miim_end,} 1209 }, 1210 (struct phy_cmd[]) { /* shutdown */ 1211 {miim_end,} 1212 }, 1213 }; 1214 1215 static struct phy_info phy_info_M88E1011S = { 1216 0x01410c6, 1217 "Marvell 88E1011S", 1218 4, 1219 (struct phy_cmd[]) { /* config */ 1220 /* Reset and configure the PHY */ 1221 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1222 {0x1d, 0x1f, NULL}, 1223 {0x1e, 0x200c, NULL}, 1224 {0x1d, 0x5, NULL}, 1225 {0x1e, 0x0, NULL}, 1226 {0x1e, 0x100, NULL}, 1227 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1228 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1229 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1230 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1231 {miim_end,} 1232 }, 1233 (struct phy_cmd[]) { /* startup */ 1234 /* Status is read once to clear old link state */ 1235 {MIIM_STATUS, miim_read, NULL}, 1236 /* Auto-negotiate */ 1237 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1238 /* Read the status */ 1239 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1240 {miim_end,} 1241 }, 1242 (struct phy_cmd[]) { /* shutdown */ 1243 {miim_end,} 1244 }, 1245 }; 1246 1247 static struct phy_info phy_info_M88E1111S = { 1248 0x01410cc, 1249 "Marvell 88E1111S", 1250 4, 1251 (struct phy_cmd[]) { /* config */ 1252 /* Reset and configure the PHY */ 1253 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1254 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1255 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1256 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1257 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1258 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1259 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1260 {miim_end,} 1261 }, 1262 (struct phy_cmd[]) { /* startup */ 1263 /* Status is read once to clear old link state */ 1264 {MIIM_STATUS, miim_read, NULL}, 1265 /* Auto-negotiate */ 1266 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1267 /* Read the status */ 1268 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1269 {miim_end,} 1270 }, 1271 (struct phy_cmd[]) { /* shutdown */ 1272 {miim_end,} 1273 }, 1274 }; 1275 1276 static struct phy_info phy_info_M88E1118 = { 1277 0x01410e1, 1278 "Marvell 88E1118", 1279 4, 1280 (struct phy_cmd[]) { /* config */ 1281 /* Reset and configure the PHY */ 1282 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1283 {0x16, 0x0002, NULL}, /* Change Page Number */ 1284 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1285 {0x16, 0x0003, NULL}, /* Change Page Number */ 1286 {0x10, 0x021e, NULL}, /* Adjust LED control */ 1287 {0x16, 0x0000, NULL}, /* Change Page Number */ 1288 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1289 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1290 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1291 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1292 {miim_end,} 1293 }, 1294 (struct phy_cmd[]) { /* startup */ 1295 {0x16, 0x0000, NULL}, /* Change Page Number */ 1296 /* Status is read once to clear old link state */ 1297 {MIIM_STATUS, miim_read, NULL}, 1298 /* Auto-negotiate */ 1299 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1300 /* Read the status */ 1301 {MIIM_88E1011_PHY_STATUS, miim_read, 1302 &mii_parse_88E1011_psr}, 1303 {miim_end,} 1304 }, 1305 (struct phy_cmd[]) { /* shutdown */ 1306 {miim_end,} 1307 }, 1308 }; 1309 1310 /* 1311 * Since to access LED register we need do switch the page, we 1312 * do LED configuring in the miim_read-like function as follows 1313 */ 1314 static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) 1315 { 1316 uint pg; 1317 1318 /* Switch the page to access the led register */ 1319 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE); 1320 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE); 1321 1322 /* Configure leds */ 1323 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL, 1324 MIIM_88E1121_PHY_LED_DEF); 1325 1326 /* Restore the page pointer */ 1327 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg); 1328 return 0; 1329 } 1330 1331 static struct phy_info phy_info_M88E1121R = { 1332 0x01410cb, 1333 "Marvell 88E1121R", 1334 4, 1335 (struct phy_cmd[]) { /* config */ 1336 /* Reset and configure the PHY */ 1337 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1338 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1339 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1340 /* Configure leds */ 1341 {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led}, 1342 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1343 /* Disable IRQs and de-assert interrupt */ 1344 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL}, 1345 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL}, 1346 {miim_end,} 1347 }, 1348 (struct phy_cmd[]) { /* startup */ 1349 /* Status is read once to clear old link state */ 1350 {MIIM_STATUS, miim_read, NULL}, 1351 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1352 {MIIM_STATUS, miim_read, &mii_parse_link}, 1353 {miim_end,} 1354 }, 1355 (struct phy_cmd[]) { /* shutdown */ 1356 {miim_end,} 1357 }, 1358 }; 1359 1360 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1361 { 1362 uint mii_data = read_phy_reg(priv, mii_reg); 1363 1364 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1365 if (priv->flags & TSEC_REDUCED) 1366 return mii_data | 1367 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1368 else 1369 return mii_data; 1370 } 1371 1372 static struct phy_info phy_info_M88E1145 = { 1373 0x01410cd, 1374 "Marvell 88E1145", 1375 4, 1376 (struct phy_cmd[]) { /* config */ 1377 /* Reset the PHY */ 1378 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1379 1380 /* Errata E0, E1 */ 1381 {29, 0x001b, NULL}, 1382 {30, 0x418f, NULL}, 1383 {29, 0x0016, NULL}, 1384 {30, 0xa2da, NULL}, 1385 1386 /* Configure the PHY */ 1387 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1388 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1389 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL}, 1390 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1391 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1392 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1393 {miim_end,} 1394 }, 1395 (struct phy_cmd[]) { /* startup */ 1396 /* Status is read once to clear old link state */ 1397 {MIIM_STATUS, miim_read, NULL}, 1398 /* Auto-negotiate */ 1399 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1400 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1401 /* Read the Status */ 1402 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, 1403 {miim_end,} 1404 }, 1405 (struct phy_cmd[]) { /* shutdown */ 1406 {miim_end,} 1407 }, 1408 }; 1409 1410 static struct phy_info phy_info_cis8204 = { 1411 0x3f11, 1412 "Cicada Cis8204", 1413 6, 1414 (struct phy_cmd[]) { /* config */ 1415 /* Override PHY config settings */ 1416 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1417 /* Configure some basic stuff */ 1418 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1419 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1420 &mii_cis8204_fixled}, 1421 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1422 &mii_cis8204_setmode}, 1423 {miim_end,} 1424 }, 1425 (struct phy_cmd[]) { /* startup */ 1426 /* Read the Status (2x to make sure link is right) */ 1427 {MIIM_STATUS, miim_read, NULL}, 1428 /* Auto-negotiate */ 1429 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1430 /* Read the status */ 1431 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1432 {miim_end,} 1433 }, 1434 (struct phy_cmd[]) { /* shutdown */ 1435 {miim_end,} 1436 }, 1437 }; 1438 1439 /* Cicada 8201 */ 1440 static struct phy_info phy_info_cis8201 = { 1441 0xfc41, 1442 "CIS8201", 1443 4, 1444 (struct phy_cmd[]) { /* config */ 1445 /* Override PHY config settings */ 1446 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1447 /* Set up the interface mode */ 1448 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, 1449 /* Configure some basic stuff */ 1450 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1451 {miim_end,} 1452 }, 1453 (struct phy_cmd[]) { /* startup */ 1454 /* Read the Status (2x to make sure link is right) */ 1455 {MIIM_STATUS, miim_read, NULL}, 1456 /* Auto-negotiate */ 1457 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1458 /* Read the status */ 1459 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1460 {miim_end,} 1461 }, 1462 (struct phy_cmd[]) { /* shutdown */ 1463 {miim_end,} 1464 }, 1465 }; 1466 1467 static struct phy_info phy_info_VSC8211 = { 1468 0xfc4b, 1469 "Vitesse VSC8211", 1470 4, 1471 (struct phy_cmd[]) { /* config */ 1472 /* Override PHY config settings */ 1473 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1474 /* Set up the interface mode */ 1475 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, 1476 /* Configure some basic stuff */ 1477 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1478 {miim_end,} 1479 }, 1480 (struct phy_cmd[]) { /* startup */ 1481 /* Read the Status (2x to make sure link is right) */ 1482 {MIIM_STATUS, miim_read, NULL}, 1483 /* Auto-negotiate */ 1484 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1485 /* Read the status */ 1486 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, 1487 {miim_end,} 1488 }, 1489 (struct phy_cmd[]) { /* shutdown */ 1490 {miim_end,} 1491 }, 1492 }; 1493 1494 static struct phy_info phy_info_VSC8244 = { 1495 0x3f1b, 1496 "Vitesse VSC8244", 1497 6, 1498 (struct phy_cmd[]) { /* config */ 1499 /* Override PHY config settings */ 1500 /* Configure some basic stuff */ 1501 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1502 {miim_end,} 1503 }, 1504 (struct phy_cmd[]) { /* startup */ 1505 /* Read the Status (2x to make sure link is right) */ 1506 {MIIM_STATUS, miim_read, NULL}, 1507 /* Auto-negotiate */ 1508 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1509 /* Read the status */ 1510 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1511 {miim_end,} 1512 }, 1513 (struct phy_cmd[]) { /* shutdown */ 1514 {miim_end,} 1515 }, 1516 }; 1517 1518 static struct phy_info phy_info_VSC8641 = { 1519 0x7043, 1520 "Vitesse VSC8641", 1521 4, 1522 (struct phy_cmd[]) { /* config */ 1523 /* Configure some basic stuff */ 1524 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1525 {miim_end,} 1526 }, 1527 (struct phy_cmd[]) { /* startup */ 1528 /* Read the Status (2x to make sure link is right) */ 1529 {MIIM_STATUS, miim_read, NULL}, 1530 /* Auto-negotiate */ 1531 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1532 /* Read the status */ 1533 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1534 {miim_end,} 1535 }, 1536 (struct phy_cmd[]) { /* shutdown */ 1537 {miim_end,} 1538 }, 1539 }; 1540 1541 static struct phy_info phy_info_VSC8221 = { 1542 0xfc55, 1543 "Vitesse VSC8221", 1544 4, 1545 (struct phy_cmd[]) { /* config */ 1546 /* Configure some basic stuff */ 1547 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1548 {miim_end,} 1549 }, 1550 (struct phy_cmd[]) { /* startup */ 1551 /* Read the Status (2x to make sure link is right) */ 1552 {MIIM_STATUS, miim_read, NULL}, 1553 /* Auto-negotiate */ 1554 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1555 /* Read the status */ 1556 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1557 {miim_end,} 1558 }, 1559 (struct phy_cmd[]) { /* shutdown */ 1560 {miim_end,} 1561 }, 1562 }; 1563 1564 static struct phy_info phy_info_VSC8601 = { 1565 0x00007042, 1566 "Vitesse VSC8601", 1567 4, 1568 (struct phy_cmd[]) { /* config */ 1569 /* Override PHY config settings */ 1570 /* Configure some basic stuff */ 1571 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1572 #ifdef CONFIG_SYS_VSC8601_SKEWFIX 1573 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1574 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) 1575 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1576 #define VSC8101_SKEW \ 1577 (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12) 1578 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1579 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1580 #endif 1581 #endif 1582 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1583 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, 1584 {miim_end,} 1585 }, 1586 (struct phy_cmd[]) { /* startup */ 1587 /* Read the Status (2x to make sure link is right) */ 1588 {MIIM_STATUS, miim_read, NULL}, 1589 /* Auto-negotiate */ 1590 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1591 /* Read the status */ 1592 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244}, 1593 {miim_end,} 1594 }, 1595 (struct phy_cmd[]) { /* shutdown */ 1596 {miim_end,} 1597 }, 1598 }; 1599 1600 static struct phy_info phy_info_dm9161 = { 1601 0x0181b88, 1602 "Davicom DM9161E", 1603 4, 1604 (struct phy_cmd[]) { /* config */ 1605 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1606 /* Do not bypass the scrambler/descrambler */ 1607 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1608 /* Clear 10BTCSR to default */ 1609 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, 1610 /* Configure some basic stuff */ 1611 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1612 /* Restart Auto Negotiation */ 1613 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1614 {miim_end,} 1615 }, 1616 (struct phy_cmd[]) { /* startup */ 1617 /* Status is read once to clear old link state */ 1618 {MIIM_STATUS, miim_read, NULL}, 1619 /* Auto-negotiate */ 1620 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1621 /* Read the status */ 1622 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, 1623 {miim_end,} 1624 }, 1625 (struct phy_cmd[]) { /* shutdown */ 1626 {miim_end,} 1627 }, 1628 }; 1629 1630 /* a generic flavor. */ 1631 static struct phy_info phy_info_generic = { 1632 0, 1633 "Unknown/Generic PHY", 1634 32, 1635 (struct phy_cmd[]) { /* config */ 1636 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1637 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1638 {miim_end,} 1639 }, 1640 (struct phy_cmd[]) { /* startup */ 1641 {PHY_BMSR, miim_read, NULL}, 1642 {PHY_BMSR, miim_read, &mii_parse_sr}, 1643 {PHY_BMSR, miim_read, &mii_parse_link}, 1644 {miim_end,} 1645 }, 1646 (struct phy_cmd[]) { /* shutdown */ 1647 {miim_end,} 1648 } 1649 }; 1650 1651 static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1652 { 1653 unsigned int speed; 1654 if (priv->link) { 1655 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1656 1657 switch (speed) { 1658 case MIIM_LXT971_SR2_10HDX: 1659 priv->speed = 10; 1660 priv->duplexity = 0; 1661 break; 1662 case MIIM_LXT971_SR2_10FDX: 1663 priv->speed = 10; 1664 priv->duplexity = 1; 1665 break; 1666 case MIIM_LXT971_SR2_100HDX: 1667 priv->speed = 100; 1668 priv->duplexity = 0; 1669 break; 1670 default: 1671 priv->speed = 100; 1672 priv->duplexity = 1; 1673 } 1674 } else { 1675 priv->speed = 0; 1676 priv->duplexity = 0; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static struct phy_info phy_info_lxt971 = { 1683 0x0001378e, 1684 "LXT971", 1685 4, 1686 (struct phy_cmd[]) { /* config */ 1687 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1688 {miim_end,} 1689 }, 1690 (struct phy_cmd[]) { /* startup - enable interrupts */ 1691 /* { 0x12, 0x00f2, NULL }, */ 1692 {MIIM_STATUS, miim_read, NULL}, 1693 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1694 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1695 {miim_end,} 1696 }, 1697 (struct phy_cmd[]) { /* shutdown - disable interrupts */ 1698 {miim_end,} 1699 }, 1700 }; 1701 1702 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1703 * information 1704 */ 1705 static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1706 { 1707 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1708 1709 case MIIM_DP83865_SPD_1000: 1710 priv->speed = 1000; 1711 break; 1712 1713 case MIIM_DP83865_SPD_100: 1714 priv->speed = 100; 1715 break; 1716 1717 default: 1718 priv->speed = 10; 1719 break; 1720 1721 } 1722 1723 if (mii_reg & MIIM_DP83865_DPX_FULL) 1724 priv->duplexity = 1; 1725 else 1726 priv->duplexity = 0; 1727 1728 return 0; 1729 } 1730 1731 static struct phy_info phy_info_dp83865 = { 1732 0x20005c7, 1733 "NatSemi DP83865", 1734 4, 1735 (struct phy_cmd[]) { /* config */ 1736 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1737 {miim_end,} 1738 }, 1739 (struct phy_cmd[]) { /* startup */ 1740 /* Status is read once to clear old link state */ 1741 {MIIM_STATUS, miim_read, NULL}, 1742 /* Auto-negotiate */ 1743 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1744 /* Read the link and auto-neg status */ 1745 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr}, 1746 {miim_end,} 1747 }, 1748 (struct phy_cmd[]) { /* shutdown */ 1749 {miim_end,} 1750 }, 1751 }; 1752 1753 static struct phy_info phy_info_rtl8211b = { 1754 0x001cc91, 1755 "RealTek RTL8211B", 1756 4, 1757 (struct phy_cmd[]) { /* config */ 1758 /* Reset and configure the PHY */ 1759 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1760 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1761 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1762 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1763 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1764 {miim_end,} 1765 }, 1766 (struct phy_cmd[]) { /* startup */ 1767 /* Status is read once to clear old link state */ 1768 {MIIM_STATUS, miim_read, NULL}, 1769 /* Auto-negotiate */ 1770 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1771 /* Read the status */ 1772 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1773 {miim_end,} 1774 }, 1775 (struct phy_cmd[]) { /* shutdown */ 1776 {miim_end,} 1777 }, 1778 }; 1779 1780 static struct phy_info *phy_info[] = { 1781 &phy_info_cis8204, 1782 &phy_info_cis8201, 1783 &phy_info_BCM5461S, 1784 &phy_info_BCM5464S, 1785 &phy_info_BCM5482S, 1786 &phy_info_M88E1011S, 1787 &phy_info_M88E1111S, 1788 &phy_info_M88E1118, 1789 &phy_info_M88E1121R, 1790 &phy_info_M88E1145, 1791 &phy_info_M88E1149S, 1792 &phy_info_dm9161, 1793 &phy_info_lxt971, 1794 &phy_info_VSC8211, 1795 &phy_info_VSC8244, 1796 &phy_info_VSC8601, 1797 &phy_info_VSC8641, 1798 &phy_info_VSC8221, 1799 &phy_info_dp83865, 1800 &phy_info_rtl8211b, 1801 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */ 1802 NULL 1803 }; 1804 1805 /* Grab the identifier of the device's PHY, and search through 1806 * all of the known PHYs to see if one matches. If so, return 1807 * it, if not, return NULL 1808 */ 1809 static struct phy_info *get_phy_info(struct eth_device *dev) 1810 { 1811 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1812 uint phy_reg, phy_ID; 1813 int i; 1814 struct phy_info *theInfo = NULL; 1815 1816 /* Grab the bits from PHYIR1, and put them in the upper half */ 1817 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1818 phy_ID = (phy_reg & 0xffff) << 16; 1819 1820 /* Grab the bits from PHYIR2, and put them in the lower half */ 1821 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1822 phy_ID |= (phy_reg & 0xffff); 1823 1824 /* loop through all the known PHY types, and find one that */ 1825 /* matches the ID we read from the PHY. */ 1826 for (i = 0; phy_info[i]; i++) { 1827 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1828 theInfo = phy_info[i]; 1829 break; 1830 } 1831 } 1832 1833 if (theInfo == &phy_info_generic) { 1834 printf("%s: No support for PHY id %x; assuming generic\n", 1835 dev->name, phy_ID); 1836 } else { 1837 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1838 } 1839 1840 return theInfo; 1841 } 1842 1843 /* Execute the given series of commands on the given device's 1844 * PHY, running functions as necessary 1845 */ 1846 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1847 { 1848 int i; 1849 uint result; 1850 volatile tsec_mdio_t *phyregs = priv->phyregs; 1851 1852 phyregs->miimcfg = MIIMCFG_RESET; 1853 1854 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1855 1856 while (phyregs->miimind & MIIMIND_BUSY) ; 1857 1858 for (i = 0; cmd->mii_reg != miim_end; i++) { 1859 if (cmd->mii_data == miim_read) { 1860 result = read_phy_reg(priv, cmd->mii_reg); 1861 1862 if (cmd->funct != NULL) 1863 (*(cmd->funct)) (result, priv); 1864 1865 } else { 1866 if (cmd->funct != NULL) 1867 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1868 else 1869 result = cmd->mii_data; 1870 1871 write_phy_reg(priv, cmd->mii_reg, result); 1872 1873 } 1874 cmd++; 1875 } 1876 } 1877 1878 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1879 && !defined(BITBANGMII) 1880 1881 /* 1882 * Read a MII PHY register. 1883 * 1884 * Returns: 1885 * 0 on success 1886 */ 1887 static int tsec_miiphy_read(char *devname, unsigned char addr, 1888 unsigned char reg, unsigned short *value) 1889 { 1890 unsigned short ret; 1891 struct tsec_private *priv = privlist[0]; 1892 1893 if (NULL == priv) { 1894 printf("Can't read PHY at address %d\n", addr); 1895 return -1; 1896 } 1897 1898 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg); 1899 *value = ret; 1900 1901 return 0; 1902 } 1903 1904 /* 1905 * Write a MII PHY register. 1906 * 1907 * Returns: 1908 * 0 on success 1909 */ 1910 static int tsec_miiphy_write(char *devname, unsigned char addr, 1911 unsigned char reg, unsigned short value) 1912 { 1913 struct tsec_private *priv = privlist[0]; 1914 1915 if (NULL == priv) { 1916 printf("Can't write PHY at address %d\n", addr); 1917 return -1; 1918 } 1919 1920 tsec_local_mdio_write(priv->phyregs, addr, reg, value); 1921 1922 return 0; 1923 } 1924 1925 #endif 1926 1927 #ifdef CONFIG_MCAST_TFTP 1928 1929 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1930 1931 /* Set the appropriate hash bit for the given addr */ 1932 1933 /* The algorithm works like so: 1934 * 1) Take the Destination Address (ie the multicast address), and 1935 * do a CRC on it (little endian), and reverse the bits of the 1936 * result. 1937 * 2) Use the 8 most significant bits as a hash into a 256-entry 1938 * table. The table is controlled through 8 32-bit registers: 1939 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1940 * gaddr7. This means that the 3 most significant bits in the 1941 * hash index which gaddr register to use, and the 5 other bits 1942 * indicate which bit (assuming an IBM numbering scheme, which 1943 * for PowerPC (tm) is usually the case) in the tregister holds 1944 * the entry. */ 1945 static int 1946 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1947 { 1948 struct tsec_private *priv = privlist[1]; 1949 volatile tsec_t *regs = priv->regs; 1950 volatile u32 *reg_array, value; 1951 u8 result, whichbit, whichreg; 1952 1953 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1954 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1955 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1956 value = (1 << (31-whichbit)); 1957 1958 reg_array = &(regs->hash.gaddr0); 1959 1960 if (set) { 1961 reg_array[whichreg] |= value; 1962 } else { 1963 reg_array[whichreg] &= ~value; 1964 } 1965 return 0; 1966 } 1967 #endif /* Multicast TFTP ? */ 1968