1 /* 2 * Freescale Three Speed Ethernet Controller driver 3 * 4 * This software may be used and distributed according to the 5 * terms of the GNU Public License, Version 2, incorporated 6 * herein by reference. 7 * 8 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 9 * (C) Copyright 2003, Motorola, Inc. 10 * author Andy Fleming 11 * 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <malloc.h> 17 #include <net.h> 18 #include <command.h> 19 #include <tsec.h> 20 21 #include "miiphy.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define TX_BUF_CNT 2 26 27 static uint rxIdx; /* index of the current RX buffer */ 28 static uint txIdx; /* index of the current TX buffer */ 29 30 typedef volatile struct rtxbd { 31 txbd8_t txbd[TX_BUF_CNT]; 32 rxbd8_t rxbd[PKTBUFSRX]; 33 } RTXBD; 34 35 #define MAXCONTROLLERS (8) 36 37 static int relocated = 0; 38 39 static struct tsec_private *privlist[MAXCONTROLLERS]; 40 static int num_tsecs = 0; 41 42 #ifdef __GNUC__ 43 static RTXBD rtx __attribute__ ((aligned(8))); 44 #else 45 #error "rtx must be 64-bit aligned" 46 #endif 47 48 static int tsec_send(struct eth_device *dev, 49 volatile void *packet, int length); 50 static int tsec_recv(struct eth_device *dev); 51 static int tsec_init(struct eth_device *dev, bd_t * bd); 52 static void tsec_halt(struct eth_device *dev); 53 static void init_registers(volatile tsec_t * regs); 54 static void startup_tsec(struct eth_device *dev); 55 static int init_phy(struct eth_device *dev); 56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); 57 uint read_phy_reg(struct tsec_private *priv, uint regnum); 58 struct phy_info *get_phy_info(struct eth_device *dev); 59 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); 60 static void adjust_link(struct eth_device *dev); 61 static void relocate_cmds(void); 62 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 63 && !defined(BITBANGMII) 64 static int tsec_miiphy_write(char *devname, unsigned char addr, 65 unsigned char reg, unsigned short value); 66 static int tsec_miiphy_read(char *devname, unsigned char addr, 67 unsigned char reg, unsigned short *value); 68 #endif 69 #ifdef CONFIG_MCAST_TFTP 70 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set); 71 #endif 72 73 /* Default initializations for TSEC controllers. */ 74 75 static struct tsec_info_struct tsec_info[] = { 76 #ifdef CONFIG_TSEC1 77 STD_TSEC_INFO(1), /* TSEC1 */ 78 #endif 79 #ifdef CONFIG_TSEC2 80 STD_TSEC_INFO(2), /* TSEC2 */ 81 #endif 82 #ifdef CONFIG_MPC85XX_FEC 83 { 84 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), 85 .miiregs = (tsec_t *)(TSEC_BASE_ADDR), 86 .devname = CONFIG_MPC85XX_FEC_NAME, 87 .phyaddr = FEC_PHY_ADDR, 88 .flags = FEC_FLAGS 89 }, /* FEC */ 90 #endif 91 #ifdef CONFIG_TSEC3 92 STD_TSEC_INFO(3), /* TSEC3 */ 93 #endif 94 #ifdef CONFIG_TSEC4 95 STD_TSEC_INFO(4), /* TSEC4 */ 96 #endif 97 }; 98 99 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) 100 { 101 int i; 102 103 for (i = 0; i < num; i++) 104 tsec_initialize(bis, &tsecs[i]); 105 106 return 0; 107 } 108 109 int tsec_standard_init(bd_t *bis) 110 { 111 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); 112 } 113 114 /* Initialize device structure. Returns success if PHY 115 * initialization succeeded (i.e. if it recognizes the PHY) 116 */ 117 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) 118 { 119 struct eth_device *dev; 120 int i; 121 struct tsec_private *priv; 122 123 dev = (struct eth_device *)malloc(sizeof *dev); 124 125 if (NULL == dev) 126 return 0; 127 128 memset(dev, 0, sizeof *dev); 129 130 priv = (struct tsec_private *)malloc(sizeof(*priv)); 131 132 if (NULL == priv) 133 return 0; 134 135 privlist[num_tsecs++] = priv; 136 priv->regs = tsec_info->regs; 137 priv->phyregs = tsec_info->miiregs; 138 139 priv->phyaddr = tsec_info->phyaddr; 140 priv->flags = tsec_info->flags; 141 142 sprintf(dev->name, tsec_info->devname); 143 dev->iobase = 0; 144 dev->priv = priv; 145 dev->init = tsec_init; 146 dev->halt = tsec_halt; 147 dev->send = tsec_send; 148 dev->recv = tsec_recv; 149 #ifdef CONFIG_MCAST_TFTP 150 dev->mcast = tsec_mcast_addr; 151 #endif 152 153 /* Tell u-boot to get the addr from the env */ 154 for (i = 0; i < 6; i++) 155 dev->enetaddr[i] = 0; 156 157 eth_register(dev); 158 159 /* Reset the MAC */ 160 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; 161 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); 162 163 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 164 && !defined(BITBANGMII) 165 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); 166 #endif 167 168 /* Try to initialize PHY here, and return */ 169 return init_phy(dev); 170 } 171 172 /* Initializes data structures and registers for the controller, 173 * and brings the interface up. Returns the link status, meaning 174 * that it returns success if the link is up, failure otherwise. 175 * This allows u-boot to find the first active controller. 176 */ 177 int tsec_init(struct eth_device *dev, bd_t * bd) 178 { 179 uint tempval; 180 char tmpbuf[MAC_ADDR_LEN]; 181 int i; 182 struct tsec_private *priv = (struct tsec_private *)dev->priv; 183 volatile tsec_t *regs = priv->regs; 184 185 /* Make sure the controller is stopped */ 186 tsec_halt(dev); 187 188 /* Init MACCFG2. Defaults to GMII */ 189 regs->maccfg2 = MACCFG2_INIT_SETTINGS; 190 191 /* Init ECNTRL */ 192 regs->ecntrl = ECNTRL_INIT_SETTINGS; 193 194 /* Copy the station address into the address registers. 195 * Backwards, because little endian MACS are dumb */ 196 for (i = 0; i < MAC_ADDR_LEN; i++) { 197 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; 198 } 199 regs->macstnaddr1 = *((uint *) (tmpbuf)); 200 201 tempval = *((uint *) (tmpbuf + 4)); 202 203 regs->macstnaddr2 = tempval; 204 205 /* reset the indices to zero */ 206 rxIdx = 0; 207 txIdx = 0; 208 209 /* Clear out (for the most part) the other registers */ 210 init_registers(regs); 211 212 /* Ready the device for tx/rx */ 213 startup_tsec(dev); 214 215 /* If there's no link, fail */ 216 return (priv->link ? 0 : -1); 217 } 218 219 /* Writes the given phy's reg with value, using the specified MDIO regs */ 220 static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, 221 uint reg, uint value) 222 { 223 int timeout = 1000000; 224 225 phyregs->miimadd = (addr << 8) | reg; 226 phyregs->miimcon = value; 227 asm("sync"); 228 229 timeout = 1000000; 230 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ; 231 } 232 233 234 /* Provide the default behavior of writing the PHY of this ethernet device */ 235 #define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value) 236 237 /* Reads register regnum on the device's PHY through the 238 * specified registers. It lowers and raises the read 239 * command, and waits for the data to become valid (miimind 240 * notvalid bit cleared), and the bus to cease activity (miimind 241 * busy bit cleared), and then returns the value 242 */ 243 uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) 244 { 245 uint value; 246 247 /* Put the address of the phy, and the register 248 * number into MIIMADD */ 249 phyregs->miimadd = (phyid << 8) | regnum; 250 251 /* Clear the command register, and wait */ 252 phyregs->miimcom = 0; 253 asm("sync"); 254 255 /* Initiate a read command, and wait */ 256 phyregs->miimcom = MIIM_READ_COMMAND; 257 asm("sync"); 258 259 /* Wait for the the indication that the read is done */ 260 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ; 261 262 /* Grab the value read from the PHY */ 263 value = phyregs->miimstat; 264 265 return value; 266 } 267 268 /* #define to provide old read_phy_reg functionality without duplicating code */ 269 #define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum) 270 271 #define TBIANA_SETTINGS ( \ 272 TBIANA_ASYMMETRIC_PAUSE \ 273 | TBIANA_SYMMETRIC_PAUSE \ 274 | TBIANA_FULL_DUPLEX \ 275 ) 276 277 #define TBICR_SETTINGS ( \ 278 TBICR_PHY_RESET \ 279 | TBICR_ANEG_ENABLE \ 280 | TBICR_FULL_DUPLEX \ 281 | TBICR_SPEED1_SET \ 282 ) 283 /* Configure the TBI for SGMII operation */ 284 static void tsec_configure_serdes(struct tsec_private *priv) 285 { 286 tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_ANA, 287 TBIANA_SETTINGS); 288 tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_TBICON, 289 TBICON_CLK_SELECT); 290 tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_CR, 291 TBICR_SETTINGS); 292 } 293 294 /* Discover which PHY is attached to the device, and configure it 295 * properly. If the PHY is not recognized, then return 0 296 * (failure). Otherwise, return 1 297 */ 298 static int init_phy(struct eth_device *dev) 299 { 300 struct tsec_private *priv = (struct tsec_private *)dev->priv; 301 struct phy_info *curphy; 302 volatile tsec_t *phyregs = priv->phyregs; 303 volatile tsec_t *regs = priv->regs; 304 305 /* Assign a Physical address to the TBI */ 306 regs->tbipa = CFG_TBIPA_VALUE; 307 phyregs->tbipa = CFG_TBIPA_VALUE; 308 asm("sync"); 309 310 /* Reset MII (due to new addresses) */ 311 priv->phyregs->miimcfg = MIIMCFG_RESET; 312 asm("sync"); 313 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 314 asm("sync"); 315 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 316 317 if (0 == relocated) 318 relocate_cmds(); 319 320 /* Get the cmd structure corresponding to the attached 321 * PHY */ 322 curphy = get_phy_info(dev); 323 324 if (curphy == NULL) { 325 priv->phyinfo = NULL; 326 printf("%s: No PHY found\n", dev->name); 327 328 return 0; 329 } 330 331 if (regs->ecntrl & ECNTRL_SGMII_MODE) 332 tsec_configure_serdes(priv); 333 334 priv->phyinfo = curphy; 335 336 phy_run_commands(priv, priv->phyinfo->config); 337 338 return 1; 339 } 340 341 /* 342 * Returns which value to write to the control register. 343 * For 10/100, the value is slightly different 344 */ 345 uint mii_cr_init(uint mii_reg, struct tsec_private * priv) 346 { 347 if (priv->flags & TSEC_GIGABIT) 348 return MIIM_CONTROL_INIT; 349 else 350 return MIIM_CR_INIT; 351 } 352 353 /* Parse the status register for link, and then do 354 * auto-negotiation 355 */ 356 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) 357 { 358 /* 359 * Wait if the link is up, and autonegotiation is in progress 360 * (ie - we're capable and it's not done) 361 */ 362 mii_reg = read_phy_reg(priv, MIIM_STATUS); 363 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) 364 && !(mii_reg & PHY_BMSR_AUTN_COMP)) { 365 int i = 0; 366 367 puts("Waiting for PHY auto negotiation to complete"); 368 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { 369 /* 370 * Timeout reached ? 371 */ 372 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 373 puts(" TIMEOUT !\n"); 374 priv->link = 0; 375 return 0; 376 } 377 378 if ((i++ % 1000) == 0) { 379 putc('.'); 380 } 381 udelay(1000); /* 1 ms */ 382 mii_reg = read_phy_reg(priv, MIIM_STATUS); 383 } 384 puts(" done\n"); 385 priv->link = 1; 386 udelay(500000); /* another 500 ms (results in faster booting) */ 387 } else { 388 if (mii_reg & MIIM_STATUS_LINK) 389 priv->link = 1; 390 else 391 priv->link = 0; 392 } 393 394 return 0; 395 } 396 397 /* Generic function which updates the speed and duplex. If 398 * autonegotiation is enabled, it uses the AND of the link 399 * partner's advertised capabilities and our advertised 400 * capabilities. If autonegotiation is disabled, we use the 401 * appropriate bits in the control register. 402 * 403 * Stolen from Linux's mii.c and phy_device.c 404 */ 405 uint mii_parse_link(uint mii_reg, struct tsec_private *priv) 406 { 407 /* We're using autonegotiation */ 408 if (mii_reg & PHY_BMSR_AUTN_ABLE) { 409 uint lpa = 0; 410 uint gblpa = 0; 411 412 /* Check for gigabit capability */ 413 if (mii_reg & PHY_BMSR_EXT) { 414 /* We want a list of states supported by 415 * both PHYs in the link 416 */ 417 gblpa = read_phy_reg(priv, PHY_1000BTSR); 418 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; 419 } 420 421 /* Set the baseline so we only have to set them 422 * if they're different 423 */ 424 priv->speed = 10; 425 priv->duplexity = 0; 426 427 /* Check the gigabit fields */ 428 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { 429 priv->speed = 1000; 430 431 if (gblpa & PHY_1000BTSR_1000FD) 432 priv->duplexity = 1; 433 434 /* We're done! */ 435 return 0; 436 } 437 438 lpa = read_phy_reg(priv, PHY_ANAR); 439 lpa &= read_phy_reg(priv, PHY_ANLPAR); 440 441 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { 442 priv->speed = 100; 443 444 if (lpa & PHY_ANLPAR_TXFD) 445 priv->duplexity = 1; 446 447 } else if (lpa & PHY_ANLPAR_10FD) 448 priv->duplexity = 1; 449 } else { 450 uint bmcr = read_phy_reg(priv, PHY_BMCR); 451 452 priv->speed = 10; 453 priv->duplexity = 0; 454 455 if (bmcr & PHY_BMCR_DPLX) 456 priv->duplexity = 1; 457 458 if (bmcr & PHY_BMCR_1000_MBPS) 459 priv->speed = 1000; 460 else if (bmcr & PHY_BMCR_100_MBPS) 461 priv->speed = 100; 462 } 463 464 return 0; 465 } 466 467 /* 468 * Parse the BCM54xx status register for speed and duplex information. 469 * The linux sungem_phy has this information, but in a table format. 470 */ 471 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) 472 { 473 474 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ 475 476 case 1: 477 printf("Enet starting in 10BT/HD\n"); 478 priv->duplexity = 0; 479 priv->speed = 10; 480 break; 481 482 case 2: 483 printf("Enet starting in 10BT/FD\n"); 484 priv->duplexity = 1; 485 priv->speed = 10; 486 break; 487 488 case 3: 489 printf("Enet starting in 100BT/HD\n"); 490 priv->duplexity = 0; 491 priv->speed = 100; 492 break; 493 494 case 5: 495 printf("Enet starting in 100BT/FD\n"); 496 priv->duplexity = 1; 497 priv->speed = 100; 498 break; 499 500 case 6: 501 printf("Enet starting in 1000BT/HD\n"); 502 priv->duplexity = 0; 503 priv->speed = 1000; 504 break; 505 506 case 7: 507 printf("Enet starting in 1000BT/FD\n"); 508 priv->duplexity = 1; 509 priv->speed = 1000; 510 break; 511 512 default: 513 printf("Auto-neg error, defaulting to 10BT/HD\n"); 514 priv->duplexity = 0; 515 priv->speed = 10; 516 break; 517 } 518 519 return 0; 520 521 } 522 /* Parse the 88E1011's status register for speed and duplex 523 * information 524 */ 525 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv) 526 { 527 uint speed; 528 529 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 530 531 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 532 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 533 int i = 0; 534 535 puts("Waiting for PHY realtime link"); 536 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 537 /* Timeout reached ? */ 538 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 539 puts(" TIMEOUT !\n"); 540 priv->link = 0; 541 break; 542 } 543 544 if ((i++ % 1000) == 0) { 545 putc('.'); 546 } 547 udelay(1000); /* 1 ms */ 548 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); 549 } 550 puts(" done\n"); 551 udelay(500000); /* another 500 ms (results in faster booting) */ 552 } else { 553 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 554 priv->link = 1; 555 else 556 priv->link = 0; 557 } 558 559 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 560 priv->duplexity = 1; 561 else 562 priv->duplexity = 0; 563 564 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 565 566 switch (speed) { 567 case MIIM_88E1011_PHYSTAT_GBIT: 568 priv->speed = 1000; 569 break; 570 case MIIM_88E1011_PHYSTAT_100: 571 priv->speed = 100; 572 break; 573 default: 574 priv->speed = 10; 575 } 576 577 return 0; 578 } 579 580 /* Parse the RTL8211B's status register for speed and duplex 581 * information 582 */ 583 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv) 584 { 585 uint speed; 586 587 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 588 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 589 int i = 0; 590 591 /* in case of timeout ->link is cleared */ 592 priv->link = 1; 593 puts("Waiting for PHY realtime link"); 594 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) { 595 /* Timeout reached ? */ 596 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 597 puts(" TIMEOUT !\n"); 598 priv->link = 0; 599 break; 600 } 601 602 if ((i++ % 1000) == 0) { 603 putc('.'); 604 } 605 udelay(1000); /* 1 ms */ 606 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS); 607 } 608 puts(" done\n"); 609 udelay(500000); /* another 500 ms (results in faster booting) */ 610 } else { 611 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK) 612 priv->link = 1; 613 else 614 priv->link = 0; 615 } 616 617 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX) 618 priv->duplexity = 1; 619 else 620 priv->duplexity = 0; 621 622 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED); 623 624 switch (speed) { 625 case MIIM_RTL8211B_PHYSTAT_GBIT: 626 priv->speed = 1000; 627 break; 628 case MIIM_RTL8211B_PHYSTAT_100: 629 priv->speed = 100; 630 break; 631 default: 632 priv->speed = 10; 633 } 634 635 return 0; 636 } 637 638 /* Parse the cis8201's status register for speed and duplex 639 * information 640 */ 641 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv) 642 { 643 uint speed; 644 645 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) 646 priv->duplexity = 1; 647 else 648 priv->duplexity = 0; 649 650 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; 651 switch (speed) { 652 case MIIM_CIS8201_AUXCONSTAT_GBIT: 653 priv->speed = 1000; 654 break; 655 case MIIM_CIS8201_AUXCONSTAT_100: 656 priv->speed = 100; 657 break; 658 default: 659 priv->speed = 10; 660 break; 661 } 662 663 return 0; 664 } 665 666 /* Parse the vsc8244's status register for speed and duplex 667 * information 668 */ 669 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv) 670 { 671 uint speed; 672 673 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX) 674 priv->duplexity = 1; 675 else 676 priv->duplexity = 0; 677 678 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED; 679 switch (speed) { 680 case MIIM_VSC8244_AUXCONSTAT_GBIT: 681 priv->speed = 1000; 682 break; 683 case MIIM_VSC8244_AUXCONSTAT_100: 684 priv->speed = 100; 685 break; 686 default: 687 priv->speed = 10; 688 break; 689 } 690 691 return 0; 692 } 693 694 /* Parse the DM9161's status register for speed and duplex 695 * information 696 */ 697 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) 698 { 699 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) 700 priv->speed = 100; 701 else 702 priv->speed = 10; 703 704 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) 705 priv->duplexity = 1; 706 else 707 priv->duplexity = 0; 708 709 return 0; 710 } 711 712 /* 713 * Hack to write all 4 PHYs with the LED values 714 */ 715 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) 716 { 717 uint phyid; 718 volatile tsec_t *regbase = priv->phyregs; 719 int timeout = 1000000; 720 721 for (phyid = 0; phyid < 4; phyid++) { 722 regbase->miimadd = (phyid << 8) | mii_reg; 723 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; 724 asm("sync"); 725 726 timeout = 1000000; 727 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ; 728 } 729 730 return MIIM_CIS8204_SLEDCON_INIT; 731 } 732 733 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) 734 { 735 if (priv->flags & TSEC_REDUCED) 736 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; 737 else 738 return MIIM_CIS8204_EPHYCON_INIT; 739 } 740 741 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) 742 { 743 uint mii_data = read_phy_reg(priv, mii_reg); 744 745 if (priv->flags & TSEC_REDUCED) 746 mii_data = (mii_data & 0xfff0) | 0x000b; 747 return mii_data; 748 } 749 750 /* Initialized required registers to appropriate values, zeroing 751 * those we don't care about (unless zero is bad, in which case, 752 * choose a more appropriate value) 753 */ 754 static void init_registers(volatile tsec_t * regs) 755 { 756 /* Clear IEVENT */ 757 regs->ievent = IEVENT_INIT_CLEAR; 758 759 regs->imask = IMASK_INIT_CLEAR; 760 761 regs->hash.iaddr0 = 0; 762 regs->hash.iaddr1 = 0; 763 regs->hash.iaddr2 = 0; 764 regs->hash.iaddr3 = 0; 765 regs->hash.iaddr4 = 0; 766 regs->hash.iaddr5 = 0; 767 regs->hash.iaddr6 = 0; 768 regs->hash.iaddr7 = 0; 769 770 regs->hash.gaddr0 = 0; 771 regs->hash.gaddr1 = 0; 772 regs->hash.gaddr2 = 0; 773 regs->hash.gaddr3 = 0; 774 regs->hash.gaddr4 = 0; 775 regs->hash.gaddr5 = 0; 776 regs->hash.gaddr6 = 0; 777 regs->hash.gaddr7 = 0; 778 779 regs->rctrl = 0x00000000; 780 781 /* Init RMON mib registers */ 782 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); 783 784 regs->rmon.cam1 = 0xffffffff; 785 regs->rmon.cam2 = 0xffffffff; 786 787 regs->mrblr = MRBLR_INIT_SETTINGS; 788 789 regs->minflr = MINFLR_INIT_SETTINGS; 790 791 regs->attr = ATTR_INIT_SETTINGS; 792 regs->attreli = ATTRELI_INIT_SETTINGS; 793 794 } 795 796 /* Configure maccfg2 based on negotiated speed and duplex 797 * reported by PHY handling code 798 */ 799 static void adjust_link(struct eth_device *dev) 800 { 801 struct tsec_private *priv = (struct tsec_private *)dev->priv; 802 volatile tsec_t *regs = priv->regs; 803 804 if (priv->link) { 805 if (priv->duplexity != 0) 806 regs->maccfg2 |= MACCFG2_FULL_DUPLEX; 807 else 808 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); 809 810 switch (priv->speed) { 811 case 1000: 812 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 813 | MACCFG2_GMII); 814 break; 815 case 100: 816 case 10: 817 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) 818 | MACCFG2_MII); 819 820 /* Set R100 bit in all modes although 821 * it is only used in RGMII mode 822 */ 823 if (priv->speed == 100) 824 regs->ecntrl |= ECNTRL_R100; 825 else 826 regs->ecntrl &= ~(ECNTRL_R100); 827 break; 828 default: 829 printf("%s: Speed was bad\n", dev->name); 830 break; 831 } 832 833 printf("Speed: %d, %s duplex\n", priv->speed, 834 (priv->duplexity) ? "full" : "half"); 835 836 } else { 837 printf("%s: No link.\n", dev->name); 838 } 839 } 840 841 /* Set up the buffers and their descriptors, and bring up the 842 * interface 843 */ 844 static void startup_tsec(struct eth_device *dev) 845 { 846 int i; 847 struct tsec_private *priv = (struct tsec_private *)dev->priv; 848 volatile tsec_t *regs = priv->regs; 849 850 /* Point to the buffer descriptors */ 851 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); 852 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); 853 854 /* Initialize the Rx Buffer descriptors */ 855 for (i = 0; i < PKTBUFSRX; i++) { 856 rtx.rxbd[i].status = RXBD_EMPTY; 857 rtx.rxbd[i].length = 0; 858 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; 859 } 860 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; 861 862 /* Initialize the TX Buffer Descriptors */ 863 for (i = 0; i < TX_BUF_CNT; i++) { 864 rtx.txbd[i].status = 0; 865 rtx.txbd[i].length = 0; 866 rtx.txbd[i].bufPtr = 0; 867 } 868 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; 869 870 /* Start up the PHY */ 871 if(priv->phyinfo) 872 phy_run_commands(priv, priv->phyinfo->startup); 873 874 adjust_link(dev); 875 876 /* Enable Transmit and Receive */ 877 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 878 879 /* Tell the DMA it is clear to go */ 880 regs->dmactrl |= DMACTRL_INIT_SETTINGS; 881 regs->tstat = TSTAT_CLEAR_THALT; 882 regs->rstat = RSTAT_CLEAR_RHALT; 883 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 884 } 885 886 /* This returns the status bits of the device. The return value 887 * is never checked, and this is what the 8260 driver did, so we 888 * do the same. Presumably, this would be zero if there were no 889 * errors 890 */ 891 static int tsec_send(struct eth_device *dev, volatile void *packet, int length) 892 { 893 int i; 894 int result = 0; 895 struct tsec_private *priv = (struct tsec_private *)dev->priv; 896 volatile tsec_t *regs = priv->regs; 897 898 /* Find an empty buffer descriptor */ 899 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 900 if (i >= TOUT_LOOP) { 901 debug("%s: tsec: tx buffers full\n", dev->name); 902 return result; 903 } 904 } 905 906 rtx.txbd[txIdx].bufPtr = (uint) packet; 907 rtx.txbd[txIdx].length = length; 908 rtx.txbd[txIdx].status |= 909 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); 910 911 /* Tell the DMA to go */ 912 regs->tstat = TSTAT_CLEAR_THALT; 913 914 /* Wait for buffer to be transmitted */ 915 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { 916 if (i >= TOUT_LOOP) { 917 debug("%s: tsec: tx error\n", dev->name); 918 return result; 919 } 920 } 921 922 txIdx = (txIdx + 1) % TX_BUF_CNT; 923 result = rtx.txbd[txIdx].status & TXBD_STATS; 924 925 return result; 926 } 927 928 static int tsec_recv(struct eth_device *dev) 929 { 930 int length; 931 struct tsec_private *priv = (struct tsec_private *)dev->priv; 932 volatile tsec_t *regs = priv->regs; 933 934 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { 935 936 length = rtx.rxbd[rxIdx].length; 937 938 /* Send the packet up if there were no errors */ 939 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { 940 NetReceive(NetRxPackets[rxIdx], length - 4); 941 } else { 942 printf("Got error %x\n", 943 (rtx.rxbd[rxIdx].status & RXBD_STATS)); 944 } 945 946 rtx.rxbd[rxIdx].length = 0; 947 948 /* Set the wrap bit if this is the last element in the list */ 949 rtx.rxbd[rxIdx].status = 950 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); 951 952 rxIdx = (rxIdx + 1) % PKTBUFSRX; 953 } 954 955 if (regs->ievent & IEVENT_BSY) { 956 regs->ievent = IEVENT_BSY; 957 regs->rstat = RSTAT_CLEAR_RHALT; 958 } 959 960 return -1; 961 962 } 963 964 /* Stop the interface */ 965 static void tsec_halt(struct eth_device *dev) 966 { 967 struct tsec_private *priv = (struct tsec_private *)dev->priv; 968 volatile tsec_t *regs = priv->regs; 969 970 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); 971 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); 972 973 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; 974 975 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); 976 977 /* Shut down the PHY, as needed */ 978 if(priv->phyinfo) 979 phy_run_commands(priv, priv->phyinfo->shutdown); 980 } 981 982 struct phy_info phy_info_M88E1149S = { 983 0x1410ca, 984 "Marvell 88E1149S", 985 4, 986 (struct phy_cmd[]){ /* config */ 987 /* Reset and configure the PHY */ 988 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 989 {0x1d, 0x1f, NULL}, 990 {0x1e, 0x200c, NULL}, 991 {0x1d, 0x5, NULL}, 992 {0x1e, 0x0, NULL}, 993 {0x1e, 0x100, NULL}, 994 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 995 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 996 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 997 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 998 {miim_end,} 999 }, 1000 (struct phy_cmd[]){ /* startup */ 1001 /* Status is read once to clear old link state */ 1002 {MIIM_STATUS, miim_read, NULL}, 1003 /* Auto-negotiate */ 1004 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1005 /* Read the status */ 1006 {MIIM_88E1011_PHY_STATUS, miim_read, 1007 &mii_parse_88E1011_psr}, 1008 {miim_end,} 1009 }, 1010 (struct phy_cmd[]){ /* shutdown */ 1011 {miim_end,} 1012 }, 1013 }; 1014 1015 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ 1016 struct phy_info phy_info_BCM5461S = { 1017 0x02060c1, /* 5461 ID */ 1018 "Broadcom BCM5461S", 1019 0, /* not clear to me what minor revisions we can shift away */ 1020 (struct phy_cmd[]) { /* config */ 1021 /* Reset and configure the PHY */ 1022 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1023 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1024 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1025 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1026 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1027 {miim_end,} 1028 }, 1029 (struct phy_cmd[]) { /* startup */ 1030 /* Status is read once to clear old link state */ 1031 {MIIM_STATUS, miim_read, NULL}, 1032 /* Auto-negotiate */ 1033 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1034 /* Read the status */ 1035 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1036 {miim_end,} 1037 }, 1038 (struct phy_cmd[]) { /* shutdown */ 1039 {miim_end,} 1040 }, 1041 }; 1042 1043 struct phy_info phy_info_BCM5464S = { 1044 0x02060b1, /* 5464 ID */ 1045 "Broadcom BCM5464S", 1046 0, /* not clear to me what minor revisions we can shift away */ 1047 (struct phy_cmd[]) { /* config */ 1048 /* Reset and configure the PHY */ 1049 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1050 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1051 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1052 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1053 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1054 {miim_end,} 1055 }, 1056 (struct phy_cmd[]) { /* startup */ 1057 /* Status is read once to clear old link state */ 1058 {MIIM_STATUS, miim_read, NULL}, 1059 /* Auto-negotiate */ 1060 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1061 /* Read the status */ 1062 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, 1063 {miim_end,} 1064 }, 1065 (struct phy_cmd[]) { /* shutdown */ 1066 {miim_end,} 1067 }, 1068 }; 1069 1070 struct phy_info phy_info_M88E1011S = { 1071 0x01410c6, 1072 "Marvell 88E1011S", 1073 4, 1074 (struct phy_cmd[]){ /* config */ 1075 /* Reset and configure the PHY */ 1076 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1077 {0x1d, 0x1f, NULL}, 1078 {0x1e, 0x200c, NULL}, 1079 {0x1d, 0x5, NULL}, 1080 {0x1e, 0x0, NULL}, 1081 {0x1e, 0x100, NULL}, 1082 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1083 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1084 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1085 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1086 {miim_end,} 1087 }, 1088 (struct phy_cmd[]){ /* startup */ 1089 /* Status is read once to clear old link state */ 1090 {MIIM_STATUS, miim_read, NULL}, 1091 /* Auto-negotiate */ 1092 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1093 /* Read the status */ 1094 {MIIM_88E1011_PHY_STATUS, miim_read, 1095 &mii_parse_88E1011_psr}, 1096 {miim_end,} 1097 }, 1098 (struct phy_cmd[]){ /* shutdown */ 1099 {miim_end,} 1100 }, 1101 }; 1102 1103 struct phy_info phy_info_M88E1111S = { 1104 0x01410cc, 1105 "Marvell 88E1111S", 1106 4, 1107 (struct phy_cmd[]){ /* config */ 1108 /* Reset and configure the PHY */ 1109 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1110 {0x1b, 0x848f, &mii_m88e1111s_setmode}, 1111 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ 1112 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1113 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1114 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1115 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1116 {miim_end,} 1117 }, 1118 (struct phy_cmd[]){ /* startup */ 1119 /* Status is read once to clear old link state */ 1120 {MIIM_STATUS, miim_read, NULL}, 1121 /* Auto-negotiate */ 1122 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1123 /* Read the status */ 1124 {MIIM_88E1011_PHY_STATUS, miim_read, 1125 &mii_parse_88E1011_psr}, 1126 {miim_end,} 1127 }, 1128 (struct phy_cmd[]){ /* shutdown */ 1129 {miim_end,} 1130 }, 1131 }; 1132 1133 struct phy_info phy_info_M88E1118 = { 1134 0x01410e1, 1135 "Marvell 88E1118", 1136 4, 1137 (struct phy_cmd[]){ /* config */ 1138 /* Reset and configure the PHY */ 1139 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1140 {0x16, 0x0002, NULL}, /* Change Page Number */ 1141 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ 1142 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1143 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1144 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1145 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1146 {miim_end,} 1147 }, 1148 (struct phy_cmd[]){ /* startup */ 1149 {0x16, 0x0000, NULL}, /* Change Page Number */ 1150 /* Status is read once to clear old link state */ 1151 {MIIM_STATUS, miim_read, NULL}, 1152 /* Auto-negotiate */ 1153 /* Read the status */ 1154 {MIIM_88E1011_PHY_STATUS, miim_read, 1155 &mii_parse_88E1011_psr}, 1156 {miim_end,} 1157 }, 1158 (struct phy_cmd[]){ /* shutdown */ 1159 {miim_end,} 1160 }, 1161 }; 1162 1163 /* 1164 * Since to access LED register we need do switch the page, we 1165 * do LED configuring in the miim_read-like function as follows 1166 */ 1167 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv) 1168 { 1169 uint pg; 1170 1171 /* Switch the page to access the led register */ 1172 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE); 1173 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE); 1174 1175 /* Configure leds */ 1176 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL, 1177 MIIM_88E1121_PHY_LED_DEF); 1178 1179 /* Restore the page pointer */ 1180 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg); 1181 return 0; 1182 } 1183 1184 struct phy_info phy_info_M88E1121R = { 1185 0x01410cb, 1186 "Marvell 88E1121R", 1187 4, 1188 (struct phy_cmd[]){ /* config */ 1189 /* Reset and configure the PHY */ 1190 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1191 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1192 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1193 /* Configure leds */ 1194 {MIIM_88E1121_PHY_LED_CTRL, miim_read, 1195 &mii_88E1121_set_led}, 1196 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1197 {miim_end,} 1198 }, 1199 (struct phy_cmd[]){ /* startup */ 1200 /* Status is read once to clear old link state */ 1201 {MIIM_STATUS, miim_read, NULL}, 1202 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1203 {MIIM_STATUS, miim_read, &mii_parse_link}, 1204 {miim_end,} 1205 }, 1206 (struct phy_cmd[]){ /* shutdown */ 1207 {miim_end,} 1208 }, 1209 }; 1210 1211 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) 1212 { 1213 uint mii_data = read_phy_reg(priv, mii_reg); 1214 1215 /* Setting MIIM_88E1145_PHY_EXT_CR */ 1216 if (priv->flags & TSEC_REDUCED) 1217 return mii_data | 1218 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY; 1219 else 1220 return mii_data; 1221 } 1222 1223 static struct phy_info phy_info_M88E1145 = { 1224 0x01410cd, 1225 "Marvell 88E1145", 1226 4, 1227 (struct phy_cmd[]){ /* config */ 1228 /* Reset the PHY */ 1229 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1230 1231 /* Errata E0, E1 */ 1232 {29, 0x001b, NULL}, 1233 {30, 0x418f, NULL}, 1234 {29, 0x0016, NULL}, 1235 {30, 0xa2da, NULL}, 1236 1237 /* Configure the PHY */ 1238 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1239 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1240 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, 1241 NULL}, 1242 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode}, 1243 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1244 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL}, 1245 {miim_end,} 1246 }, 1247 (struct phy_cmd[]){ /* startup */ 1248 /* Status is read once to clear old link state */ 1249 {MIIM_STATUS, miim_read, NULL}, 1250 /* Auto-negotiate */ 1251 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1252 {MIIM_88E1111_PHY_LED_CONTROL, 1253 MIIM_88E1111_PHY_LED_DIRECT, NULL}, 1254 /* Read the Status */ 1255 {MIIM_88E1011_PHY_STATUS, miim_read, 1256 &mii_parse_88E1011_psr}, 1257 {miim_end,} 1258 }, 1259 (struct phy_cmd[]){ /* shutdown */ 1260 {miim_end,} 1261 }, 1262 }; 1263 1264 struct phy_info phy_info_cis8204 = { 1265 0x3f11, 1266 "Cicada Cis8204", 1267 6, 1268 (struct phy_cmd[]){ /* config */ 1269 /* Override PHY config settings */ 1270 {MIIM_CIS8201_AUX_CONSTAT, 1271 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1272 /* Configure some basic stuff */ 1273 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1274 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, 1275 &mii_cis8204_fixled}, 1276 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, 1277 &mii_cis8204_setmode}, 1278 {miim_end,} 1279 }, 1280 (struct phy_cmd[]){ /* startup */ 1281 /* Read the Status (2x to make sure link is right) */ 1282 {MIIM_STATUS, miim_read, NULL}, 1283 /* Auto-negotiate */ 1284 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1285 /* Read the status */ 1286 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1287 &mii_parse_cis8201}, 1288 {miim_end,} 1289 }, 1290 (struct phy_cmd[]){ /* shutdown */ 1291 {miim_end,} 1292 }, 1293 }; 1294 1295 /* Cicada 8201 */ 1296 struct phy_info phy_info_cis8201 = { 1297 0xfc41, 1298 "CIS8201", 1299 4, 1300 (struct phy_cmd[]){ /* config */ 1301 /* Override PHY config settings */ 1302 {MIIM_CIS8201_AUX_CONSTAT, 1303 MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, 1304 /* Set up the interface mode */ 1305 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, 1306 NULL}, 1307 /* Configure some basic stuff */ 1308 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1309 {miim_end,} 1310 }, 1311 (struct phy_cmd[]){ /* startup */ 1312 /* Read the Status (2x to make sure link is right) */ 1313 {MIIM_STATUS, miim_read, NULL}, 1314 /* Auto-negotiate */ 1315 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1316 /* Read the status */ 1317 {MIIM_CIS8201_AUX_CONSTAT, miim_read, 1318 &mii_parse_cis8201}, 1319 {miim_end,} 1320 }, 1321 (struct phy_cmd[]){ /* shutdown */ 1322 {miim_end,} 1323 }, 1324 }; 1325 struct phy_info phy_info_VSC8244 = { 1326 0x3f1b, 1327 "Vitesse VSC8244", 1328 6, 1329 (struct phy_cmd[]){ /* config */ 1330 /* Override PHY config settings */ 1331 /* Configure some basic stuff */ 1332 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1333 {miim_end,} 1334 }, 1335 (struct phy_cmd[]){ /* startup */ 1336 /* Read the Status (2x to make sure link is right) */ 1337 {MIIM_STATUS, miim_read, NULL}, 1338 /* Auto-negotiate */ 1339 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1340 /* Read the status */ 1341 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1342 &mii_parse_vsc8244}, 1343 {miim_end,} 1344 }, 1345 (struct phy_cmd[]){ /* shutdown */ 1346 {miim_end,} 1347 }, 1348 }; 1349 1350 struct phy_info phy_info_VSC8601 = { 1351 0x00007042, 1352 "Vitesse VSC8601", 1353 4, 1354 (struct phy_cmd[]){ /* config */ 1355 /* Override PHY config settings */ 1356 /* Configure some basic stuff */ 1357 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1358 #ifdef CFG_VSC8601_SKEWFIX 1359 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, 1360 #if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX) 1361 {MIIM_EXT_PAGE_ACCESS,1,NULL}, 1362 #define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12) 1363 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, 1364 {MIIM_EXT_PAGE_ACCESS,0,NULL}, 1365 #endif 1366 #endif 1367 {miim_end,} 1368 }, 1369 (struct phy_cmd[]){ /* startup */ 1370 /* Read the Status (2x to make sure link is right) */ 1371 {MIIM_STATUS, miim_read, NULL}, 1372 /* Auto-negotiate */ 1373 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1374 /* Read the status */ 1375 {MIIM_VSC8244_AUX_CONSTAT, miim_read, 1376 &mii_parse_vsc8244}, 1377 {miim_end,} 1378 }, 1379 (struct phy_cmd[]){ /* shutdown */ 1380 {miim_end,} 1381 }, 1382 }; 1383 1384 1385 struct phy_info phy_info_dm9161 = { 1386 0x0181b88, 1387 "Davicom DM9161E", 1388 4, 1389 (struct phy_cmd[]){ /* config */ 1390 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, 1391 /* Do not bypass the scrambler/descrambler */ 1392 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, 1393 /* Clear 10BTCSR to default */ 1394 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, 1395 NULL}, 1396 /* Configure some basic stuff */ 1397 {MIIM_CONTROL, MIIM_CR_INIT, NULL}, 1398 /* Restart Auto Negotiation */ 1399 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, 1400 {miim_end,} 1401 }, 1402 (struct phy_cmd[]){ /* startup */ 1403 /* Status is read once to clear old link state */ 1404 {MIIM_STATUS, miim_read, NULL}, 1405 /* Auto-negotiate */ 1406 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1407 /* Read the status */ 1408 {MIIM_DM9161_SCSR, miim_read, 1409 &mii_parse_dm9161_scsr}, 1410 {miim_end,} 1411 }, 1412 (struct phy_cmd[]){ /* shutdown */ 1413 {miim_end,} 1414 }, 1415 }; 1416 /* a generic flavor. */ 1417 struct phy_info phy_info_generic = { 1418 0, 1419 "Unknown/Generic PHY", 1420 32, 1421 (struct phy_cmd[]) { /* config */ 1422 {PHY_BMCR, PHY_BMCR_RESET, NULL}, 1423 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, 1424 {miim_end,} 1425 }, 1426 (struct phy_cmd[]) { /* startup */ 1427 {PHY_BMSR, miim_read, NULL}, 1428 {PHY_BMSR, miim_read, &mii_parse_sr}, 1429 {PHY_BMSR, miim_read, &mii_parse_link}, 1430 {miim_end,} 1431 }, 1432 (struct phy_cmd[]) { /* shutdown */ 1433 {miim_end,} 1434 } 1435 }; 1436 1437 1438 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) 1439 { 1440 unsigned int speed; 1441 if (priv->link) { 1442 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; 1443 1444 switch (speed) { 1445 case MIIM_LXT971_SR2_10HDX: 1446 priv->speed = 10; 1447 priv->duplexity = 0; 1448 break; 1449 case MIIM_LXT971_SR2_10FDX: 1450 priv->speed = 10; 1451 priv->duplexity = 1; 1452 break; 1453 case MIIM_LXT971_SR2_100HDX: 1454 priv->speed = 100; 1455 priv->duplexity = 0; 1456 break; 1457 default: 1458 priv->speed = 100; 1459 priv->duplexity = 1; 1460 } 1461 } else { 1462 priv->speed = 0; 1463 priv->duplexity = 0; 1464 } 1465 1466 return 0; 1467 } 1468 1469 static struct phy_info phy_info_lxt971 = { 1470 0x0001378e, 1471 "LXT971", 1472 4, 1473 (struct phy_cmd[]){ /* config */ 1474 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */ 1475 {miim_end,} 1476 }, 1477 (struct phy_cmd[]){ /* startup - enable interrupts */ 1478 /* { 0x12, 0x00f2, NULL }, */ 1479 {MIIM_STATUS, miim_read, NULL}, 1480 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1481 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2}, 1482 {miim_end,} 1483 }, 1484 (struct phy_cmd[]){ /* shutdown - disable interrupts */ 1485 {miim_end,} 1486 }, 1487 }; 1488 1489 /* Parse the DP83865's link and auto-neg status register for speed and duplex 1490 * information 1491 */ 1492 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) 1493 { 1494 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 1495 1496 case MIIM_DP83865_SPD_1000: 1497 priv->speed = 1000; 1498 break; 1499 1500 case MIIM_DP83865_SPD_100: 1501 priv->speed = 100; 1502 break; 1503 1504 default: 1505 priv->speed = 10; 1506 break; 1507 1508 } 1509 1510 if (mii_reg & MIIM_DP83865_DPX_FULL) 1511 priv->duplexity = 1; 1512 else 1513 priv->duplexity = 0; 1514 1515 return 0; 1516 } 1517 1518 struct phy_info phy_info_dp83865 = { 1519 0x20005c7, 1520 "NatSemi DP83865", 1521 4, 1522 (struct phy_cmd[]){ /* config */ 1523 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, 1524 {miim_end,} 1525 }, 1526 (struct phy_cmd[]){ /* startup */ 1527 /* Status is read once to clear old link state */ 1528 {MIIM_STATUS, miim_read, NULL}, 1529 /* Auto-negotiate */ 1530 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1531 /* Read the link and auto-neg status */ 1532 {MIIM_DP83865_LANR, miim_read, 1533 &mii_parse_dp83865_lanr}, 1534 {miim_end,} 1535 }, 1536 (struct phy_cmd[]){ /* shutdown */ 1537 {miim_end,} 1538 }, 1539 }; 1540 1541 struct phy_info phy_info_rtl8211b = { 1542 0x001cc91, 1543 "RealTek RTL8211B", 1544 4, 1545 (struct phy_cmd[]){ /* config */ 1546 /* Reset and configure the PHY */ 1547 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1548 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 1549 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 1550 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 1551 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 1552 {miim_end,} 1553 }, 1554 (struct phy_cmd[]){ /* startup */ 1555 /* Status is read once to clear old link state */ 1556 {MIIM_STATUS, miim_read, NULL}, 1557 /* Auto-negotiate */ 1558 {MIIM_STATUS, miim_read, &mii_parse_sr}, 1559 /* Read the status */ 1560 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr}, 1561 {miim_end,} 1562 }, 1563 (struct phy_cmd[]){ /* shutdown */ 1564 {miim_end,} 1565 }, 1566 }; 1567 1568 struct phy_info *phy_info[] = { 1569 &phy_info_cis8204, 1570 &phy_info_cis8201, 1571 &phy_info_BCM5461S, 1572 &phy_info_BCM5464S, 1573 &phy_info_M88E1011S, 1574 &phy_info_M88E1111S, 1575 &phy_info_M88E1118, 1576 &phy_info_M88E1121R, 1577 &phy_info_M88E1145, 1578 &phy_info_M88E1149S, 1579 &phy_info_dm9161, 1580 &phy_info_lxt971, 1581 &phy_info_VSC8244, 1582 &phy_info_VSC8601, 1583 &phy_info_dp83865, 1584 &phy_info_rtl8211b, 1585 &phy_info_generic, 1586 NULL 1587 }; 1588 1589 /* Grab the identifier of the device's PHY, and search through 1590 * all of the known PHYs to see if one matches. If so, return 1591 * it, if not, return NULL 1592 */ 1593 struct phy_info *get_phy_info(struct eth_device *dev) 1594 { 1595 struct tsec_private *priv = (struct tsec_private *)dev->priv; 1596 uint phy_reg, phy_ID; 1597 int i; 1598 struct phy_info *theInfo = NULL; 1599 1600 /* Grab the bits from PHYIR1, and put them in the upper half */ 1601 phy_reg = read_phy_reg(priv, MIIM_PHYIR1); 1602 phy_ID = (phy_reg & 0xffff) << 16; 1603 1604 /* Grab the bits from PHYIR2, and put them in the lower half */ 1605 phy_reg = read_phy_reg(priv, MIIM_PHYIR2); 1606 phy_ID |= (phy_reg & 0xffff); 1607 1608 /* loop through all the known PHY types, and find one that */ 1609 /* matches the ID we read from the PHY. */ 1610 for (i = 0; phy_info[i]; i++) { 1611 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 1612 theInfo = phy_info[i]; 1613 break; 1614 } 1615 } 1616 1617 if (theInfo == NULL) { 1618 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); 1619 return NULL; 1620 } else { 1621 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 1622 } 1623 1624 return theInfo; 1625 } 1626 1627 /* Execute the given series of commands on the given device's 1628 * PHY, running functions as necessary 1629 */ 1630 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) 1631 { 1632 int i; 1633 uint result; 1634 volatile tsec_t *phyregs = priv->phyregs; 1635 1636 phyregs->miimcfg = MIIMCFG_RESET; 1637 1638 phyregs->miimcfg = MIIMCFG_INIT_VALUE; 1639 1640 while (phyregs->miimind & MIIMIND_BUSY) ; 1641 1642 for (i = 0; cmd->mii_reg != miim_end; i++) { 1643 if (cmd->mii_data == miim_read) { 1644 result = read_phy_reg(priv, cmd->mii_reg); 1645 1646 if (cmd->funct != NULL) 1647 (*(cmd->funct)) (result, priv); 1648 1649 } else { 1650 if (cmd->funct != NULL) 1651 result = (*(cmd->funct)) (cmd->mii_reg, priv); 1652 else 1653 result = cmd->mii_data; 1654 1655 write_phy_reg(priv, cmd->mii_reg, result); 1656 1657 } 1658 cmd++; 1659 } 1660 } 1661 1662 /* Relocate the function pointers in the phy cmd lists */ 1663 static void relocate_cmds(void) 1664 { 1665 struct phy_cmd **cmdlistptr; 1666 struct phy_cmd *cmd; 1667 int i, j, k; 1668 1669 for (i = 0; phy_info[i]; i++) { 1670 /* First thing's first: relocate the pointers to the 1671 * PHY command structures (the structs were done) */ 1672 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 1673 + gd->reloc_off); 1674 phy_info[i]->name += gd->reloc_off; 1675 phy_info[i]->config = 1676 (struct phy_cmd *)((uint) phy_info[i]->config 1677 + gd->reloc_off); 1678 phy_info[i]->startup = 1679 (struct phy_cmd *)((uint) phy_info[i]->startup 1680 + gd->reloc_off); 1681 phy_info[i]->shutdown = 1682 (struct phy_cmd *)((uint) phy_info[i]->shutdown 1683 + gd->reloc_off); 1684 1685 cmdlistptr = &phy_info[i]->config; 1686 j = 0; 1687 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { 1688 k = 0; 1689 for (cmd = *cmdlistptr; 1690 cmd->mii_reg != miim_end; 1691 cmd++) { 1692 /* Only relocate non-NULL pointers */ 1693 if (cmd->funct) 1694 cmd->funct += gd->reloc_off; 1695 1696 k++; 1697 } 1698 j++; 1699 } 1700 } 1701 1702 relocated = 1; 1703 } 1704 1705 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ 1706 && !defined(BITBANGMII) 1707 1708 /* 1709 * Read a MII PHY register. 1710 * 1711 * Returns: 1712 * 0 on success 1713 */ 1714 static int tsec_miiphy_read(char *devname, unsigned char addr, 1715 unsigned char reg, unsigned short *value) 1716 { 1717 unsigned short ret; 1718 struct tsec_private *priv = privlist[0]; 1719 1720 if (NULL == priv) { 1721 printf("Can't read PHY at address %d\n", addr); 1722 return -1; 1723 } 1724 1725 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg); 1726 *value = ret; 1727 1728 return 0; 1729 } 1730 1731 /* 1732 * Write a MII PHY register. 1733 * 1734 * Returns: 1735 * 0 on success 1736 */ 1737 static int tsec_miiphy_write(char *devname, unsigned char addr, 1738 unsigned char reg, unsigned short value) 1739 { 1740 struct tsec_private *priv = privlist[0]; 1741 1742 if (NULL == priv) { 1743 printf("Can't write PHY at address %d\n", addr); 1744 return -1; 1745 } 1746 1747 tsec_local_mdio_write(priv->phyregs, addr, reg, value); 1748 1749 return 0; 1750 } 1751 1752 #endif 1753 1754 #ifdef CONFIG_MCAST_TFTP 1755 1756 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ 1757 1758 /* Set the appropriate hash bit for the given addr */ 1759 1760 /* The algorithm works like so: 1761 * 1) Take the Destination Address (ie the multicast address), and 1762 * do a CRC on it (little endian), and reverse the bits of the 1763 * result. 1764 * 2) Use the 8 most significant bits as a hash into a 256-entry 1765 * table. The table is controlled through 8 32-bit registers: 1766 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 1767 * gaddr7. This means that the 3 most significant bits in the 1768 * hash index which gaddr register to use, and the 5 other bits 1769 * indicate which bit (assuming an IBM numbering scheme, which 1770 * for PowerPC (tm) is usually the case) in the tregister holds 1771 * the entry. */ 1772 static int 1773 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) 1774 { 1775 struct tsec_private *priv = privlist[1]; 1776 volatile tsec_t *regs = priv->regs; 1777 volatile u32 *reg_array, value; 1778 u8 result, whichbit, whichreg; 1779 1780 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); 1781 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ 1782 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ 1783 value = (1 << (31-whichbit)); 1784 1785 reg_array = &(regs->hash.gaddr0); 1786 1787 if (set) { 1788 reg_array[whichreg] |= value; 1789 } else { 1790 reg_array[whichreg] &= ~value; 1791 } 1792 return 0; 1793 } 1794 #endif /* Multicast TFTP ? */ 1795