1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Ethernet driver for TI K2HK EVM. 4 * 5 * (C) Copyright 2012-2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 #include <common.h> 9 #include <command.h> 10 #include <console.h> 11 12 #include <dm.h> 13 #include <dm/lists.h> 14 15 #include <net.h> 16 #include <phy.h> 17 #include <errno.h> 18 #include <miiphy.h> 19 #include <malloc.h> 20 #include <asm/ti-common/keystone_nav.h> 21 #include <asm/ti-common/keystone_net.h> 22 #include <asm/ti-common/keystone_serdes.h> 23 #include <asm/arch/psc_defs.h> 24 25 #include "cpsw_mdio.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #ifdef KEYSTONE2_EMAC_GIG_ENABLE 30 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) 31 #else 32 #define emac_gigabit_enable(x) /* no gigabit to enable */ 33 #endif 34 35 #define RX_BUFF_NUMS 24 36 #define RX_BUFF_LEN 1520 37 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN 38 #define SGMII_ANEG_TIMEOUT 4000 39 40 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); 41 42 enum link_type { 43 LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0, 44 LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1, 45 LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2, 46 LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3, 47 LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4, 48 LINK_TYPE_RGMII_LINK_MAC_PHY = 5, 49 LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6, 50 LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7, 51 LINK_TYPE_10G_MAC_TO_PHY_MODE = 10, 52 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11, 53 }; 54 55 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 56 ((mac)[2] << 16) | ((mac)[3] << 24)) 57 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 58 59 #ifdef CONFIG_KSNET_NETCP_V1_0 60 61 #define EMAC_EMACSW_BASE_OFS 0x90800 62 #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60) 63 64 /* CPSW Switch slave registers */ 65 #define CPGMACSL_REG_SA_LO 0x10 66 #define CPGMACSL_REG_SA_HI 0x14 67 68 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ 69 (x) * 0x30) 70 71 #elif defined(CONFIG_KSNET_NETCP_V1_5) 72 73 #define EMAC_EMACSW_PORT_BASE_OFS 0x222000 74 75 /* CPSW Switch slave registers */ 76 #define CPGMACSL_REG_SA_LO 0x308 77 #define CPGMACSL_REG_SA_HI 0x30c 78 79 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ 80 (x) * 0x1000) 81 82 #endif 83 84 85 struct ks2_eth_priv { 86 struct udevice *dev; 87 struct phy_device *phydev; 88 struct mii_dev *mdio_bus; 89 int phy_addr; 90 phy_interface_t phy_if; 91 int sgmii_link_type; 92 void *mdio_base; 93 struct rx_buff_desc net_rx_buffs; 94 struct pktdma_cfg *netcp_pktdma; 95 void *hd; 96 int slave_port; 97 enum link_type link_type; 98 bool emac_open; 99 bool has_mdio; 100 }; 101 102 static void __attribute__((unused)) 103 keystone2_eth_gigabit_enable(struct udevice *dev) 104 { 105 struct ks2_eth_priv *priv = dev_get_priv(dev); 106 107 /* 108 * Check if link detected is giga-bit 109 * If Gigabit mode detected, enable gigbit in MAC 110 */ 111 if (priv->has_mdio) { 112 if (priv->phydev->speed != 1000) 113 return; 114 } 115 116 writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) + 117 CPGMACSL_REG_CTL) | 118 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, 119 DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL); 120 } 121 122 #ifdef CONFIG_SOC_K2G 123 int keystone_rgmii_config(struct phy_device *phy_dev) 124 { 125 unsigned int i, status; 126 127 i = 0; 128 do { 129 if (i > SGMII_ANEG_TIMEOUT) { 130 puts(" TIMEOUT !\n"); 131 phy_dev->link = 0; 132 return 0; 133 } 134 135 if (ctrlc()) { 136 puts("user interrupt!\n"); 137 phy_dev->link = 0; 138 return -EINTR; 139 } 140 141 if ((i++ % 500) == 0) 142 printf("."); 143 144 udelay(1000); /* 1 ms */ 145 status = readl(RGMII_STATUS_REG); 146 } while (!(status & RGMII_REG_STATUS_LINK)); 147 148 puts(" done\n"); 149 150 return 0; 151 } 152 #else 153 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) 154 { 155 unsigned int i, status, mask; 156 unsigned int mr_adv_ability, control; 157 158 switch (interface) { 159 case SGMII_LINK_MAC_MAC_AUTONEG: 160 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 161 SGMII_REG_MR_ADV_LINK | 162 SGMII_REG_MR_ADV_FULL_DUPLEX | 163 SGMII_REG_MR_ADV_GIG_MODE); 164 control = (SGMII_REG_CONTROL_MASTER | 165 SGMII_REG_CONTROL_AUTONEG); 166 167 break; 168 case SGMII_LINK_MAC_PHY: 169 case SGMII_LINK_MAC_PHY_FORCED: 170 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 171 control = SGMII_REG_CONTROL_AUTONEG; 172 173 break; 174 case SGMII_LINK_MAC_MAC_FORCED: 175 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | 176 SGMII_REG_MR_ADV_LINK | 177 SGMII_REG_MR_ADV_FULL_DUPLEX | 178 SGMII_REG_MR_ADV_GIG_MODE); 179 control = SGMII_REG_CONTROL_MASTER; 180 181 break; 182 case SGMII_LINK_MAC_FIBER: 183 mr_adv_ability = 0x20; 184 control = SGMII_REG_CONTROL_AUTONEG; 185 186 break; 187 default: 188 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; 189 control = SGMII_REG_CONTROL_AUTONEG; 190 } 191 192 __raw_writel(0, SGMII_CTL_REG(port)); 193 194 /* 195 * Wait for the SerDes pll to lock, 196 * but don't trap if lock is never read 197 */ 198 for (i = 0; i < 1000; i++) { 199 udelay(2000); 200 status = __raw_readl(SGMII_STATUS_REG(port)); 201 if ((status & SGMII_REG_STATUS_LOCK) != 0) 202 break; 203 } 204 205 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); 206 __raw_writel(control, SGMII_CTL_REG(port)); 207 208 209 mask = SGMII_REG_STATUS_LINK; 210 211 if (control & SGMII_REG_CONTROL_AUTONEG) 212 mask |= SGMII_REG_STATUS_AUTONEG; 213 214 status = __raw_readl(SGMII_STATUS_REG(port)); 215 if ((status & mask) == mask) 216 return 0; 217 218 printf("\n%s Waiting for SGMII auto negotiation to complete", 219 phy_dev->dev->name); 220 while ((status & mask) != mask) { 221 /* 222 * Timeout reached ? 223 */ 224 if (i > SGMII_ANEG_TIMEOUT) { 225 puts(" TIMEOUT !\n"); 226 phy_dev->link = 0; 227 return 0; 228 } 229 230 if (ctrlc()) { 231 puts("user interrupt!\n"); 232 phy_dev->link = 0; 233 return -EINTR; 234 } 235 236 if ((i++ % 500) == 0) 237 printf("."); 238 239 udelay(1000); /* 1 ms */ 240 status = __raw_readl(SGMII_STATUS_REG(port)); 241 } 242 puts(" done\n"); 243 244 return 0; 245 } 246 #endif 247 248 int mac_sl_reset(u32 port) 249 { 250 u32 i, v; 251 252 if (port >= DEVICE_N_GMACSL_PORTS) 253 return GMACSL_RET_INVALID_PORT; 254 255 /* Set the soft reset bit */ 256 writel(CPGMAC_REG_RESET_VAL_RESET, 257 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 258 259 /* Wait for the bit to clear */ 260 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 261 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 262 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 263 CPGMAC_REG_RESET_VAL_RESET) 264 return GMACSL_RET_OK; 265 } 266 267 /* Timeout on the reset */ 268 return GMACSL_RET_WARN_RESET_INCOMPLETE; 269 } 270 271 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) 272 { 273 u32 v, i; 274 int ret = GMACSL_RET_OK; 275 276 if (port >= DEVICE_N_GMACSL_PORTS) 277 return GMACSL_RET_INVALID_PORT; 278 279 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { 280 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; 281 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; 282 } 283 284 /* Must wait if the device is undergoing reset */ 285 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { 286 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); 287 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != 288 CPGMAC_REG_RESET_VAL_RESET) 289 break; 290 } 291 292 if (i == DEVICE_EMACSL_RESET_POLL_COUNT) 293 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; 294 295 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); 296 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); 297 298 #ifndef CONFIG_SOC_K2HK 299 /* Map RX packet flow priority to 0 */ 300 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); 301 #endif 302 303 return ret; 304 } 305 306 int ethss_config(u32 ctl, u32 max_pkt_size) 307 { 308 u32 i; 309 310 /* Max length register */ 311 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN); 312 313 /* Control register */ 314 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL); 315 316 /* All statistics enabled by default */ 317 writel(CPSW_REG_VAL_STAT_ENABLE_ALL, 318 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN); 319 320 /* Reset and enable the ALE */ 321 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | 322 CPSW_REG_VAL_ALE_CTL_BYPASS, 323 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL); 324 325 /* All ports put into forward mode */ 326 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) 327 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE, 328 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i)); 329 330 return 0; 331 } 332 333 int ethss_start(void) 334 { 335 int i; 336 struct mac_sl_cfg cfg; 337 338 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; 339 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; 340 341 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { 342 mac_sl_reset(i); 343 mac_sl_config(i, &cfg); 344 } 345 346 return 0; 347 } 348 349 int ethss_stop(void) 350 { 351 int i; 352 353 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) 354 mac_sl_reset(i); 355 356 return 0; 357 } 358 359 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { 360 .clk = SERDES_CLOCK_156P25M, 361 .rate = SERDES_RATE_5G, 362 .rate_mode = SERDES_QUARTER_RATE, 363 .intf = SERDES_PHY_SGMII, 364 .loopback = 0, 365 }; 366 367 #ifndef CONFIG_SOC_K2G 368 static void keystone2_net_serdes_setup(void) 369 { 370 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, 371 &ks2_serdes_sgmii_156p25mhz, 372 CONFIG_KSNET_SERDES_LANES_PER_SGMII); 373 374 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) 375 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, 376 &ks2_serdes_sgmii_156p25mhz, 377 CONFIG_KSNET_SERDES_LANES_PER_SGMII); 378 #endif 379 380 /* wait till setup */ 381 udelay(5000); 382 } 383 #endif 384 385 static int ks2_eth_start(struct udevice *dev) 386 { 387 struct ks2_eth_priv *priv = dev_get_priv(dev); 388 389 #ifdef CONFIG_SOC_K2G 390 keystone_rgmii_config(priv->phydev); 391 #else 392 keystone_sgmii_config(priv->phydev, priv->slave_port - 1, 393 priv->sgmii_link_type); 394 #endif 395 396 udelay(10000); 397 398 /* On chip switch configuration */ 399 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); 400 401 qm_init(); 402 403 if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) { 404 pr_err("ksnav_init failed\n"); 405 goto err_knav_init; 406 } 407 408 /* 409 * Streaming switch configuration. If not present this 410 * statement is defined to void in target.h. 411 * If present this is usually defined to a series of register writes 412 */ 413 hw_config_streaming_switch(); 414 415 if (priv->has_mdio) { 416 phy_startup(priv->phydev); 417 if (priv->phydev->link == 0) { 418 pr_err("phy startup failed\n"); 419 goto err_phy_start; 420 } 421 } 422 423 emac_gigabit_enable(dev); 424 425 ethss_start(); 426 427 priv->emac_open = true; 428 429 return 0; 430 431 err_phy_start: 432 ksnav_close(priv->netcp_pktdma); 433 err_knav_init: 434 qm_close(); 435 436 return -EFAULT; 437 } 438 439 static int ks2_eth_send(struct udevice *dev, void *packet, int length) 440 { 441 struct ks2_eth_priv *priv = dev_get_priv(dev); 442 443 genphy_update_link(priv->phydev); 444 if (priv->phydev->link == 0) 445 return -1; 446 447 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) 448 length = EMAC_MIN_ETHERNET_PKT_SIZE; 449 450 return ksnav_send(priv->netcp_pktdma, (u32 *)packet, 451 length, (priv->slave_port) << 16); 452 } 453 454 static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp) 455 { 456 struct ks2_eth_priv *priv = dev_get_priv(dev); 457 int pkt_size; 458 u32 *pkt = NULL; 459 460 priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size); 461 if (priv->hd == NULL) 462 return -EAGAIN; 463 464 *packetp = (uchar *)pkt; 465 466 return pkt_size; 467 } 468 469 static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet, 470 int length) 471 { 472 struct ks2_eth_priv *priv = dev_get_priv(dev); 473 474 ksnav_release_rxhd(priv->netcp_pktdma, priv->hd); 475 476 return 0; 477 } 478 479 static void ks2_eth_stop(struct udevice *dev) 480 { 481 struct ks2_eth_priv *priv = dev_get_priv(dev); 482 483 if (!priv->emac_open) 484 return; 485 ethss_stop(); 486 487 ksnav_close(priv->netcp_pktdma); 488 qm_close(); 489 phy_shutdown(priv->phydev); 490 priv->emac_open = false; 491 } 492 493 int ks2_eth_read_rom_hwaddr(struct udevice *dev) 494 { 495 struct ks2_eth_priv *priv = dev_get_priv(dev); 496 struct eth_pdata *pdata = dev_get_platdata(dev); 497 u32 maca = 0; 498 u32 macb = 0; 499 500 /* Read the e-fuse mac address */ 501 if (priv->slave_port == 1) { 502 maca = __raw_readl(MAC_ID_BASE_ADDR); 503 macb = __raw_readl(MAC_ID_BASE_ADDR + 4); 504 } 505 506 pdata->enetaddr[0] = (macb >> 8) & 0xff; 507 pdata->enetaddr[1] = (macb >> 0) & 0xff; 508 pdata->enetaddr[2] = (maca >> 24) & 0xff; 509 pdata->enetaddr[3] = (maca >> 16) & 0xff; 510 pdata->enetaddr[4] = (maca >> 8) & 0xff; 511 pdata->enetaddr[5] = (maca >> 0) & 0xff; 512 513 return 0; 514 } 515 516 int ks2_eth_write_hwaddr(struct udevice *dev) 517 { 518 struct ks2_eth_priv *priv = dev_get_priv(dev); 519 struct eth_pdata *pdata = dev_get_platdata(dev); 520 521 writel(mac_hi(pdata->enetaddr), 522 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) + 523 CPGMACSL_REG_SA_HI); 524 writel(mac_lo(pdata->enetaddr), 525 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) + 526 CPGMACSL_REG_SA_LO); 527 528 return 0; 529 } 530 531 static int ks2_eth_probe(struct udevice *dev) 532 { 533 struct ks2_eth_priv *priv = dev_get_priv(dev); 534 struct mii_dev *mdio_bus; 535 536 priv->dev = dev; 537 priv->emac_open = false; 538 539 /* These clock enables has to be moved to common location */ 540 if (cpu_is_k2g()) 541 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); 542 543 /* By default, select PA PLL clock as PA clock source */ 544 #ifndef CONFIG_SOC_K2G 545 if (psc_enable_module(KS2_LPSC_PA)) 546 return -EACCES; 547 #endif 548 if (psc_enable_module(KS2_LPSC_CPGMAC)) 549 return -EACCES; 550 if (psc_enable_module(KS2_LPSC_CRYPTO)) 551 return -EACCES; 552 553 if (cpu_is_k2e() || cpu_is_k2l()) 554 pll_pa_clk_sel(); 555 556 priv->net_rx_buffs.buff_ptr = rx_buffs; 557 priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS; 558 priv->net_rx_buffs.buff_len = RX_BUFF_LEN; 559 560 if (priv->slave_port == 1) { 561 #ifndef CONFIG_SOC_K2G 562 keystone2_net_serdes_setup(); 563 #endif 564 /* 565 * Register MDIO bus for slave 0 only, other slave have 566 * to re-use the same 567 */ 568 mdio_bus = cpsw_mdio_init("ethernet-mdio", 569 (u32)priv->mdio_base, 570 EMAC_MDIO_CLOCK_FREQ, 571 EMAC_MDIO_BUS_FREQ); 572 if (!mdio_bus) { 573 pr_err("MDIO alloc failed\n"); 574 return -ENOMEM; 575 } 576 priv->mdio_bus = mdio_bus; 577 } else { 578 /* Get the MDIO bus from slave 0 device */ 579 struct ks2_eth_priv *parent_priv; 580 581 parent_priv = dev_get_priv(dev->parent); 582 priv->mdio_bus = parent_priv->mdio_bus; 583 priv->mdio_base = parent_priv->mdio_base; 584 } 585 586 priv->netcp_pktdma = &netcp_pktdma; 587 588 if (priv->has_mdio) { 589 priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr, 590 dev, priv->phy_if); 591 phy_config(priv->phydev); 592 } 593 594 return 0; 595 } 596 597 int ks2_eth_remove(struct udevice *dev) 598 { 599 struct ks2_eth_priv *priv = dev_get_priv(dev); 600 601 cpsw_mdio_free(priv->mdio_bus); 602 603 return 0; 604 } 605 606 static const struct eth_ops ks2_eth_ops = { 607 .start = ks2_eth_start, 608 .send = ks2_eth_send, 609 .recv = ks2_eth_recv, 610 .free_pkt = ks2_eth_free_pkt, 611 .stop = ks2_eth_stop, 612 .read_rom_hwaddr = ks2_eth_read_rom_hwaddr, 613 .write_hwaddr = ks2_eth_write_hwaddr, 614 }; 615 616 static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0) 617 { 618 const void *fdt = gd->fdt_blob; 619 struct udevice *sl_dev; 620 int interfaces; 621 int sec_slave; 622 int slave; 623 int ret; 624 char *slave_name; 625 626 interfaces = fdt_subnode_offset(fdt, gbe, "interfaces"); 627 fdt_for_each_subnode(slave, fdt, interfaces) { 628 int slave_no; 629 630 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT); 631 if (slave_no == -ENOENT) 632 continue; 633 634 if (slave_no == 0) { 635 /* This is the current eth device */ 636 *gbe_0 = slave; 637 } else { 638 /* Slave devices to be registered */ 639 slave_name = malloc(20); 640 snprintf(slave_name, 20, "netcp@slave-%d", slave_no); 641 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", 642 slave_name, offset_to_ofnode(slave), 643 &sl_dev); 644 if (ret) { 645 pr_err("ks2_net - not able to bind slave interfaces\n"); 646 return ret; 647 } 648 } 649 } 650 651 sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports"); 652 fdt_for_each_subnode(slave, fdt, sec_slave) { 653 int slave_no; 654 655 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT); 656 if (slave_no == -ENOENT) 657 continue; 658 659 /* Slave devices to be registered */ 660 slave_name = malloc(20); 661 snprintf(slave_name, 20, "netcp@slave-%d", slave_no); 662 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name, 663 offset_to_ofnode(slave), &sl_dev); 664 if (ret) { 665 pr_err("ks2_net - not able to bind slave interfaces\n"); 666 return ret; 667 } 668 } 669 670 return 0; 671 } 672 673 static int ks2_eth_parse_slave_interface(int netcp, int slave, 674 struct ks2_eth_priv *priv, 675 struct eth_pdata *pdata) 676 { 677 const void *fdt = gd->fdt_blob; 678 int mdio; 679 int phy; 680 int dma_count; 681 u32 dma_channel[8]; 682 683 priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1); 684 priv->net_rx_buffs.rx_flow = priv->slave_port * 8; 685 686 /* U-Boot slave port number starts with 1 instead of 0 */ 687 priv->slave_port += 1; 688 689 dma_count = fdtdec_get_int_array_count(fdt, netcp, 690 "ti,navigator-dmas", 691 dma_channel, 8); 692 693 if (dma_count > (2 * priv->slave_port)) { 694 int dma_idx; 695 696 dma_idx = priv->slave_port * 2 - 1; 697 priv->net_rx_buffs.rx_flow = dma_channel[dma_idx]; 698 } 699 700 priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1); 701 702 phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle"); 703 if (phy >= 0) { 704 priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1); 705 706 mdio = fdt_parent_offset(fdt, phy); 707 if (mdio < 0) { 708 pr_err("mdio dt not found\n"); 709 return -ENODEV; 710 } 711 priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg"); 712 } 713 714 if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) { 715 priv->phy_if = PHY_INTERFACE_MODE_SGMII; 716 pdata->phy_interface = priv->phy_if; 717 priv->sgmii_link_type = SGMII_LINK_MAC_PHY; 718 priv->has_mdio = true; 719 } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) { 720 priv->phy_if = PHY_INTERFACE_MODE_RGMII; 721 pdata->phy_interface = priv->phy_if; 722 priv->has_mdio = true; 723 } 724 725 return 0; 726 } 727 728 static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev) 729 { 730 struct ks2_eth_priv *priv = dev_get_priv(dev); 731 struct eth_pdata *pdata = dev_get_platdata(dev); 732 const void *fdt = gd->fdt_blob; 733 int slave = dev_of_offset(dev); 734 int interfaces; 735 int gbe; 736 int netcp_devices; 737 int netcp; 738 739 interfaces = fdt_parent_offset(fdt, slave); 740 gbe = fdt_parent_offset(fdt, interfaces); 741 netcp_devices = fdt_parent_offset(fdt, gbe); 742 netcp = fdt_parent_offset(fdt, netcp_devices); 743 744 ks2_eth_parse_slave_interface(netcp, slave, priv, pdata); 745 746 pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg"); 747 748 return 0; 749 } 750 751 static int ks2_eth_ofdata_to_platdata(struct udevice *dev) 752 { 753 struct ks2_eth_priv *priv = dev_get_priv(dev); 754 struct eth_pdata *pdata = dev_get_platdata(dev); 755 const void *fdt = gd->fdt_blob; 756 int gbe_0 = -ENODEV; 757 int netcp_devices; 758 int gbe; 759 760 netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev), 761 "netcp-devices"); 762 gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe"); 763 764 ks2_eth_bind_slaves(dev, gbe, &gbe_0); 765 766 ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata); 767 768 pdata->iobase = devfdt_get_addr(dev); 769 770 return 0; 771 } 772 773 static const struct udevice_id ks2_eth_ids[] = { 774 { .compatible = "ti,netcp-1.0" }, 775 { } 776 }; 777 778 U_BOOT_DRIVER(eth_ks2_slave) = { 779 .name = "eth_ks2_sl", 780 .id = UCLASS_ETH, 781 .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata, 782 .probe = ks2_eth_probe, 783 .remove = ks2_eth_remove, 784 .ops = &ks2_eth_ops, 785 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv), 786 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 787 .flags = DM_FLAG_ALLOC_PRIV_DMA, 788 }; 789 790 U_BOOT_DRIVER(eth_ks2) = { 791 .name = "eth_ks2", 792 .id = UCLASS_ETH, 793 .of_match = ks2_eth_ids, 794 .ofdata_to_platdata = ks2_eth_ofdata_to_platdata, 795 .probe = ks2_eth_probe, 796 .remove = ks2_eth_remove, 797 .ops = &ks2_eth_ops, 798 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv), 799 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 800 .flags = DM_FLAG_ALLOC_PRIV_DMA, 801 }; 802