1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * CPSW Ethernet Switch Driver 4 * 5 * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <net.h> 11 #include <miiphy.h> 12 #include <malloc.h> 13 #include <net.h> 14 #include <netdev.h> 15 #include <cpsw.h> 16 #include <linux/errno.h> 17 #include <asm/gpio.h> 18 #include <asm/io.h> 19 #include <phy.h> 20 #include <asm/arch/cpu.h> 21 #include <dm.h> 22 #include <fdt_support.h> 23 24 #include "cpsw_mdio.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define BITMASK(bits) (BIT(bits) - 1) 29 #define NUM_DESCS (PKTBUFSRX * 2) 30 #define PKT_MIN 60 31 #define PKT_MAX (1500 + 14 + 4 + 4) 32 #define CLEAR_BIT 1 33 #define GIGABITEN BIT(7) 34 #define FULLDUPLEXEN BIT(0) 35 #define MIIEN BIT(15) 36 37 /* reg offset */ 38 #define CPSW_HOST_PORT_OFFSET 0x108 39 #define CPSW_SLAVE0_OFFSET 0x208 40 #define CPSW_SLAVE1_OFFSET 0x308 41 #define CPSW_SLAVE_SIZE 0x100 42 #define CPSW_CPDMA_OFFSET 0x800 43 #define CPSW_HW_STATS 0x900 44 #define CPSW_STATERAM_OFFSET 0xa00 45 #define CPSW_CPTS_OFFSET 0xc00 46 #define CPSW_ALE_OFFSET 0xd00 47 #define CPSW_SLIVER0_OFFSET 0xd80 48 #define CPSW_SLIVER1_OFFSET 0xdc0 49 #define CPSW_BD_OFFSET 0x2000 50 #define CPSW_MDIO_DIV 0xff 51 52 #define AM335X_GMII_SEL_OFFSET 0x630 53 54 /* DMA Registers */ 55 #define CPDMA_TXCONTROL 0x004 56 #define CPDMA_RXCONTROL 0x014 57 #define CPDMA_SOFTRESET 0x01c 58 #define CPDMA_RXFREE 0x0e0 59 #define CPDMA_TXHDP_VER1 0x100 60 #define CPDMA_TXHDP_VER2 0x200 61 #define CPDMA_RXHDP_VER1 0x120 62 #define CPDMA_RXHDP_VER2 0x220 63 #define CPDMA_TXCP_VER1 0x140 64 #define CPDMA_TXCP_VER2 0x240 65 #define CPDMA_RXCP_VER1 0x160 66 #define CPDMA_RXCP_VER2 0x260 67 68 /* Descriptor mode bits */ 69 #define CPDMA_DESC_SOP BIT(31) 70 #define CPDMA_DESC_EOP BIT(30) 71 #define CPDMA_DESC_OWNER BIT(29) 72 #define CPDMA_DESC_EOQ BIT(28) 73 74 /* 75 * This timeout definition is a worst-case ultra defensive measure against 76 * unexpected controller lock ups. Ideally, we should never ever hit this 77 * scenario in practice. 78 */ 79 #define CPDMA_TIMEOUT 100 /* msecs */ 80 81 struct cpsw_regs { 82 u32 id_ver; 83 u32 control; 84 u32 soft_reset; 85 u32 stat_port_en; 86 u32 ptype; 87 }; 88 89 struct cpsw_slave_regs { 90 u32 max_blks; 91 u32 blk_cnt; 92 u32 flow_thresh; 93 u32 port_vlan; 94 u32 tx_pri_map; 95 #ifdef CONFIG_AM33XX 96 u32 gap_thresh; 97 #elif defined(CONFIG_TI814X) 98 u32 ts_ctl; 99 u32 ts_seq_ltype; 100 u32 ts_vlan; 101 #endif 102 u32 sa_lo; 103 u32 sa_hi; 104 }; 105 106 struct cpsw_host_regs { 107 u32 max_blks; 108 u32 blk_cnt; 109 u32 flow_thresh; 110 u32 port_vlan; 111 u32 tx_pri_map; 112 u32 cpdma_tx_pri_map; 113 u32 cpdma_rx_chan_map; 114 }; 115 116 struct cpsw_sliver_regs { 117 u32 id_ver; 118 u32 mac_control; 119 u32 mac_status; 120 u32 soft_reset; 121 u32 rx_maxlen; 122 u32 __reserved_0; 123 u32 rx_pause; 124 u32 tx_pause; 125 u32 __reserved_1; 126 u32 rx_pri_map; 127 }; 128 129 #define ALE_ENTRY_BITS 68 130 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32) 131 132 /* ALE Registers */ 133 #define ALE_CONTROL 0x08 134 #define ALE_UNKNOWNVLAN 0x18 135 #define ALE_TABLE_CONTROL 0x20 136 #define ALE_TABLE 0x34 137 #define ALE_PORTCTL 0x40 138 139 #define ALE_TABLE_WRITE BIT(31) 140 141 #define ALE_TYPE_FREE 0 142 #define ALE_TYPE_ADDR 1 143 #define ALE_TYPE_VLAN 2 144 #define ALE_TYPE_VLAN_ADDR 3 145 146 #define ALE_UCAST_PERSISTANT 0 147 #define ALE_UCAST_UNTOUCHED 1 148 #define ALE_UCAST_OUI 2 149 #define ALE_UCAST_TOUCHED 3 150 151 #define ALE_MCAST_FWD 0 152 #define ALE_MCAST_BLOCK_LEARN_FWD 1 153 #define ALE_MCAST_FWD_LEARN 2 154 #define ALE_MCAST_FWD_2 3 155 156 enum cpsw_ale_port_state { 157 ALE_PORT_STATE_DISABLE = 0x00, 158 ALE_PORT_STATE_BLOCK = 0x01, 159 ALE_PORT_STATE_LEARN = 0x02, 160 ALE_PORT_STATE_FORWARD = 0x03, 161 }; 162 163 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */ 164 #define ALE_SECURE 1 165 #define ALE_BLOCKED 2 166 167 struct cpsw_slave { 168 struct cpsw_slave_regs *regs; 169 struct cpsw_sliver_regs *sliver; 170 int slave_num; 171 u32 mac_control; 172 struct cpsw_slave_data *data; 173 }; 174 175 struct cpdma_desc { 176 /* hardware fields */ 177 u32 hw_next; 178 u32 hw_buffer; 179 u32 hw_len; 180 u32 hw_mode; 181 /* software fields */ 182 u32 sw_buffer; 183 u32 sw_len; 184 }; 185 186 struct cpdma_chan { 187 struct cpdma_desc *head, *tail; 188 void *hdp, *cp, *rxfree; 189 }; 190 191 /* AM33xx SoC specific definitions for the CONTROL port */ 192 #define AM33XX_GMII_SEL_MODE_MII 0 193 #define AM33XX_GMII_SEL_MODE_RMII 1 194 #define AM33XX_GMII_SEL_MODE_RGMII 2 195 196 #define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4) 197 #define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5) 198 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6) 199 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7) 200 201 #define GMII_SEL_MODE_MASK 0x3 202 203 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) 204 #define desc_read(desc, fld) __raw_readl(&(desc)->fld) 205 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) 206 207 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld) 208 #define chan_read(chan, fld) __raw_readl((chan)->fld) 209 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) 210 211 #define for_active_slave(slave, priv) \ 212 slave = (priv)->slaves + (priv)->data.active_slave; if (slave) 213 #define for_each_slave(slave, priv) \ 214 for (slave = (priv)->slaves; slave != (priv)->slaves + \ 215 (priv)->data.slaves; slave++) 216 217 struct cpsw_priv { 218 #ifdef CONFIG_DM_ETH 219 struct udevice *dev; 220 #else 221 struct eth_device *dev; 222 #endif 223 struct cpsw_platform_data data; 224 int host_port; 225 226 struct cpsw_regs *regs; 227 void *dma_regs; 228 struct cpsw_host_regs *host_port_regs; 229 void *ale_regs; 230 231 struct cpdma_desc *descs; 232 struct cpdma_desc *desc_free; 233 struct cpdma_chan rx_chan, tx_chan; 234 235 struct cpsw_slave *slaves; 236 struct phy_device *phydev; 237 struct mii_dev *bus; 238 239 u32 phy_mask; 240 }; 241 242 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 243 { 244 int idx; 245 246 idx = start / 32; 247 start -= idx * 32; 248 idx = 2 - idx; /* flip */ 249 return (ale_entry[idx] >> start) & BITMASK(bits); 250 } 251 252 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 253 u32 value) 254 { 255 int idx; 256 257 value &= BITMASK(bits); 258 idx = start / 32; 259 start -= idx * 32; 260 idx = 2 - idx; /* flip */ 261 ale_entry[idx] &= ~(BITMASK(bits) << start); 262 ale_entry[idx] |= (value << start); 263 } 264 265 #define DEFINE_ALE_FIELD(name, start, bits) \ 266 static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 267 { \ 268 return cpsw_ale_get_field(ale_entry, start, bits); \ 269 } \ 270 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 271 { \ 272 cpsw_ale_set_field(ale_entry, start, bits, value); \ 273 } 274 275 DEFINE_ALE_FIELD(entry_type, 60, 2) 276 DEFINE_ALE_FIELD(mcast_state, 62, 2) 277 DEFINE_ALE_FIELD(port_mask, 66, 3) 278 DEFINE_ALE_FIELD(ucast_type, 62, 2) 279 DEFINE_ALE_FIELD(port_num, 66, 2) 280 DEFINE_ALE_FIELD(blocked, 65, 1) 281 DEFINE_ALE_FIELD(secure, 64, 1) 282 DEFINE_ALE_FIELD(mcast, 40, 1) 283 284 /* The MAC address field in the ALE entry cannot be macroized as above */ 285 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 286 { 287 int i; 288 289 for (i = 0; i < 6; i++) 290 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 291 } 292 293 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) 294 { 295 int i; 296 297 for (i = 0; i < 6; i++) 298 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 299 } 300 301 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) 302 { 303 int i; 304 305 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); 306 307 for (i = 0; i < ALE_ENTRY_WORDS; i++) 308 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); 309 310 return idx; 311 } 312 313 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) 314 { 315 int i; 316 317 for (i = 0; i < ALE_ENTRY_WORDS; i++) 318 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); 319 320 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); 321 322 return idx; 323 } 324 325 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr) 326 { 327 u32 ale_entry[ALE_ENTRY_WORDS]; 328 int type, idx; 329 330 for (idx = 0; idx < priv->data.ale_entries; idx++) { 331 u8 entry_addr[6]; 332 333 cpsw_ale_read(priv, idx, ale_entry); 334 type = cpsw_ale_get_entry_type(ale_entry); 335 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 336 continue; 337 cpsw_ale_get_addr(ale_entry, entry_addr); 338 if (memcmp(entry_addr, addr, 6) == 0) 339 return idx; 340 } 341 return -ENOENT; 342 } 343 344 static int cpsw_ale_match_free(struct cpsw_priv *priv) 345 { 346 u32 ale_entry[ALE_ENTRY_WORDS]; 347 int type, idx; 348 349 for (idx = 0; idx < priv->data.ale_entries; idx++) { 350 cpsw_ale_read(priv, idx, ale_entry); 351 type = cpsw_ale_get_entry_type(ale_entry); 352 if (type == ALE_TYPE_FREE) 353 return idx; 354 } 355 return -ENOENT; 356 } 357 358 static int cpsw_ale_find_ageable(struct cpsw_priv *priv) 359 { 360 u32 ale_entry[ALE_ENTRY_WORDS]; 361 int type, idx; 362 363 for (idx = 0; idx < priv->data.ale_entries; idx++) { 364 cpsw_ale_read(priv, idx, ale_entry); 365 type = cpsw_ale_get_entry_type(ale_entry); 366 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 367 continue; 368 if (cpsw_ale_get_mcast(ale_entry)) 369 continue; 370 type = cpsw_ale_get_ucast_type(ale_entry); 371 if (type != ALE_UCAST_PERSISTANT && 372 type != ALE_UCAST_OUI) 373 return idx; 374 } 375 return -ENOENT; 376 } 377 378 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr, 379 int port, int flags) 380 { 381 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 382 int idx; 383 384 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 385 cpsw_ale_set_addr(ale_entry, addr); 386 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 387 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 388 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 389 cpsw_ale_set_port_num(ale_entry, port); 390 391 idx = cpsw_ale_match_addr(priv, addr); 392 if (idx < 0) 393 idx = cpsw_ale_match_free(priv); 394 if (idx < 0) 395 idx = cpsw_ale_find_ageable(priv); 396 if (idx < 0) 397 return -ENOMEM; 398 399 cpsw_ale_write(priv, idx, ale_entry); 400 return 0; 401 } 402 403 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr, 404 int port_mask) 405 { 406 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 407 int idx, mask; 408 409 idx = cpsw_ale_match_addr(priv, addr); 410 if (idx >= 0) 411 cpsw_ale_read(priv, idx, ale_entry); 412 413 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 414 cpsw_ale_set_addr(ale_entry, addr); 415 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2); 416 417 mask = cpsw_ale_get_port_mask(ale_entry); 418 port_mask |= mask; 419 cpsw_ale_set_port_mask(ale_entry, port_mask); 420 421 if (idx < 0) 422 idx = cpsw_ale_match_free(priv); 423 if (idx < 0) 424 idx = cpsw_ale_find_ageable(priv); 425 if (idx < 0) 426 return -ENOMEM; 427 428 cpsw_ale_write(priv, idx, ale_entry); 429 return 0; 430 } 431 432 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val) 433 { 434 u32 tmp, mask = BIT(bit); 435 436 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL); 437 tmp &= ~mask; 438 tmp |= val ? mask : 0; 439 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); 440 } 441 442 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val) 443 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val) 444 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val) 445 446 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, 447 int val) 448 { 449 int offset = ALE_PORTCTL + 4 * port; 450 u32 tmp, mask = 0x3; 451 452 tmp = __raw_readl(priv->ale_regs + offset); 453 tmp &= ~mask; 454 tmp |= val & mask; 455 __raw_writel(tmp, priv->ale_regs + offset); 456 } 457 458 /* Set a self-clearing bit in a register, and wait for it to clear */ 459 static inline void setbit_and_wait_for_clear32(void *addr) 460 { 461 __raw_writel(CLEAR_BIT, addr); 462 while (__raw_readl(addr) & CLEAR_BIT) 463 ; 464 } 465 466 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 467 ((mac)[2] << 16) | ((mac)[3] << 24)) 468 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 469 470 static void cpsw_set_slave_mac(struct cpsw_slave *slave, 471 struct cpsw_priv *priv) 472 { 473 #ifdef CONFIG_DM_ETH 474 struct eth_pdata *pdata = dev_get_platdata(priv->dev); 475 476 writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi); 477 writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo); 478 #else 479 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi); 480 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); 481 #endif 482 } 483 484 static int cpsw_slave_update_link(struct cpsw_slave *slave, 485 struct cpsw_priv *priv, int *link) 486 { 487 struct phy_device *phy; 488 u32 mac_control = 0; 489 int ret = -ENODEV; 490 491 phy = priv->phydev; 492 if (!phy) 493 goto out; 494 495 ret = phy_startup(phy); 496 if (ret) 497 goto out; 498 499 if (link) 500 *link = phy->link; 501 502 if (phy->link) { /* link up */ 503 mac_control = priv->data.mac_control; 504 if (phy->speed == 1000) 505 mac_control |= GIGABITEN; 506 if (phy->duplex == DUPLEX_FULL) 507 mac_control |= FULLDUPLEXEN; 508 if (phy->speed == 100) 509 mac_control |= MIIEN; 510 } 511 512 if (mac_control == slave->mac_control) 513 goto out; 514 515 if (mac_control) { 516 printf("link up on port %d, speed %d, %s duplex\n", 517 slave->slave_num, phy->speed, 518 (phy->duplex == DUPLEX_FULL) ? "full" : "half"); 519 } else { 520 printf("link down on port %d\n", slave->slave_num); 521 } 522 523 __raw_writel(mac_control, &slave->sliver->mac_control); 524 slave->mac_control = mac_control; 525 526 out: 527 return ret; 528 } 529 530 static int cpsw_update_link(struct cpsw_priv *priv) 531 { 532 int ret = -ENODEV; 533 struct cpsw_slave *slave; 534 535 for_active_slave(slave, priv) 536 ret = cpsw_slave_update_link(slave, priv, NULL); 537 538 return ret; 539 } 540 541 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 542 { 543 if (priv->host_port == 0) 544 return slave_num + 1; 545 else 546 return slave_num; 547 } 548 549 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) 550 { 551 u32 slave_port; 552 553 setbit_and_wait_for_clear32(&slave->sliver->soft_reset); 554 555 /* setup priority mapping */ 556 __raw_writel(0x76543210, &slave->sliver->rx_pri_map); 557 __raw_writel(0x33221100, &slave->regs->tx_pri_map); 558 559 /* setup max packet size, and mac address */ 560 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen); 561 cpsw_set_slave_mac(slave, priv); 562 563 slave->mac_control = 0; /* no link yet */ 564 565 /* enable forwarding */ 566 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 567 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); 568 569 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port); 570 571 priv->phy_mask |= 1 << slave->data->phy_addr; 572 } 573 574 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) 575 { 576 struct cpdma_desc *desc = priv->desc_free; 577 578 if (desc) 579 priv->desc_free = desc_read_ptr(desc, hw_next); 580 return desc; 581 } 582 583 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc) 584 { 585 if (desc) { 586 desc_write(desc, hw_next, priv->desc_free); 587 priv->desc_free = desc; 588 } 589 } 590 591 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan, 592 void *buffer, int len) 593 { 594 struct cpdma_desc *desc, *prev; 595 u32 mode; 596 597 desc = cpdma_desc_alloc(priv); 598 if (!desc) 599 return -ENOMEM; 600 601 if (len < PKT_MIN) 602 len = PKT_MIN; 603 604 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; 605 606 desc_write(desc, hw_next, 0); 607 desc_write(desc, hw_buffer, buffer); 608 desc_write(desc, hw_len, len); 609 desc_write(desc, hw_mode, mode | len); 610 desc_write(desc, sw_buffer, buffer); 611 desc_write(desc, sw_len, len); 612 613 if (!chan->head) { 614 /* simple case - first packet enqueued */ 615 chan->head = desc; 616 chan->tail = desc; 617 chan_write(chan, hdp, desc); 618 goto done; 619 } 620 621 /* not the first packet - enqueue at the tail */ 622 prev = chan->tail; 623 desc_write(prev, hw_next, desc); 624 chan->tail = desc; 625 626 /* next check if EOQ has been triggered already */ 627 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ) 628 chan_write(chan, hdp, desc); 629 630 done: 631 if (chan->rxfree) 632 chan_write(chan, rxfree, 1); 633 return 0; 634 } 635 636 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, 637 void **buffer, int *len) 638 { 639 struct cpdma_desc *desc = chan->head; 640 u32 status; 641 642 if (!desc) 643 return -ENOENT; 644 645 status = desc_read(desc, hw_mode); 646 647 if (len) 648 *len = status & 0x7ff; 649 650 if (buffer) 651 *buffer = desc_read_ptr(desc, sw_buffer); 652 653 if (status & CPDMA_DESC_OWNER) { 654 if (chan_read(chan, hdp) == 0) { 655 if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER) 656 chan_write(chan, hdp, desc); 657 } 658 659 return -EBUSY; 660 } 661 662 chan->head = desc_read_ptr(desc, hw_next); 663 chan_write(chan, cp, desc); 664 665 cpdma_desc_free(priv, desc); 666 return 0; 667 } 668 669 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) 670 { 671 struct cpsw_slave *slave; 672 int i, ret; 673 674 /* soft reset the controller and initialize priv */ 675 setbit_and_wait_for_clear32(&priv->regs->soft_reset); 676 677 /* initialize and reset the address lookup engine */ 678 cpsw_ale_enable(priv, 1); 679 cpsw_ale_clear(priv, 1); 680 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */ 681 682 /* setup host port priority mapping */ 683 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); 684 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 685 686 /* disable priority elevation and enable statistics on all ports */ 687 __raw_writel(0, &priv->regs->ptype); 688 689 /* enable statistics collection only on the host port */ 690 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); 691 __raw_writel(0x7, &priv->regs->stat_port_en); 692 693 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); 694 695 cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE); 696 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port); 697 698 for_active_slave(slave, priv) 699 cpsw_slave_init(slave, priv); 700 701 ret = cpsw_update_link(priv); 702 if (ret) 703 goto out; 704 705 /* init descriptor pool */ 706 for (i = 0; i < NUM_DESCS; i++) { 707 desc_write(&priv->descs[i], hw_next, 708 (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]); 709 } 710 priv->desc_free = &priv->descs[0]; 711 712 /* initialize channels */ 713 if (priv->data.version == CPSW_CTRL_VERSION_2) { 714 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 715 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2; 716 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2; 717 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 718 719 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 720 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2; 721 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2; 722 } else { 723 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 724 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1; 725 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1; 726 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 727 728 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 729 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1; 730 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1; 731 } 732 733 /* clear dma state */ 734 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 735 736 if (priv->data.version == CPSW_CTRL_VERSION_2) { 737 for (i = 0; i < priv->data.channels; i++) { 738 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 739 * i); 740 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 741 * i); 742 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 743 * i); 744 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 745 * i); 746 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 747 * i); 748 } 749 } else { 750 for (i = 0; i < priv->data.channels; i++) { 751 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 752 * i); 753 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 754 * i); 755 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 756 * i); 757 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 758 * i); 759 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 760 * i); 761 762 } 763 } 764 765 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL); 766 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL); 767 768 /* submit rx descs */ 769 for (i = 0; i < PKTBUFSRX; i++) { 770 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i], 771 PKTSIZE); 772 if (ret < 0) { 773 printf("error %d submitting rx desc\n", ret); 774 break; 775 } 776 } 777 778 out: 779 return ret; 780 } 781 782 static int cpsw_reap_completed_packets(struct cpsw_priv *priv) 783 { 784 int timeout = CPDMA_TIMEOUT; 785 786 /* reap completed packets */ 787 while (timeout-- && 788 (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0)) 789 ; 790 791 return timeout; 792 } 793 794 static void _cpsw_halt(struct cpsw_priv *priv) 795 { 796 cpsw_reap_completed_packets(priv); 797 798 writel(0, priv->dma_regs + CPDMA_TXCONTROL); 799 writel(0, priv->dma_regs + CPDMA_RXCONTROL); 800 801 /* soft reset the controller and initialize priv */ 802 setbit_and_wait_for_clear32(&priv->regs->soft_reset); 803 804 /* clear dma state */ 805 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 806 807 } 808 809 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) 810 { 811 int timeout; 812 813 flush_dcache_range((unsigned long)packet, 814 (unsigned long)packet + ALIGN(length, PKTALIGN)); 815 816 timeout = cpsw_reap_completed_packets(priv); 817 if (timeout == -1) { 818 printf("cpdma_process timeout\n"); 819 return -ETIMEDOUT; 820 } 821 822 return cpdma_submit(priv, &priv->tx_chan, packet, length); 823 } 824 825 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt) 826 { 827 void *buffer; 828 int len; 829 int ret; 830 831 ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len); 832 if (ret < 0) 833 return ret; 834 835 invalidate_dcache_range((unsigned long)buffer, 836 (unsigned long)buffer + PKTSIZE_ALIGN); 837 *pkt = buffer; 838 839 return len; 840 } 841 842 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, 843 struct cpsw_priv *priv) 844 { 845 void *regs = priv->regs; 846 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 847 slave->slave_num = slave_num; 848 slave->data = data; 849 slave->regs = regs + data->slave_reg_ofs; 850 slave->sliver = regs + data->sliver_reg_ofs; 851 } 852 853 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) 854 { 855 struct phy_device *phydev; 856 u32 supported = PHY_GBIT_FEATURES; 857 858 phydev = phy_connect(priv->bus, 859 slave->data->phy_addr, 860 priv->dev, 861 slave->data->phy_if); 862 863 if (!phydev) 864 return -1; 865 866 phydev->supported &= supported; 867 phydev->advertising = phydev->supported; 868 869 #ifdef CONFIG_DM_ETH 870 if (slave->data->phy_of_handle) 871 phydev->node = offset_to_ofnode(slave->data->phy_of_handle); 872 #endif 873 874 priv->phydev = phydev; 875 phy_config(phydev); 876 877 return 1; 878 } 879 880 static void cpsw_phy_addr_update(struct cpsw_priv *priv) 881 { 882 struct cpsw_platform_data *data = &priv->data; 883 u16 alive = cpsw_mdio_get_alive(priv->bus); 884 int active = data->active_slave; 885 int new_addr = ffs(alive) - 1; 886 887 /* 888 * If there is only one phy alive and its address does not match 889 * that of active slave, then phy address can safely be updated. 890 */ 891 if (hweight16(alive) == 1 && 892 data->slave_data[active].phy_addr != new_addr) { 893 printf("Updated phy address for CPSW#%d, old: %d, new: %d\n", 894 active, data->slave_data[active].phy_addr, new_addr); 895 data->slave_data[active].phy_addr = new_addr; 896 } 897 } 898 899 int _cpsw_register(struct cpsw_priv *priv) 900 { 901 struct cpsw_slave *slave; 902 struct cpsw_platform_data *data = &priv->data; 903 void *regs = (void *)data->cpsw_base; 904 905 priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); 906 if (!priv->slaves) { 907 return -ENOMEM; 908 } 909 910 priv->host_port = data->host_port_num; 911 priv->regs = regs; 912 priv->host_port_regs = regs + data->host_port_reg_ofs; 913 priv->dma_regs = regs + data->cpdma_reg_ofs; 914 priv->ale_regs = regs + data->ale_reg_ofs; 915 priv->descs = (void *)regs + data->bd_ram_ofs; 916 917 int idx = 0; 918 919 for_each_slave(slave, priv) { 920 cpsw_slave_setup(slave, idx, priv); 921 idx = idx + 1; 922 } 923 924 priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0); 925 if (!priv->bus) 926 return -EFAULT; 927 928 cpsw_phy_addr_update(priv); 929 930 for_active_slave(slave, priv) 931 cpsw_phy_init(priv, slave); 932 933 return 0; 934 } 935 936 #ifndef CONFIG_DM_ETH 937 static int cpsw_init(struct eth_device *dev, bd_t *bis) 938 { 939 struct cpsw_priv *priv = dev->priv; 940 941 return _cpsw_init(priv, dev->enetaddr); 942 } 943 944 static void cpsw_halt(struct eth_device *dev) 945 { 946 struct cpsw_priv *priv = dev->priv; 947 948 return _cpsw_halt(priv); 949 } 950 951 static int cpsw_send(struct eth_device *dev, void *packet, int length) 952 { 953 struct cpsw_priv *priv = dev->priv; 954 955 return _cpsw_send(priv, packet, length); 956 } 957 958 static int cpsw_recv(struct eth_device *dev) 959 { 960 struct cpsw_priv *priv = dev->priv; 961 uchar *pkt = NULL; 962 int len; 963 964 len = _cpsw_recv(priv, &pkt); 965 966 if (len > 0) { 967 net_process_received_packet(pkt, len); 968 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE); 969 } 970 971 return len; 972 } 973 974 int cpsw_register(struct cpsw_platform_data *data) 975 { 976 struct cpsw_priv *priv; 977 struct eth_device *dev; 978 int ret; 979 980 dev = calloc(sizeof(*dev), 1); 981 if (!dev) 982 return -ENOMEM; 983 984 priv = calloc(sizeof(*priv), 1); 985 if (!priv) { 986 free(dev); 987 return -ENOMEM; 988 } 989 990 priv->dev = dev; 991 priv->data = *data; 992 993 strcpy(dev->name, "cpsw"); 994 dev->iobase = 0; 995 dev->init = cpsw_init; 996 dev->halt = cpsw_halt; 997 dev->send = cpsw_send; 998 dev->recv = cpsw_recv; 999 dev->priv = priv; 1000 1001 eth_register(dev); 1002 1003 ret = _cpsw_register(priv); 1004 if (ret < 0) { 1005 eth_unregister(dev); 1006 free(dev); 1007 free(priv); 1008 return ret; 1009 } 1010 1011 return 1; 1012 } 1013 #else 1014 static int cpsw_eth_start(struct udevice *dev) 1015 { 1016 struct eth_pdata *pdata = dev_get_platdata(dev); 1017 struct cpsw_priv *priv = dev_get_priv(dev); 1018 1019 return _cpsw_init(priv, pdata->enetaddr); 1020 } 1021 1022 static int cpsw_eth_send(struct udevice *dev, void *packet, int length) 1023 { 1024 struct cpsw_priv *priv = dev_get_priv(dev); 1025 1026 return _cpsw_send(priv, packet, length); 1027 } 1028 1029 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp) 1030 { 1031 struct cpsw_priv *priv = dev_get_priv(dev); 1032 1033 return _cpsw_recv(priv, packetp); 1034 } 1035 1036 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet, 1037 int length) 1038 { 1039 struct cpsw_priv *priv = dev_get_priv(dev); 1040 1041 return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE); 1042 } 1043 1044 static void cpsw_eth_stop(struct udevice *dev) 1045 { 1046 struct cpsw_priv *priv = dev_get_priv(dev); 1047 1048 return _cpsw_halt(priv); 1049 } 1050 1051 1052 static int cpsw_eth_probe(struct udevice *dev) 1053 { 1054 struct cpsw_priv *priv = dev_get_priv(dev); 1055 1056 priv->dev = dev; 1057 1058 return _cpsw_register(priv); 1059 } 1060 1061 static const struct eth_ops cpsw_eth_ops = { 1062 .start = cpsw_eth_start, 1063 .send = cpsw_eth_send, 1064 .recv = cpsw_eth_recv, 1065 .free_pkt = cpsw_eth_free_pkt, 1066 .stop = cpsw_eth_stop, 1067 }; 1068 1069 static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node) 1070 { 1071 return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL, 1072 false); 1073 } 1074 1075 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv, 1076 phy_interface_t phy_mode) 1077 { 1078 u32 reg; 1079 u32 mask; 1080 u32 mode = 0; 1081 bool rgmii_id = false; 1082 int slave = priv->data.active_slave; 1083 1084 reg = readl(priv->data.gmii_sel); 1085 1086 switch (phy_mode) { 1087 case PHY_INTERFACE_MODE_RMII: 1088 mode = AM33XX_GMII_SEL_MODE_RMII; 1089 break; 1090 1091 case PHY_INTERFACE_MODE_RGMII: 1092 mode = AM33XX_GMII_SEL_MODE_RGMII; 1093 break; 1094 case PHY_INTERFACE_MODE_RGMII_ID: 1095 case PHY_INTERFACE_MODE_RGMII_RXID: 1096 case PHY_INTERFACE_MODE_RGMII_TXID: 1097 mode = AM33XX_GMII_SEL_MODE_RGMII; 1098 rgmii_id = true; 1099 break; 1100 1101 case PHY_INTERFACE_MODE_MII: 1102 default: 1103 mode = AM33XX_GMII_SEL_MODE_MII; 1104 break; 1105 }; 1106 1107 mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6); 1108 mode <<= slave * 2; 1109 1110 if (priv->data.rmii_clock_external) { 1111 if (slave == 0) 1112 mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN; 1113 else 1114 mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN; 1115 } 1116 1117 if (rgmii_id) { 1118 if (slave == 0) 1119 mode |= AM33XX_GMII_SEL_RGMII1_IDMODE; 1120 else 1121 mode |= AM33XX_GMII_SEL_RGMII2_IDMODE; 1122 } 1123 1124 reg &= ~mask; 1125 reg |= mode; 1126 1127 writel(reg, priv->data.gmii_sel); 1128 } 1129 1130 static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv, 1131 phy_interface_t phy_mode) 1132 { 1133 u32 reg; 1134 u32 mask; 1135 u32 mode = 0; 1136 int slave = priv->data.active_slave; 1137 1138 reg = readl(priv->data.gmii_sel); 1139 1140 switch (phy_mode) { 1141 case PHY_INTERFACE_MODE_RMII: 1142 mode = AM33XX_GMII_SEL_MODE_RMII; 1143 break; 1144 1145 case PHY_INTERFACE_MODE_RGMII: 1146 case PHY_INTERFACE_MODE_RGMII_ID: 1147 case PHY_INTERFACE_MODE_RGMII_RXID: 1148 case PHY_INTERFACE_MODE_RGMII_TXID: 1149 mode = AM33XX_GMII_SEL_MODE_RGMII; 1150 break; 1151 1152 case PHY_INTERFACE_MODE_MII: 1153 default: 1154 mode = AM33XX_GMII_SEL_MODE_MII; 1155 break; 1156 }; 1157 1158 switch (slave) { 1159 case 0: 1160 mask = GMII_SEL_MODE_MASK; 1161 break; 1162 case 1: 1163 mask = GMII_SEL_MODE_MASK << 4; 1164 mode <<= 4; 1165 break; 1166 default: 1167 dev_err(priv->dev, "invalid slave number...\n"); 1168 return; 1169 } 1170 1171 if (priv->data.rmii_clock_external) 1172 dev_err(priv->dev, "RMII External clock is not supported\n"); 1173 1174 reg &= ~mask; 1175 reg |= mode; 1176 1177 writel(reg, priv->data.gmii_sel); 1178 } 1179 1180 static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat, 1181 phy_interface_t phy_mode) 1182 { 1183 if (!strcmp(compat, "ti,am3352-cpsw-phy-sel")) 1184 cpsw_gmii_sel_am3352(priv, phy_mode); 1185 if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel")) 1186 cpsw_gmii_sel_am3352(priv, phy_mode); 1187 else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel")) 1188 cpsw_gmii_sel_dra7xx(priv, phy_mode); 1189 } 1190 1191 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) 1192 { 1193 struct eth_pdata *pdata = dev_get_platdata(dev); 1194 struct cpsw_priv *priv = dev_get_priv(dev); 1195 struct gpio_desc *mode_gpios; 1196 const char *phy_mode; 1197 const char *phy_sel_compat = NULL; 1198 const void *fdt = gd->fdt_blob; 1199 int node = dev_of_offset(dev); 1200 int subnode; 1201 int slave_index = 0; 1202 int active_slave; 1203 int num_mode_gpios; 1204 int ret; 1205 1206 pdata->iobase = devfdt_get_addr(dev); 1207 priv->data.version = CPSW_CTRL_VERSION_2; 1208 priv->data.bd_ram_ofs = CPSW_BD_OFFSET; 1209 priv->data.ale_reg_ofs = CPSW_ALE_OFFSET; 1210 priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET; 1211 priv->data.mdio_div = CPSW_MDIO_DIV; 1212 priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET, 1213 1214 pdata->phy_interface = -1; 1215 1216 priv->data.cpsw_base = pdata->iobase; 1217 priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1); 1218 if (priv->data.channels <= 0) { 1219 printf("error: cpdma_channels not found in dt\n"); 1220 return -ENOENT; 1221 } 1222 1223 priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1); 1224 if (priv->data.slaves <= 0) { 1225 printf("error: slaves not found in dt\n"); 1226 return -ENOENT; 1227 } 1228 priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) * 1229 priv->data.slaves); 1230 1231 priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1); 1232 if (priv->data.ale_entries <= 0) { 1233 printf("error: ale_entries not found in dt\n"); 1234 return -ENOENT; 1235 } 1236 1237 priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1); 1238 if (priv->data.bd_ram_ofs <= 0) { 1239 printf("error: bd_ram_size not found in dt\n"); 1240 return -ENOENT; 1241 } 1242 1243 priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1); 1244 if (priv->data.mac_control <= 0) { 1245 printf("error: ale_entries not found in dt\n"); 1246 return -ENOENT; 1247 } 1248 1249 num_mode_gpios = gpio_get_list_count(dev, "mode-gpios"); 1250 if (num_mode_gpios > 0) { 1251 mode_gpios = malloc(sizeof(struct gpio_desc) * 1252 num_mode_gpios); 1253 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios, 1254 num_mode_gpios, GPIOD_IS_OUT); 1255 free(mode_gpios); 1256 } 1257 1258 active_slave = fdtdec_get_int(fdt, node, "active_slave", 0); 1259 priv->data.active_slave = active_slave; 1260 1261 fdt_for_each_subnode(subnode, fdt, node) { 1262 int len; 1263 const char *name; 1264 1265 name = fdt_get_name(fdt, subnode, &len); 1266 if (!strncmp(name, "mdio", 4)) { 1267 u32 mdio_base; 1268 1269 mdio_base = cpsw_get_addr_by_node(fdt, subnode); 1270 if (mdio_base == FDT_ADDR_T_NONE) { 1271 pr_err("Not able to get MDIO address space\n"); 1272 return -ENOENT; 1273 } 1274 priv->data.mdio_base = mdio_base; 1275 } 1276 1277 if (!strncmp(name, "slave", 5)) { 1278 u32 phy_id[2]; 1279 1280 if (slave_index >= priv->data.slaves) 1281 continue; 1282 phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL); 1283 if (phy_mode) 1284 priv->data.slave_data[slave_index].phy_if = 1285 phy_get_interface_by_name(phy_mode); 1286 1287 priv->data.slave_data[slave_index].phy_of_handle = 1288 fdtdec_lookup_phandle(fdt, subnode, 1289 "phy-handle"); 1290 1291 if (priv->data.slave_data[slave_index].phy_of_handle >= 0) { 1292 priv->data.slave_data[slave_index].phy_addr = 1293 fdtdec_get_int(gd->fdt_blob, 1294 priv->data.slave_data[slave_index].phy_of_handle, 1295 "reg", -1); 1296 } else { 1297 fdtdec_get_int_array(fdt, subnode, "phy_id", 1298 phy_id, 2); 1299 priv->data.slave_data[slave_index].phy_addr = 1300 phy_id[1]; 1301 } 1302 slave_index++; 1303 } 1304 1305 if (!strncmp(name, "cpsw-phy-sel", 12)) { 1306 priv->data.gmii_sel = cpsw_get_addr_by_node(fdt, 1307 subnode); 1308 1309 if (priv->data.gmii_sel == FDT_ADDR_T_NONE) { 1310 pr_err("Not able to get gmii_sel reg address\n"); 1311 return -ENOENT; 1312 } 1313 1314 if (fdt_get_property(fdt, subnode, "rmii-clock-ext", 1315 NULL)) 1316 priv->data.rmii_clock_external = true; 1317 1318 phy_sel_compat = fdt_getprop(fdt, subnode, "compatible", 1319 NULL); 1320 if (!phy_sel_compat) { 1321 pr_err("Not able to get gmii_sel compatible\n"); 1322 return -ENOENT; 1323 } 1324 } 1325 } 1326 1327 priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET; 1328 priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET; 1329 1330 if (priv->data.slaves == 2) { 1331 priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET; 1332 priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET; 1333 } 1334 1335 ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr); 1336 if (ret < 0) { 1337 pr_err("cpsw read efuse mac failed\n"); 1338 return ret; 1339 } 1340 1341 pdata->phy_interface = priv->data.slave_data[active_slave].phy_if; 1342 if (pdata->phy_interface == -1) { 1343 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1344 return -EINVAL; 1345 } 1346 1347 /* Select phy interface in control module */ 1348 cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface); 1349 1350 return 0; 1351 } 1352 1353 int cpsw_get_slave_phy_addr(struct udevice *dev, int slave) 1354 { 1355 struct cpsw_priv *priv = dev_get_priv(dev); 1356 struct cpsw_platform_data *data = &priv->data; 1357 1358 return data->slave_data[slave].phy_addr; 1359 } 1360 1361 static const struct udevice_id cpsw_eth_ids[] = { 1362 { .compatible = "ti,cpsw" }, 1363 { .compatible = "ti,am335x-cpsw" }, 1364 { } 1365 }; 1366 1367 U_BOOT_DRIVER(eth_cpsw) = { 1368 .name = "eth_cpsw", 1369 .id = UCLASS_ETH, 1370 .of_match = cpsw_eth_ids, 1371 .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata, 1372 .probe = cpsw_eth_probe, 1373 .ops = &cpsw_eth_ops, 1374 .priv_auto_alloc_size = sizeof(struct cpsw_priv), 1375 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1376 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1377 }; 1378 #endif /* CONFIG_DM_ETH */ 1379