1*cbec53b4SGrygorii Strashko // SPDX-License-Identifier: GPL-2.0+ 2ffad5fa0SGrygorii Strashko /* 3ffad5fa0SGrygorii Strashko * CPSW Ethernet Switch Driver 4ffad5fa0SGrygorii Strashko * 5*cbec53b4SGrygorii Strashko * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/ 6ffad5fa0SGrygorii Strashko */ 7ffad5fa0SGrygorii Strashko 8ffad5fa0SGrygorii Strashko #include <common.h> 9ffad5fa0SGrygorii Strashko #include <command.h> 10ffad5fa0SGrygorii Strashko #include <net.h> 11ffad5fa0SGrygorii Strashko #include <miiphy.h> 12ffad5fa0SGrygorii Strashko #include <malloc.h> 13ffad5fa0SGrygorii Strashko #include <net.h> 14ffad5fa0SGrygorii Strashko #include <netdev.h> 15ffad5fa0SGrygorii Strashko #include <cpsw.h> 16ffad5fa0SGrygorii Strashko #include <linux/errno.h> 17ffad5fa0SGrygorii Strashko #include <asm/gpio.h> 18ffad5fa0SGrygorii Strashko #include <asm/io.h> 19ffad5fa0SGrygorii Strashko #include <phy.h> 20ffad5fa0SGrygorii Strashko #include <asm/arch/cpu.h> 21ffad5fa0SGrygorii Strashko #include <dm.h> 22ffad5fa0SGrygorii Strashko #include <fdt_support.h> 23ffad5fa0SGrygorii Strashko 24ffad5fa0SGrygorii Strashko DECLARE_GLOBAL_DATA_PTR; 25ffad5fa0SGrygorii Strashko 26ffad5fa0SGrygorii Strashko #define BITMASK(bits) (BIT(bits) - 1) 27ffad5fa0SGrygorii Strashko #define PHY_REG_MASK 0x1f 28ffad5fa0SGrygorii Strashko #define PHY_ID_MASK 0x1f 29ffad5fa0SGrygorii Strashko #define NUM_DESCS (PKTBUFSRX * 2) 30ffad5fa0SGrygorii Strashko #define PKT_MIN 60 31ffad5fa0SGrygorii Strashko #define PKT_MAX (1500 + 14 + 4 + 4) 32ffad5fa0SGrygorii Strashko #define CLEAR_BIT 1 33ffad5fa0SGrygorii Strashko #define GIGABITEN BIT(7) 34ffad5fa0SGrygorii Strashko #define FULLDUPLEXEN BIT(0) 35ffad5fa0SGrygorii Strashko #define MIIEN BIT(15) 36ffad5fa0SGrygorii Strashko 37ffad5fa0SGrygorii Strashko /* reg offset */ 38ffad5fa0SGrygorii Strashko #define CPSW_HOST_PORT_OFFSET 0x108 39ffad5fa0SGrygorii Strashko #define CPSW_SLAVE0_OFFSET 0x208 40ffad5fa0SGrygorii Strashko #define CPSW_SLAVE1_OFFSET 0x308 41ffad5fa0SGrygorii Strashko #define CPSW_SLAVE_SIZE 0x100 42ffad5fa0SGrygorii Strashko #define CPSW_CPDMA_OFFSET 0x800 43ffad5fa0SGrygorii Strashko #define CPSW_HW_STATS 0x900 44ffad5fa0SGrygorii Strashko #define CPSW_STATERAM_OFFSET 0xa00 45ffad5fa0SGrygorii Strashko #define CPSW_CPTS_OFFSET 0xc00 46ffad5fa0SGrygorii Strashko #define CPSW_ALE_OFFSET 0xd00 47ffad5fa0SGrygorii Strashko #define CPSW_SLIVER0_OFFSET 0xd80 48ffad5fa0SGrygorii Strashko #define CPSW_SLIVER1_OFFSET 0xdc0 49ffad5fa0SGrygorii Strashko #define CPSW_BD_OFFSET 0x2000 50ffad5fa0SGrygorii Strashko #define CPSW_MDIO_DIV 0xff 51ffad5fa0SGrygorii Strashko 52ffad5fa0SGrygorii Strashko #define AM335X_GMII_SEL_OFFSET 0x630 53ffad5fa0SGrygorii Strashko 54ffad5fa0SGrygorii Strashko /* DMA Registers */ 55ffad5fa0SGrygorii Strashko #define CPDMA_TXCONTROL 0x004 56ffad5fa0SGrygorii Strashko #define CPDMA_RXCONTROL 0x014 57ffad5fa0SGrygorii Strashko #define CPDMA_SOFTRESET 0x01c 58ffad5fa0SGrygorii Strashko #define CPDMA_RXFREE 0x0e0 59ffad5fa0SGrygorii Strashko #define CPDMA_TXHDP_VER1 0x100 60ffad5fa0SGrygorii Strashko #define CPDMA_TXHDP_VER2 0x200 61ffad5fa0SGrygorii Strashko #define CPDMA_RXHDP_VER1 0x120 62ffad5fa0SGrygorii Strashko #define CPDMA_RXHDP_VER2 0x220 63ffad5fa0SGrygorii Strashko #define CPDMA_TXCP_VER1 0x140 64ffad5fa0SGrygorii Strashko #define CPDMA_TXCP_VER2 0x240 65ffad5fa0SGrygorii Strashko #define CPDMA_RXCP_VER1 0x160 66ffad5fa0SGrygorii Strashko #define CPDMA_RXCP_VER2 0x260 67ffad5fa0SGrygorii Strashko 68ffad5fa0SGrygorii Strashko /* Descriptor mode bits */ 69ffad5fa0SGrygorii Strashko #define CPDMA_DESC_SOP BIT(31) 70ffad5fa0SGrygorii Strashko #define CPDMA_DESC_EOP BIT(30) 71ffad5fa0SGrygorii Strashko #define CPDMA_DESC_OWNER BIT(29) 72ffad5fa0SGrygorii Strashko #define CPDMA_DESC_EOQ BIT(28) 73ffad5fa0SGrygorii Strashko 74ffad5fa0SGrygorii Strashko /* 75ffad5fa0SGrygorii Strashko * This timeout definition is a worst-case ultra defensive measure against 76ffad5fa0SGrygorii Strashko * unexpected controller lock ups. Ideally, we should never ever hit this 77ffad5fa0SGrygorii Strashko * scenario in practice. 78ffad5fa0SGrygorii Strashko */ 79ffad5fa0SGrygorii Strashko #define MDIO_TIMEOUT 100 /* msecs */ 80ffad5fa0SGrygorii Strashko #define CPDMA_TIMEOUT 100 /* msecs */ 81ffad5fa0SGrygorii Strashko 82ffad5fa0SGrygorii Strashko struct cpsw_mdio_regs { 83ffad5fa0SGrygorii Strashko u32 version; 84ffad5fa0SGrygorii Strashko u32 control; 85ffad5fa0SGrygorii Strashko #define CONTROL_IDLE BIT(31) 86ffad5fa0SGrygorii Strashko #define CONTROL_ENABLE BIT(30) 87ffad5fa0SGrygorii Strashko 88ffad5fa0SGrygorii Strashko u32 alive; 89ffad5fa0SGrygorii Strashko u32 link; 90ffad5fa0SGrygorii Strashko u32 linkintraw; 91ffad5fa0SGrygorii Strashko u32 linkintmasked; 92ffad5fa0SGrygorii Strashko u32 __reserved_0[2]; 93ffad5fa0SGrygorii Strashko u32 userintraw; 94ffad5fa0SGrygorii Strashko u32 userintmasked; 95ffad5fa0SGrygorii Strashko u32 userintmaskset; 96ffad5fa0SGrygorii Strashko u32 userintmaskclr; 97ffad5fa0SGrygorii Strashko u32 __reserved_1[20]; 98ffad5fa0SGrygorii Strashko 99ffad5fa0SGrygorii Strashko struct { 100ffad5fa0SGrygorii Strashko u32 access; 101ffad5fa0SGrygorii Strashko u32 physel; 102ffad5fa0SGrygorii Strashko #define USERACCESS_GO BIT(31) 103ffad5fa0SGrygorii Strashko #define USERACCESS_WRITE BIT(30) 104ffad5fa0SGrygorii Strashko #define USERACCESS_ACK BIT(29) 105ffad5fa0SGrygorii Strashko #define USERACCESS_READ (0) 106ffad5fa0SGrygorii Strashko #define USERACCESS_DATA (0xffff) 107ffad5fa0SGrygorii Strashko } user[0]; 108ffad5fa0SGrygorii Strashko }; 109ffad5fa0SGrygorii Strashko 110ffad5fa0SGrygorii Strashko struct cpsw_regs { 111ffad5fa0SGrygorii Strashko u32 id_ver; 112ffad5fa0SGrygorii Strashko u32 control; 113ffad5fa0SGrygorii Strashko u32 soft_reset; 114ffad5fa0SGrygorii Strashko u32 stat_port_en; 115ffad5fa0SGrygorii Strashko u32 ptype; 116ffad5fa0SGrygorii Strashko }; 117ffad5fa0SGrygorii Strashko 118ffad5fa0SGrygorii Strashko struct cpsw_slave_regs { 119ffad5fa0SGrygorii Strashko u32 max_blks; 120ffad5fa0SGrygorii Strashko u32 blk_cnt; 121ffad5fa0SGrygorii Strashko u32 flow_thresh; 122ffad5fa0SGrygorii Strashko u32 port_vlan; 123ffad5fa0SGrygorii Strashko u32 tx_pri_map; 124ffad5fa0SGrygorii Strashko #ifdef CONFIG_AM33XX 125ffad5fa0SGrygorii Strashko u32 gap_thresh; 126ffad5fa0SGrygorii Strashko #elif defined(CONFIG_TI814X) 127ffad5fa0SGrygorii Strashko u32 ts_ctl; 128ffad5fa0SGrygorii Strashko u32 ts_seq_ltype; 129ffad5fa0SGrygorii Strashko u32 ts_vlan; 130ffad5fa0SGrygorii Strashko #endif 131ffad5fa0SGrygorii Strashko u32 sa_lo; 132ffad5fa0SGrygorii Strashko u32 sa_hi; 133ffad5fa0SGrygorii Strashko }; 134ffad5fa0SGrygorii Strashko 135ffad5fa0SGrygorii Strashko struct cpsw_host_regs { 136ffad5fa0SGrygorii Strashko u32 max_blks; 137ffad5fa0SGrygorii Strashko u32 blk_cnt; 138ffad5fa0SGrygorii Strashko u32 flow_thresh; 139ffad5fa0SGrygorii Strashko u32 port_vlan; 140ffad5fa0SGrygorii Strashko u32 tx_pri_map; 141ffad5fa0SGrygorii Strashko u32 cpdma_tx_pri_map; 142ffad5fa0SGrygorii Strashko u32 cpdma_rx_chan_map; 143ffad5fa0SGrygorii Strashko }; 144ffad5fa0SGrygorii Strashko 145ffad5fa0SGrygorii Strashko struct cpsw_sliver_regs { 146ffad5fa0SGrygorii Strashko u32 id_ver; 147ffad5fa0SGrygorii Strashko u32 mac_control; 148ffad5fa0SGrygorii Strashko u32 mac_status; 149ffad5fa0SGrygorii Strashko u32 soft_reset; 150ffad5fa0SGrygorii Strashko u32 rx_maxlen; 151ffad5fa0SGrygorii Strashko u32 __reserved_0; 152ffad5fa0SGrygorii Strashko u32 rx_pause; 153ffad5fa0SGrygorii Strashko u32 tx_pause; 154ffad5fa0SGrygorii Strashko u32 __reserved_1; 155ffad5fa0SGrygorii Strashko u32 rx_pri_map; 156ffad5fa0SGrygorii Strashko }; 157ffad5fa0SGrygorii Strashko 158ffad5fa0SGrygorii Strashko #define ALE_ENTRY_BITS 68 159ffad5fa0SGrygorii Strashko #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32) 160ffad5fa0SGrygorii Strashko 161ffad5fa0SGrygorii Strashko /* ALE Registers */ 162ffad5fa0SGrygorii Strashko #define ALE_CONTROL 0x08 163ffad5fa0SGrygorii Strashko #define ALE_UNKNOWNVLAN 0x18 164ffad5fa0SGrygorii Strashko #define ALE_TABLE_CONTROL 0x20 165ffad5fa0SGrygorii Strashko #define ALE_TABLE 0x34 166ffad5fa0SGrygorii Strashko #define ALE_PORTCTL 0x40 167ffad5fa0SGrygorii Strashko 168ffad5fa0SGrygorii Strashko #define ALE_TABLE_WRITE BIT(31) 169ffad5fa0SGrygorii Strashko 170ffad5fa0SGrygorii Strashko #define ALE_TYPE_FREE 0 171ffad5fa0SGrygorii Strashko #define ALE_TYPE_ADDR 1 172ffad5fa0SGrygorii Strashko #define ALE_TYPE_VLAN 2 173ffad5fa0SGrygorii Strashko #define ALE_TYPE_VLAN_ADDR 3 174ffad5fa0SGrygorii Strashko 175ffad5fa0SGrygorii Strashko #define ALE_UCAST_PERSISTANT 0 176ffad5fa0SGrygorii Strashko #define ALE_UCAST_UNTOUCHED 1 177ffad5fa0SGrygorii Strashko #define ALE_UCAST_OUI 2 178ffad5fa0SGrygorii Strashko #define ALE_UCAST_TOUCHED 3 179ffad5fa0SGrygorii Strashko 180ffad5fa0SGrygorii Strashko #define ALE_MCAST_FWD 0 181ffad5fa0SGrygorii Strashko #define ALE_MCAST_BLOCK_LEARN_FWD 1 182ffad5fa0SGrygorii Strashko #define ALE_MCAST_FWD_LEARN 2 183ffad5fa0SGrygorii Strashko #define ALE_MCAST_FWD_2 3 184ffad5fa0SGrygorii Strashko 185ffad5fa0SGrygorii Strashko enum cpsw_ale_port_state { 186ffad5fa0SGrygorii Strashko ALE_PORT_STATE_DISABLE = 0x00, 187ffad5fa0SGrygorii Strashko ALE_PORT_STATE_BLOCK = 0x01, 188ffad5fa0SGrygorii Strashko ALE_PORT_STATE_LEARN = 0x02, 189ffad5fa0SGrygorii Strashko ALE_PORT_STATE_FORWARD = 0x03, 190ffad5fa0SGrygorii Strashko }; 191ffad5fa0SGrygorii Strashko 192ffad5fa0SGrygorii Strashko /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */ 193ffad5fa0SGrygorii Strashko #define ALE_SECURE 1 194ffad5fa0SGrygorii Strashko #define ALE_BLOCKED 2 195ffad5fa0SGrygorii Strashko 196ffad5fa0SGrygorii Strashko struct cpsw_slave { 197ffad5fa0SGrygorii Strashko struct cpsw_slave_regs *regs; 198ffad5fa0SGrygorii Strashko struct cpsw_sliver_regs *sliver; 199ffad5fa0SGrygorii Strashko int slave_num; 200ffad5fa0SGrygorii Strashko u32 mac_control; 201ffad5fa0SGrygorii Strashko struct cpsw_slave_data *data; 202ffad5fa0SGrygorii Strashko }; 203ffad5fa0SGrygorii Strashko 204ffad5fa0SGrygorii Strashko struct cpdma_desc { 205ffad5fa0SGrygorii Strashko /* hardware fields */ 206ffad5fa0SGrygorii Strashko u32 hw_next; 207ffad5fa0SGrygorii Strashko u32 hw_buffer; 208ffad5fa0SGrygorii Strashko u32 hw_len; 209ffad5fa0SGrygorii Strashko u32 hw_mode; 210ffad5fa0SGrygorii Strashko /* software fields */ 211ffad5fa0SGrygorii Strashko u32 sw_buffer; 212ffad5fa0SGrygorii Strashko u32 sw_len; 213ffad5fa0SGrygorii Strashko }; 214ffad5fa0SGrygorii Strashko 215ffad5fa0SGrygorii Strashko struct cpdma_chan { 216ffad5fa0SGrygorii Strashko struct cpdma_desc *head, *tail; 217ffad5fa0SGrygorii Strashko void *hdp, *cp, *rxfree; 218ffad5fa0SGrygorii Strashko }; 219ffad5fa0SGrygorii Strashko 220ffad5fa0SGrygorii Strashko /* AM33xx SoC specific definitions for the CONTROL port */ 221ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_MODE_MII 0 222ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_MODE_RMII 1 223ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_MODE_RGMII 2 224ffad5fa0SGrygorii Strashko 225ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4) 226ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5) 227ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6) 228ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7) 229ffad5fa0SGrygorii Strashko 230ffad5fa0SGrygorii Strashko #define GMII_SEL_MODE_MASK 0x3 231ffad5fa0SGrygorii Strashko 232ffad5fa0SGrygorii Strashko #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) 233ffad5fa0SGrygorii Strashko #define desc_read(desc, fld) __raw_readl(&(desc)->fld) 234ffad5fa0SGrygorii Strashko #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) 235ffad5fa0SGrygorii Strashko 236ffad5fa0SGrygorii Strashko #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld) 237ffad5fa0SGrygorii Strashko #define chan_read(chan, fld) __raw_readl((chan)->fld) 238ffad5fa0SGrygorii Strashko #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) 239ffad5fa0SGrygorii Strashko 240ffad5fa0SGrygorii Strashko #define for_active_slave(slave, priv) \ 241ffad5fa0SGrygorii Strashko slave = (priv)->slaves + (priv)->data.active_slave; if (slave) 242ffad5fa0SGrygorii Strashko #define for_each_slave(slave, priv) \ 243ffad5fa0SGrygorii Strashko for (slave = (priv)->slaves; slave != (priv)->slaves + \ 244ffad5fa0SGrygorii Strashko (priv)->data.slaves; slave++) 245ffad5fa0SGrygorii Strashko 246ffad5fa0SGrygorii Strashko struct cpsw_priv { 247ffad5fa0SGrygorii Strashko #ifdef CONFIG_DM_ETH 248ffad5fa0SGrygorii Strashko struct udevice *dev; 249ffad5fa0SGrygorii Strashko #else 250ffad5fa0SGrygorii Strashko struct eth_device *dev; 251ffad5fa0SGrygorii Strashko #endif 252ffad5fa0SGrygorii Strashko struct cpsw_platform_data data; 253ffad5fa0SGrygorii Strashko int host_port; 254ffad5fa0SGrygorii Strashko 255ffad5fa0SGrygorii Strashko struct cpsw_regs *regs; 256ffad5fa0SGrygorii Strashko void *dma_regs; 257ffad5fa0SGrygorii Strashko struct cpsw_host_regs *host_port_regs; 258ffad5fa0SGrygorii Strashko void *ale_regs; 259ffad5fa0SGrygorii Strashko 260ffad5fa0SGrygorii Strashko struct cpdma_desc *descs; 261ffad5fa0SGrygorii Strashko struct cpdma_desc *desc_free; 262ffad5fa0SGrygorii Strashko struct cpdma_chan rx_chan, tx_chan; 263ffad5fa0SGrygorii Strashko 264ffad5fa0SGrygorii Strashko struct cpsw_slave *slaves; 265ffad5fa0SGrygorii Strashko struct phy_device *phydev; 266ffad5fa0SGrygorii Strashko struct mii_dev *bus; 267ffad5fa0SGrygorii Strashko 268ffad5fa0SGrygorii Strashko u32 phy_mask; 269ffad5fa0SGrygorii Strashko }; 270ffad5fa0SGrygorii Strashko 271ffad5fa0SGrygorii Strashko static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 272ffad5fa0SGrygorii Strashko { 273ffad5fa0SGrygorii Strashko int idx; 274ffad5fa0SGrygorii Strashko 275ffad5fa0SGrygorii Strashko idx = start / 32; 276ffad5fa0SGrygorii Strashko start -= idx * 32; 277ffad5fa0SGrygorii Strashko idx = 2 - idx; /* flip */ 278ffad5fa0SGrygorii Strashko return (ale_entry[idx] >> start) & BITMASK(bits); 279ffad5fa0SGrygorii Strashko } 280ffad5fa0SGrygorii Strashko 281ffad5fa0SGrygorii Strashko static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 282ffad5fa0SGrygorii Strashko u32 value) 283ffad5fa0SGrygorii Strashko { 284ffad5fa0SGrygorii Strashko int idx; 285ffad5fa0SGrygorii Strashko 286ffad5fa0SGrygorii Strashko value &= BITMASK(bits); 287ffad5fa0SGrygorii Strashko idx = start / 32; 288ffad5fa0SGrygorii Strashko start -= idx * 32; 289ffad5fa0SGrygorii Strashko idx = 2 - idx; /* flip */ 290ffad5fa0SGrygorii Strashko ale_entry[idx] &= ~(BITMASK(bits) << start); 291ffad5fa0SGrygorii Strashko ale_entry[idx] |= (value << start); 292ffad5fa0SGrygorii Strashko } 293ffad5fa0SGrygorii Strashko 294ffad5fa0SGrygorii Strashko #define DEFINE_ALE_FIELD(name, start, bits) \ 295ffad5fa0SGrygorii Strashko static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 296ffad5fa0SGrygorii Strashko { \ 297ffad5fa0SGrygorii Strashko return cpsw_ale_get_field(ale_entry, start, bits); \ 298ffad5fa0SGrygorii Strashko } \ 299ffad5fa0SGrygorii Strashko static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 300ffad5fa0SGrygorii Strashko { \ 301ffad5fa0SGrygorii Strashko cpsw_ale_set_field(ale_entry, start, bits, value); \ 302ffad5fa0SGrygorii Strashko } 303ffad5fa0SGrygorii Strashko 304ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(entry_type, 60, 2) 305ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(mcast_state, 62, 2) 306ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(port_mask, 66, 3) 307ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(ucast_type, 62, 2) 308ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(port_num, 66, 2) 309ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(blocked, 65, 1) 310ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(secure, 64, 1) 311ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(mcast, 40, 1) 312ffad5fa0SGrygorii Strashko 313ffad5fa0SGrygorii Strashko /* The MAC address field in the ALE entry cannot be macroized as above */ 314ffad5fa0SGrygorii Strashko static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 315ffad5fa0SGrygorii Strashko { 316ffad5fa0SGrygorii Strashko int i; 317ffad5fa0SGrygorii Strashko 318ffad5fa0SGrygorii Strashko for (i = 0; i < 6; i++) 319ffad5fa0SGrygorii Strashko addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 320ffad5fa0SGrygorii Strashko } 321ffad5fa0SGrygorii Strashko 322ffad5fa0SGrygorii Strashko static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) 323ffad5fa0SGrygorii Strashko { 324ffad5fa0SGrygorii Strashko int i; 325ffad5fa0SGrygorii Strashko 326ffad5fa0SGrygorii Strashko for (i = 0; i < 6; i++) 327ffad5fa0SGrygorii Strashko cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 328ffad5fa0SGrygorii Strashko } 329ffad5fa0SGrygorii Strashko 330ffad5fa0SGrygorii Strashko static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) 331ffad5fa0SGrygorii Strashko { 332ffad5fa0SGrygorii Strashko int i; 333ffad5fa0SGrygorii Strashko 334ffad5fa0SGrygorii Strashko __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); 335ffad5fa0SGrygorii Strashko 336ffad5fa0SGrygorii Strashko for (i = 0; i < ALE_ENTRY_WORDS; i++) 337ffad5fa0SGrygorii Strashko ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); 338ffad5fa0SGrygorii Strashko 339ffad5fa0SGrygorii Strashko return idx; 340ffad5fa0SGrygorii Strashko } 341ffad5fa0SGrygorii Strashko 342ffad5fa0SGrygorii Strashko static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) 343ffad5fa0SGrygorii Strashko { 344ffad5fa0SGrygorii Strashko int i; 345ffad5fa0SGrygorii Strashko 346ffad5fa0SGrygorii Strashko for (i = 0; i < ALE_ENTRY_WORDS; i++) 347ffad5fa0SGrygorii Strashko __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); 348ffad5fa0SGrygorii Strashko 349ffad5fa0SGrygorii Strashko __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); 350ffad5fa0SGrygorii Strashko 351ffad5fa0SGrygorii Strashko return idx; 352ffad5fa0SGrygorii Strashko } 353ffad5fa0SGrygorii Strashko 354ffad5fa0SGrygorii Strashko static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr) 355ffad5fa0SGrygorii Strashko { 356ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS]; 357ffad5fa0SGrygorii Strashko int type, idx; 358ffad5fa0SGrygorii Strashko 359ffad5fa0SGrygorii Strashko for (idx = 0; idx < priv->data.ale_entries; idx++) { 360ffad5fa0SGrygorii Strashko u8 entry_addr[6]; 361ffad5fa0SGrygorii Strashko 362ffad5fa0SGrygorii Strashko cpsw_ale_read(priv, idx, ale_entry); 363ffad5fa0SGrygorii Strashko type = cpsw_ale_get_entry_type(ale_entry); 364ffad5fa0SGrygorii Strashko if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 365ffad5fa0SGrygorii Strashko continue; 366ffad5fa0SGrygorii Strashko cpsw_ale_get_addr(ale_entry, entry_addr); 367ffad5fa0SGrygorii Strashko if (memcmp(entry_addr, addr, 6) == 0) 368ffad5fa0SGrygorii Strashko return idx; 369ffad5fa0SGrygorii Strashko } 370ffad5fa0SGrygorii Strashko return -ENOENT; 371ffad5fa0SGrygorii Strashko } 372ffad5fa0SGrygorii Strashko 373ffad5fa0SGrygorii Strashko static int cpsw_ale_match_free(struct cpsw_priv *priv) 374ffad5fa0SGrygorii Strashko { 375ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS]; 376ffad5fa0SGrygorii Strashko int type, idx; 377ffad5fa0SGrygorii Strashko 378ffad5fa0SGrygorii Strashko for (idx = 0; idx < priv->data.ale_entries; idx++) { 379ffad5fa0SGrygorii Strashko cpsw_ale_read(priv, idx, ale_entry); 380ffad5fa0SGrygorii Strashko type = cpsw_ale_get_entry_type(ale_entry); 381ffad5fa0SGrygorii Strashko if (type == ALE_TYPE_FREE) 382ffad5fa0SGrygorii Strashko return idx; 383ffad5fa0SGrygorii Strashko } 384ffad5fa0SGrygorii Strashko return -ENOENT; 385ffad5fa0SGrygorii Strashko } 386ffad5fa0SGrygorii Strashko 387ffad5fa0SGrygorii Strashko static int cpsw_ale_find_ageable(struct cpsw_priv *priv) 388ffad5fa0SGrygorii Strashko { 389ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS]; 390ffad5fa0SGrygorii Strashko int type, idx; 391ffad5fa0SGrygorii Strashko 392ffad5fa0SGrygorii Strashko for (idx = 0; idx < priv->data.ale_entries; idx++) { 393ffad5fa0SGrygorii Strashko cpsw_ale_read(priv, idx, ale_entry); 394ffad5fa0SGrygorii Strashko type = cpsw_ale_get_entry_type(ale_entry); 395ffad5fa0SGrygorii Strashko if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 396ffad5fa0SGrygorii Strashko continue; 397ffad5fa0SGrygorii Strashko if (cpsw_ale_get_mcast(ale_entry)) 398ffad5fa0SGrygorii Strashko continue; 399ffad5fa0SGrygorii Strashko type = cpsw_ale_get_ucast_type(ale_entry); 400ffad5fa0SGrygorii Strashko if (type != ALE_UCAST_PERSISTANT && 401ffad5fa0SGrygorii Strashko type != ALE_UCAST_OUI) 402ffad5fa0SGrygorii Strashko return idx; 403ffad5fa0SGrygorii Strashko } 404ffad5fa0SGrygorii Strashko return -ENOENT; 405ffad5fa0SGrygorii Strashko } 406ffad5fa0SGrygorii Strashko 407ffad5fa0SGrygorii Strashko static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr, 408ffad5fa0SGrygorii Strashko int port, int flags) 409ffad5fa0SGrygorii Strashko { 410ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 411ffad5fa0SGrygorii Strashko int idx; 412ffad5fa0SGrygorii Strashko 413ffad5fa0SGrygorii Strashko cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 414ffad5fa0SGrygorii Strashko cpsw_ale_set_addr(ale_entry, addr); 415ffad5fa0SGrygorii Strashko cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 416ffad5fa0SGrygorii Strashko cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 417ffad5fa0SGrygorii Strashko cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 418ffad5fa0SGrygorii Strashko cpsw_ale_set_port_num(ale_entry, port); 419ffad5fa0SGrygorii Strashko 420ffad5fa0SGrygorii Strashko idx = cpsw_ale_match_addr(priv, addr); 421ffad5fa0SGrygorii Strashko if (idx < 0) 422ffad5fa0SGrygorii Strashko idx = cpsw_ale_match_free(priv); 423ffad5fa0SGrygorii Strashko if (idx < 0) 424ffad5fa0SGrygorii Strashko idx = cpsw_ale_find_ageable(priv); 425ffad5fa0SGrygorii Strashko if (idx < 0) 426ffad5fa0SGrygorii Strashko return -ENOMEM; 427ffad5fa0SGrygorii Strashko 428ffad5fa0SGrygorii Strashko cpsw_ale_write(priv, idx, ale_entry); 429ffad5fa0SGrygorii Strashko return 0; 430ffad5fa0SGrygorii Strashko } 431ffad5fa0SGrygorii Strashko 432ffad5fa0SGrygorii Strashko static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr, 433ffad5fa0SGrygorii Strashko int port_mask) 434ffad5fa0SGrygorii Strashko { 435ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 436ffad5fa0SGrygorii Strashko int idx, mask; 437ffad5fa0SGrygorii Strashko 438ffad5fa0SGrygorii Strashko idx = cpsw_ale_match_addr(priv, addr); 439ffad5fa0SGrygorii Strashko if (idx >= 0) 440ffad5fa0SGrygorii Strashko cpsw_ale_read(priv, idx, ale_entry); 441ffad5fa0SGrygorii Strashko 442ffad5fa0SGrygorii Strashko cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 443ffad5fa0SGrygorii Strashko cpsw_ale_set_addr(ale_entry, addr); 444ffad5fa0SGrygorii Strashko cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2); 445ffad5fa0SGrygorii Strashko 446ffad5fa0SGrygorii Strashko mask = cpsw_ale_get_port_mask(ale_entry); 447ffad5fa0SGrygorii Strashko port_mask |= mask; 448ffad5fa0SGrygorii Strashko cpsw_ale_set_port_mask(ale_entry, port_mask); 449ffad5fa0SGrygorii Strashko 450ffad5fa0SGrygorii Strashko if (idx < 0) 451ffad5fa0SGrygorii Strashko idx = cpsw_ale_match_free(priv); 452ffad5fa0SGrygorii Strashko if (idx < 0) 453ffad5fa0SGrygorii Strashko idx = cpsw_ale_find_ageable(priv); 454ffad5fa0SGrygorii Strashko if (idx < 0) 455ffad5fa0SGrygorii Strashko return -ENOMEM; 456ffad5fa0SGrygorii Strashko 457ffad5fa0SGrygorii Strashko cpsw_ale_write(priv, idx, ale_entry); 458ffad5fa0SGrygorii Strashko return 0; 459ffad5fa0SGrygorii Strashko } 460ffad5fa0SGrygorii Strashko 461ffad5fa0SGrygorii Strashko static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val) 462ffad5fa0SGrygorii Strashko { 463ffad5fa0SGrygorii Strashko u32 tmp, mask = BIT(bit); 464ffad5fa0SGrygorii Strashko 465ffad5fa0SGrygorii Strashko tmp = __raw_readl(priv->ale_regs + ALE_CONTROL); 466ffad5fa0SGrygorii Strashko tmp &= ~mask; 467ffad5fa0SGrygorii Strashko tmp |= val ? mask : 0; 468ffad5fa0SGrygorii Strashko __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); 469ffad5fa0SGrygorii Strashko } 470ffad5fa0SGrygorii Strashko 471ffad5fa0SGrygorii Strashko #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val) 472ffad5fa0SGrygorii Strashko #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val) 473ffad5fa0SGrygorii Strashko #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val) 474ffad5fa0SGrygorii Strashko 475ffad5fa0SGrygorii Strashko static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, 476ffad5fa0SGrygorii Strashko int val) 477ffad5fa0SGrygorii Strashko { 478ffad5fa0SGrygorii Strashko int offset = ALE_PORTCTL + 4 * port; 479ffad5fa0SGrygorii Strashko u32 tmp, mask = 0x3; 480ffad5fa0SGrygorii Strashko 481ffad5fa0SGrygorii Strashko tmp = __raw_readl(priv->ale_regs + offset); 482ffad5fa0SGrygorii Strashko tmp &= ~mask; 483ffad5fa0SGrygorii Strashko tmp |= val & mask; 484ffad5fa0SGrygorii Strashko __raw_writel(tmp, priv->ale_regs + offset); 485ffad5fa0SGrygorii Strashko } 486ffad5fa0SGrygorii Strashko 487ffad5fa0SGrygorii Strashko static struct cpsw_mdio_regs *mdio_regs; 488ffad5fa0SGrygorii Strashko 489ffad5fa0SGrygorii Strashko /* wait until hardware is ready for another user access */ 490ffad5fa0SGrygorii Strashko static inline u32 wait_for_user_access(void) 491ffad5fa0SGrygorii Strashko { 492ffad5fa0SGrygorii Strashko u32 reg = 0; 493ffad5fa0SGrygorii Strashko int timeout = MDIO_TIMEOUT; 494ffad5fa0SGrygorii Strashko 495ffad5fa0SGrygorii Strashko while (timeout-- && 496ffad5fa0SGrygorii Strashko ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)) 497ffad5fa0SGrygorii Strashko udelay(10); 498ffad5fa0SGrygorii Strashko 499ffad5fa0SGrygorii Strashko if (timeout == -1) { 500ffad5fa0SGrygorii Strashko printf("wait_for_user_access Timeout\n"); 501ffad5fa0SGrygorii Strashko return -ETIMEDOUT; 502ffad5fa0SGrygorii Strashko } 503ffad5fa0SGrygorii Strashko return reg; 504ffad5fa0SGrygorii Strashko } 505ffad5fa0SGrygorii Strashko 506ffad5fa0SGrygorii Strashko /* wait until hardware state machine is idle */ 507ffad5fa0SGrygorii Strashko static inline void wait_for_idle(void) 508ffad5fa0SGrygorii Strashko { 509ffad5fa0SGrygorii Strashko int timeout = MDIO_TIMEOUT; 510ffad5fa0SGrygorii Strashko 511ffad5fa0SGrygorii Strashko while (timeout-- && 512ffad5fa0SGrygorii Strashko ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)) 513ffad5fa0SGrygorii Strashko udelay(10); 514ffad5fa0SGrygorii Strashko 515ffad5fa0SGrygorii Strashko if (timeout == -1) 516ffad5fa0SGrygorii Strashko printf("wait_for_idle Timeout\n"); 517ffad5fa0SGrygorii Strashko } 518ffad5fa0SGrygorii Strashko 519ffad5fa0SGrygorii Strashko static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, 520ffad5fa0SGrygorii Strashko int dev_addr, int phy_reg) 521ffad5fa0SGrygorii Strashko { 522ffad5fa0SGrygorii Strashko int data; 523ffad5fa0SGrygorii Strashko u32 reg; 524ffad5fa0SGrygorii Strashko 525ffad5fa0SGrygorii Strashko if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) 526ffad5fa0SGrygorii Strashko return -EINVAL; 527ffad5fa0SGrygorii Strashko 528ffad5fa0SGrygorii Strashko wait_for_user_access(); 529ffad5fa0SGrygorii Strashko reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | 530ffad5fa0SGrygorii Strashko (phy_id << 16)); 531ffad5fa0SGrygorii Strashko __raw_writel(reg, &mdio_regs->user[0].access); 532ffad5fa0SGrygorii Strashko reg = wait_for_user_access(); 533ffad5fa0SGrygorii Strashko 534ffad5fa0SGrygorii Strashko data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; 535ffad5fa0SGrygorii Strashko return data; 536ffad5fa0SGrygorii Strashko } 537ffad5fa0SGrygorii Strashko 538ffad5fa0SGrygorii Strashko static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, 539ffad5fa0SGrygorii Strashko int phy_reg, u16 data) 540ffad5fa0SGrygorii Strashko { 541ffad5fa0SGrygorii Strashko u32 reg; 542ffad5fa0SGrygorii Strashko 543ffad5fa0SGrygorii Strashko if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) 544ffad5fa0SGrygorii Strashko return -EINVAL; 545ffad5fa0SGrygorii Strashko 546ffad5fa0SGrygorii Strashko wait_for_user_access(); 547ffad5fa0SGrygorii Strashko reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | 548ffad5fa0SGrygorii Strashko (phy_id << 16) | (data & USERACCESS_DATA)); 549ffad5fa0SGrygorii Strashko __raw_writel(reg, &mdio_regs->user[0].access); 550ffad5fa0SGrygorii Strashko wait_for_user_access(); 551ffad5fa0SGrygorii Strashko 552ffad5fa0SGrygorii Strashko return 0; 553ffad5fa0SGrygorii Strashko } 554ffad5fa0SGrygorii Strashko 555ffad5fa0SGrygorii Strashko static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div) 556ffad5fa0SGrygorii Strashko { 557ffad5fa0SGrygorii Strashko struct mii_dev *bus = mdio_alloc(); 558ffad5fa0SGrygorii Strashko 559ffad5fa0SGrygorii Strashko mdio_regs = (struct cpsw_mdio_regs *)mdio_base; 560ffad5fa0SGrygorii Strashko 561ffad5fa0SGrygorii Strashko /* set enable and clock divider */ 562ffad5fa0SGrygorii Strashko __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control); 563ffad5fa0SGrygorii Strashko 564ffad5fa0SGrygorii Strashko /* 565ffad5fa0SGrygorii Strashko * wait for scan logic to settle: 566ffad5fa0SGrygorii Strashko * the scan time consists of (a) a large fixed component, and (b) a 567ffad5fa0SGrygorii Strashko * small component that varies with the mii bus frequency. These 568ffad5fa0SGrygorii Strashko * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x 569ffad5fa0SGrygorii Strashko * silicon. Since the effect of (b) was found to be largely 570ffad5fa0SGrygorii Strashko * negligible, we keep things simple here. 571ffad5fa0SGrygorii Strashko */ 572ffad5fa0SGrygorii Strashko udelay(1000); 573ffad5fa0SGrygorii Strashko 574ffad5fa0SGrygorii Strashko bus->read = cpsw_mdio_read; 575ffad5fa0SGrygorii Strashko bus->write = cpsw_mdio_write; 576ffad5fa0SGrygorii Strashko strcpy(bus->name, name); 577ffad5fa0SGrygorii Strashko 578ffad5fa0SGrygorii Strashko mdio_register(bus); 579ffad5fa0SGrygorii Strashko } 580ffad5fa0SGrygorii Strashko 581ffad5fa0SGrygorii Strashko /* Set a self-clearing bit in a register, and wait for it to clear */ 582ffad5fa0SGrygorii Strashko static inline void setbit_and_wait_for_clear32(void *addr) 583ffad5fa0SGrygorii Strashko { 584ffad5fa0SGrygorii Strashko __raw_writel(CLEAR_BIT, addr); 585ffad5fa0SGrygorii Strashko while (__raw_readl(addr) & CLEAR_BIT) 586ffad5fa0SGrygorii Strashko ; 587ffad5fa0SGrygorii Strashko } 588ffad5fa0SGrygorii Strashko 589ffad5fa0SGrygorii Strashko #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 590ffad5fa0SGrygorii Strashko ((mac)[2] << 16) | ((mac)[3] << 24)) 591ffad5fa0SGrygorii Strashko #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 592ffad5fa0SGrygorii Strashko 593ffad5fa0SGrygorii Strashko static void cpsw_set_slave_mac(struct cpsw_slave *slave, 594ffad5fa0SGrygorii Strashko struct cpsw_priv *priv) 595ffad5fa0SGrygorii Strashko { 596ffad5fa0SGrygorii Strashko #ifdef CONFIG_DM_ETH 597ffad5fa0SGrygorii Strashko struct eth_pdata *pdata = dev_get_platdata(priv->dev); 598ffad5fa0SGrygorii Strashko 599ffad5fa0SGrygorii Strashko writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi); 600ffad5fa0SGrygorii Strashko writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo); 601ffad5fa0SGrygorii Strashko #else 602ffad5fa0SGrygorii Strashko __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi); 603ffad5fa0SGrygorii Strashko __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); 604ffad5fa0SGrygorii Strashko #endif 605ffad5fa0SGrygorii Strashko } 606ffad5fa0SGrygorii Strashko 607ffad5fa0SGrygorii Strashko static int cpsw_slave_update_link(struct cpsw_slave *slave, 608ffad5fa0SGrygorii Strashko struct cpsw_priv *priv, int *link) 609ffad5fa0SGrygorii Strashko { 610ffad5fa0SGrygorii Strashko struct phy_device *phy; 611ffad5fa0SGrygorii Strashko u32 mac_control = 0; 612ffad5fa0SGrygorii Strashko int ret = -ENODEV; 613ffad5fa0SGrygorii Strashko 614ffad5fa0SGrygorii Strashko phy = priv->phydev; 615ffad5fa0SGrygorii Strashko if (!phy) 616ffad5fa0SGrygorii Strashko goto out; 617ffad5fa0SGrygorii Strashko 618ffad5fa0SGrygorii Strashko ret = phy_startup(phy); 619ffad5fa0SGrygorii Strashko if (ret) 620ffad5fa0SGrygorii Strashko goto out; 621ffad5fa0SGrygorii Strashko 622ffad5fa0SGrygorii Strashko if (link) 623ffad5fa0SGrygorii Strashko *link = phy->link; 624ffad5fa0SGrygorii Strashko 625ffad5fa0SGrygorii Strashko if (phy->link) { /* link up */ 626ffad5fa0SGrygorii Strashko mac_control = priv->data.mac_control; 627ffad5fa0SGrygorii Strashko if (phy->speed == 1000) 628ffad5fa0SGrygorii Strashko mac_control |= GIGABITEN; 629ffad5fa0SGrygorii Strashko if (phy->duplex == DUPLEX_FULL) 630ffad5fa0SGrygorii Strashko mac_control |= FULLDUPLEXEN; 631ffad5fa0SGrygorii Strashko if (phy->speed == 100) 632ffad5fa0SGrygorii Strashko mac_control |= MIIEN; 633ffad5fa0SGrygorii Strashko } 634ffad5fa0SGrygorii Strashko 635ffad5fa0SGrygorii Strashko if (mac_control == slave->mac_control) 636ffad5fa0SGrygorii Strashko goto out; 637ffad5fa0SGrygorii Strashko 638ffad5fa0SGrygorii Strashko if (mac_control) { 639ffad5fa0SGrygorii Strashko printf("link up on port %d, speed %d, %s duplex\n", 640ffad5fa0SGrygorii Strashko slave->slave_num, phy->speed, 641ffad5fa0SGrygorii Strashko (phy->duplex == DUPLEX_FULL) ? "full" : "half"); 642ffad5fa0SGrygorii Strashko } else { 643ffad5fa0SGrygorii Strashko printf("link down on port %d\n", slave->slave_num); 644ffad5fa0SGrygorii Strashko } 645ffad5fa0SGrygorii Strashko 646ffad5fa0SGrygorii Strashko __raw_writel(mac_control, &slave->sliver->mac_control); 647ffad5fa0SGrygorii Strashko slave->mac_control = mac_control; 648ffad5fa0SGrygorii Strashko 649ffad5fa0SGrygorii Strashko out: 650ffad5fa0SGrygorii Strashko return ret; 651ffad5fa0SGrygorii Strashko } 652ffad5fa0SGrygorii Strashko 653ffad5fa0SGrygorii Strashko static int cpsw_update_link(struct cpsw_priv *priv) 654ffad5fa0SGrygorii Strashko { 655ffad5fa0SGrygorii Strashko int ret = -ENODEV; 656ffad5fa0SGrygorii Strashko struct cpsw_slave *slave; 657ffad5fa0SGrygorii Strashko 658ffad5fa0SGrygorii Strashko for_active_slave(slave, priv) 659ffad5fa0SGrygorii Strashko ret = cpsw_slave_update_link(slave, priv, NULL); 660ffad5fa0SGrygorii Strashko 661ffad5fa0SGrygorii Strashko return ret; 662ffad5fa0SGrygorii Strashko } 663ffad5fa0SGrygorii Strashko 664ffad5fa0SGrygorii Strashko static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 665ffad5fa0SGrygorii Strashko { 666ffad5fa0SGrygorii Strashko if (priv->host_port == 0) 667ffad5fa0SGrygorii Strashko return slave_num + 1; 668ffad5fa0SGrygorii Strashko else 669ffad5fa0SGrygorii Strashko return slave_num; 670ffad5fa0SGrygorii Strashko } 671ffad5fa0SGrygorii Strashko 672ffad5fa0SGrygorii Strashko static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) 673ffad5fa0SGrygorii Strashko { 674ffad5fa0SGrygorii Strashko u32 slave_port; 675ffad5fa0SGrygorii Strashko 676ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(&slave->sliver->soft_reset); 677ffad5fa0SGrygorii Strashko 678ffad5fa0SGrygorii Strashko /* setup priority mapping */ 679ffad5fa0SGrygorii Strashko __raw_writel(0x76543210, &slave->sliver->rx_pri_map); 680ffad5fa0SGrygorii Strashko __raw_writel(0x33221100, &slave->regs->tx_pri_map); 681ffad5fa0SGrygorii Strashko 682ffad5fa0SGrygorii Strashko /* setup max packet size, and mac address */ 683ffad5fa0SGrygorii Strashko __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen); 684ffad5fa0SGrygorii Strashko cpsw_set_slave_mac(slave, priv); 685ffad5fa0SGrygorii Strashko 686ffad5fa0SGrygorii Strashko slave->mac_control = 0; /* no link yet */ 687ffad5fa0SGrygorii Strashko 688ffad5fa0SGrygorii Strashko /* enable forwarding */ 689ffad5fa0SGrygorii Strashko slave_port = cpsw_get_slave_port(priv, slave->slave_num); 690ffad5fa0SGrygorii Strashko cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); 691ffad5fa0SGrygorii Strashko 692ffad5fa0SGrygorii Strashko cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port); 693ffad5fa0SGrygorii Strashko 694ffad5fa0SGrygorii Strashko priv->phy_mask |= 1 << slave->data->phy_addr; 695ffad5fa0SGrygorii Strashko } 696ffad5fa0SGrygorii Strashko 697ffad5fa0SGrygorii Strashko static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) 698ffad5fa0SGrygorii Strashko { 699ffad5fa0SGrygorii Strashko struct cpdma_desc *desc = priv->desc_free; 700ffad5fa0SGrygorii Strashko 701ffad5fa0SGrygorii Strashko if (desc) 702ffad5fa0SGrygorii Strashko priv->desc_free = desc_read_ptr(desc, hw_next); 703ffad5fa0SGrygorii Strashko return desc; 704ffad5fa0SGrygorii Strashko } 705ffad5fa0SGrygorii Strashko 706ffad5fa0SGrygorii Strashko static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc) 707ffad5fa0SGrygorii Strashko { 708ffad5fa0SGrygorii Strashko if (desc) { 709ffad5fa0SGrygorii Strashko desc_write(desc, hw_next, priv->desc_free); 710ffad5fa0SGrygorii Strashko priv->desc_free = desc; 711ffad5fa0SGrygorii Strashko } 712ffad5fa0SGrygorii Strashko } 713ffad5fa0SGrygorii Strashko 714ffad5fa0SGrygorii Strashko static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan, 715ffad5fa0SGrygorii Strashko void *buffer, int len) 716ffad5fa0SGrygorii Strashko { 717ffad5fa0SGrygorii Strashko struct cpdma_desc *desc, *prev; 718ffad5fa0SGrygorii Strashko u32 mode; 719ffad5fa0SGrygorii Strashko 720ffad5fa0SGrygorii Strashko desc = cpdma_desc_alloc(priv); 721ffad5fa0SGrygorii Strashko if (!desc) 722ffad5fa0SGrygorii Strashko return -ENOMEM; 723ffad5fa0SGrygorii Strashko 724ffad5fa0SGrygorii Strashko if (len < PKT_MIN) 725ffad5fa0SGrygorii Strashko len = PKT_MIN; 726ffad5fa0SGrygorii Strashko 727ffad5fa0SGrygorii Strashko mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; 728ffad5fa0SGrygorii Strashko 729ffad5fa0SGrygorii Strashko desc_write(desc, hw_next, 0); 730ffad5fa0SGrygorii Strashko desc_write(desc, hw_buffer, buffer); 731ffad5fa0SGrygorii Strashko desc_write(desc, hw_len, len); 732ffad5fa0SGrygorii Strashko desc_write(desc, hw_mode, mode | len); 733ffad5fa0SGrygorii Strashko desc_write(desc, sw_buffer, buffer); 734ffad5fa0SGrygorii Strashko desc_write(desc, sw_len, len); 735ffad5fa0SGrygorii Strashko 736ffad5fa0SGrygorii Strashko if (!chan->head) { 737ffad5fa0SGrygorii Strashko /* simple case - first packet enqueued */ 738ffad5fa0SGrygorii Strashko chan->head = desc; 739ffad5fa0SGrygorii Strashko chan->tail = desc; 740ffad5fa0SGrygorii Strashko chan_write(chan, hdp, desc); 741ffad5fa0SGrygorii Strashko goto done; 742ffad5fa0SGrygorii Strashko } 743ffad5fa0SGrygorii Strashko 744ffad5fa0SGrygorii Strashko /* not the first packet - enqueue at the tail */ 745ffad5fa0SGrygorii Strashko prev = chan->tail; 746ffad5fa0SGrygorii Strashko desc_write(prev, hw_next, desc); 747ffad5fa0SGrygorii Strashko chan->tail = desc; 748ffad5fa0SGrygorii Strashko 749ffad5fa0SGrygorii Strashko /* next check if EOQ has been triggered already */ 750ffad5fa0SGrygorii Strashko if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ) 751ffad5fa0SGrygorii Strashko chan_write(chan, hdp, desc); 752ffad5fa0SGrygorii Strashko 753ffad5fa0SGrygorii Strashko done: 754ffad5fa0SGrygorii Strashko if (chan->rxfree) 755ffad5fa0SGrygorii Strashko chan_write(chan, rxfree, 1); 756ffad5fa0SGrygorii Strashko return 0; 757ffad5fa0SGrygorii Strashko } 758ffad5fa0SGrygorii Strashko 759ffad5fa0SGrygorii Strashko static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, 760ffad5fa0SGrygorii Strashko void **buffer, int *len) 761ffad5fa0SGrygorii Strashko { 762ffad5fa0SGrygorii Strashko struct cpdma_desc *desc = chan->head; 763ffad5fa0SGrygorii Strashko u32 status; 764ffad5fa0SGrygorii Strashko 765ffad5fa0SGrygorii Strashko if (!desc) 766ffad5fa0SGrygorii Strashko return -ENOENT; 767ffad5fa0SGrygorii Strashko 768ffad5fa0SGrygorii Strashko status = desc_read(desc, hw_mode); 769ffad5fa0SGrygorii Strashko 770ffad5fa0SGrygorii Strashko if (len) 771ffad5fa0SGrygorii Strashko *len = status & 0x7ff; 772ffad5fa0SGrygorii Strashko 773ffad5fa0SGrygorii Strashko if (buffer) 774ffad5fa0SGrygorii Strashko *buffer = desc_read_ptr(desc, sw_buffer); 775ffad5fa0SGrygorii Strashko 776ffad5fa0SGrygorii Strashko if (status & CPDMA_DESC_OWNER) { 777ffad5fa0SGrygorii Strashko if (chan_read(chan, hdp) == 0) { 778ffad5fa0SGrygorii Strashko if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER) 779ffad5fa0SGrygorii Strashko chan_write(chan, hdp, desc); 780ffad5fa0SGrygorii Strashko } 781ffad5fa0SGrygorii Strashko 782ffad5fa0SGrygorii Strashko return -EBUSY; 783ffad5fa0SGrygorii Strashko } 784ffad5fa0SGrygorii Strashko 785ffad5fa0SGrygorii Strashko chan->head = desc_read_ptr(desc, hw_next); 786ffad5fa0SGrygorii Strashko chan_write(chan, cp, desc); 787ffad5fa0SGrygorii Strashko 788ffad5fa0SGrygorii Strashko cpdma_desc_free(priv, desc); 789ffad5fa0SGrygorii Strashko return 0; 790ffad5fa0SGrygorii Strashko } 791ffad5fa0SGrygorii Strashko 792ffad5fa0SGrygorii Strashko static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) 793ffad5fa0SGrygorii Strashko { 794ffad5fa0SGrygorii Strashko struct cpsw_slave *slave; 795ffad5fa0SGrygorii Strashko int i, ret; 796ffad5fa0SGrygorii Strashko 797ffad5fa0SGrygorii Strashko /* soft reset the controller and initialize priv */ 798ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(&priv->regs->soft_reset); 799ffad5fa0SGrygorii Strashko 800ffad5fa0SGrygorii Strashko /* initialize and reset the address lookup engine */ 801ffad5fa0SGrygorii Strashko cpsw_ale_enable(priv, 1); 802ffad5fa0SGrygorii Strashko cpsw_ale_clear(priv, 1); 803ffad5fa0SGrygorii Strashko cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */ 804ffad5fa0SGrygorii Strashko 805ffad5fa0SGrygorii Strashko /* setup host port priority mapping */ 806ffad5fa0SGrygorii Strashko __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); 807ffad5fa0SGrygorii Strashko __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 808ffad5fa0SGrygorii Strashko 809ffad5fa0SGrygorii Strashko /* disable priority elevation and enable statistics on all ports */ 810ffad5fa0SGrygorii Strashko __raw_writel(0, &priv->regs->ptype); 811ffad5fa0SGrygorii Strashko 812ffad5fa0SGrygorii Strashko /* enable statistics collection only on the host port */ 813ffad5fa0SGrygorii Strashko __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); 814ffad5fa0SGrygorii Strashko __raw_writel(0x7, &priv->regs->stat_port_en); 815ffad5fa0SGrygorii Strashko 816ffad5fa0SGrygorii Strashko cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); 817ffad5fa0SGrygorii Strashko 818ffad5fa0SGrygorii Strashko cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE); 819ffad5fa0SGrygorii Strashko cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port); 820ffad5fa0SGrygorii Strashko 821ffad5fa0SGrygorii Strashko for_active_slave(slave, priv) 822ffad5fa0SGrygorii Strashko cpsw_slave_init(slave, priv); 823ffad5fa0SGrygorii Strashko 824ffad5fa0SGrygorii Strashko ret = cpsw_update_link(priv); 825ffad5fa0SGrygorii Strashko if (ret) 826ffad5fa0SGrygorii Strashko goto out; 827ffad5fa0SGrygorii Strashko 828ffad5fa0SGrygorii Strashko /* init descriptor pool */ 829ffad5fa0SGrygorii Strashko for (i = 0; i < NUM_DESCS; i++) { 830ffad5fa0SGrygorii Strashko desc_write(&priv->descs[i], hw_next, 831ffad5fa0SGrygorii Strashko (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]); 832ffad5fa0SGrygorii Strashko } 833ffad5fa0SGrygorii Strashko priv->desc_free = &priv->descs[0]; 834ffad5fa0SGrygorii Strashko 835ffad5fa0SGrygorii Strashko /* initialize channels */ 836ffad5fa0SGrygorii Strashko if (priv->data.version == CPSW_CTRL_VERSION_2) { 837ffad5fa0SGrygorii Strashko memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 838ffad5fa0SGrygorii Strashko priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2; 839ffad5fa0SGrygorii Strashko priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2; 840ffad5fa0SGrygorii Strashko priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 841ffad5fa0SGrygorii Strashko 842ffad5fa0SGrygorii Strashko memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 843ffad5fa0SGrygorii Strashko priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2; 844ffad5fa0SGrygorii Strashko priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2; 845ffad5fa0SGrygorii Strashko } else { 846ffad5fa0SGrygorii Strashko memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 847ffad5fa0SGrygorii Strashko priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1; 848ffad5fa0SGrygorii Strashko priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1; 849ffad5fa0SGrygorii Strashko priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 850ffad5fa0SGrygorii Strashko 851ffad5fa0SGrygorii Strashko memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 852ffad5fa0SGrygorii Strashko priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1; 853ffad5fa0SGrygorii Strashko priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1; 854ffad5fa0SGrygorii Strashko } 855ffad5fa0SGrygorii Strashko 856ffad5fa0SGrygorii Strashko /* clear dma state */ 857ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 858ffad5fa0SGrygorii Strashko 859ffad5fa0SGrygorii Strashko if (priv->data.version == CPSW_CTRL_VERSION_2) { 860ffad5fa0SGrygorii Strashko for (i = 0; i < priv->data.channels; i++) { 861ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 862ffad5fa0SGrygorii Strashko * i); 863ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 864ffad5fa0SGrygorii Strashko * i); 865ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 866ffad5fa0SGrygorii Strashko * i); 867ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 868ffad5fa0SGrygorii Strashko * i); 869ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 870ffad5fa0SGrygorii Strashko * i); 871ffad5fa0SGrygorii Strashko } 872ffad5fa0SGrygorii Strashko } else { 873ffad5fa0SGrygorii Strashko for (i = 0; i < priv->data.channels; i++) { 874ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 875ffad5fa0SGrygorii Strashko * i); 876ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 877ffad5fa0SGrygorii Strashko * i); 878ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 879ffad5fa0SGrygorii Strashko * i); 880ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 881ffad5fa0SGrygorii Strashko * i); 882ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 883ffad5fa0SGrygorii Strashko * i); 884ffad5fa0SGrygorii Strashko 885ffad5fa0SGrygorii Strashko } 886ffad5fa0SGrygorii Strashko } 887ffad5fa0SGrygorii Strashko 888ffad5fa0SGrygorii Strashko __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL); 889ffad5fa0SGrygorii Strashko __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL); 890ffad5fa0SGrygorii Strashko 891ffad5fa0SGrygorii Strashko /* submit rx descs */ 892ffad5fa0SGrygorii Strashko for (i = 0; i < PKTBUFSRX; i++) { 893ffad5fa0SGrygorii Strashko ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i], 894ffad5fa0SGrygorii Strashko PKTSIZE); 895ffad5fa0SGrygorii Strashko if (ret < 0) { 896ffad5fa0SGrygorii Strashko printf("error %d submitting rx desc\n", ret); 897ffad5fa0SGrygorii Strashko break; 898ffad5fa0SGrygorii Strashko } 899ffad5fa0SGrygorii Strashko } 900ffad5fa0SGrygorii Strashko 901ffad5fa0SGrygorii Strashko out: 902ffad5fa0SGrygorii Strashko return ret; 903ffad5fa0SGrygorii Strashko } 904ffad5fa0SGrygorii Strashko 905ffad5fa0SGrygorii Strashko static int cpsw_reap_completed_packets(struct cpsw_priv *priv) 906ffad5fa0SGrygorii Strashko { 907ffad5fa0SGrygorii Strashko int timeout = CPDMA_TIMEOUT; 908ffad5fa0SGrygorii Strashko 909ffad5fa0SGrygorii Strashko /* reap completed packets */ 910ffad5fa0SGrygorii Strashko while (timeout-- && 911ffad5fa0SGrygorii Strashko (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0)) 912ffad5fa0SGrygorii Strashko ; 913ffad5fa0SGrygorii Strashko 914ffad5fa0SGrygorii Strashko return timeout; 915ffad5fa0SGrygorii Strashko } 916ffad5fa0SGrygorii Strashko 917ffad5fa0SGrygorii Strashko static void _cpsw_halt(struct cpsw_priv *priv) 918ffad5fa0SGrygorii Strashko { 919ffad5fa0SGrygorii Strashko cpsw_reap_completed_packets(priv); 920ffad5fa0SGrygorii Strashko 921ffad5fa0SGrygorii Strashko writel(0, priv->dma_regs + CPDMA_TXCONTROL); 922ffad5fa0SGrygorii Strashko writel(0, priv->dma_regs + CPDMA_RXCONTROL); 923ffad5fa0SGrygorii Strashko 924ffad5fa0SGrygorii Strashko /* soft reset the controller and initialize priv */ 925ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(&priv->regs->soft_reset); 926ffad5fa0SGrygorii Strashko 927ffad5fa0SGrygorii Strashko /* clear dma state */ 928ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 929ffad5fa0SGrygorii Strashko 930ffad5fa0SGrygorii Strashko } 931ffad5fa0SGrygorii Strashko 932ffad5fa0SGrygorii Strashko static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) 933ffad5fa0SGrygorii Strashko { 934ffad5fa0SGrygorii Strashko int timeout; 935ffad5fa0SGrygorii Strashko 936ffad5fa0SGrygorii Strashko flush_dcache_range((unsigned long)packet, 937ffad5fa0SGrygorii Strashko (unsigned long)packet + ALIGN(length, PKTALIGN)); 938ffad5fa0SGrygorii Strashko 939ffad5fa0SGrygorii Strashko timeout = cpsw_reap_completed_packets(priv); 940ffad5fa0SGrygorii Strashko if (timeout == -1) { 941ffad5fa0SGrygorii Strashko printf("cpdma_process timeout\n"); 942ffad5fa0SGrygorii Strashko return -ETIMEDOUT; 943ffad5fa0SGrygorii Strashko } 944ffad5fa0SGrygorii Strashko 945ffad5fa0SGrygorii Strashko return cpdma_submit(priv, &priv->tx_chan, packet, length); 946ffad5fa0SGrygorii Strashko } 947ffad5fa0SGrygorii Strashko 948ffad5fa0SGrygorii Strashko static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt) 949ffad5fa0SGrygorii Strashko { 950ffad5fa0SGrygorii Strashko void *buffer; 951ffad5fa0SGrygorii Strashko int len; 952ffad5fa0SGrygorii Strashko int ret; 953ffad5fa0SGrygorii Strashko 954ffad5fa0SGrygorii Strashko ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len); 955ffad5fa0SGrygorii Strashko if (ret < 0) 956ffad5fa0SGrygorii Strashko return ret; 957ffad5fa0SGrygorii Strashko 958ffad5fa0SGrygorii Strashko invalidate_dcache_range((unsigned long)buffer, 959ffad5fa0SGrygorii Strashko (unsigned long)buffer + PKTSIZE_ALIGN); 960ffad5fa0SGrygorii Strashko *pkt = buffer; 961ffad5fa0SGrygorii Strashko 962ffad5fa0SGrygorii Strashko return len; 963ffad5fa0SGrygorii Strashko } 964ffad5fa0SGrygorii Strashko 965ffad5fa0SGrygorii Strashko static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, 966ffad5fa0SGrygorii Strashko struct cpsw_priv *priv) 967ffad5fa0SGrygorii Strashko { 968ffad5fa0SGrygorii Strashko void *regs = priv->regs; 969ffad5fa0SGrygorii Strashko struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 970ffad5fa0SGrygorii Strashko slave->slave_num = slave_num; 971ffad5fa0SGrygorii Strashko slave->data = data; 972ffad5fa0SGrygorii Strashko slave->regs = regs + data->slave_reg_ofs; 973ffad5fa0SGrygorii Strashko slave->sliver = regs + data->sliver_reg_ofs; 974ffad5fa0SGrygorii Strashko } 975ffad5fa0SGrygorii Strashko 976ffad5fa0SGrygorii Strashko static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) 977ffad5fa0SGrygorii Strashko { 978ffad5fa0SGrygorii Strashko struct phy_device *phydev; 979ffad5fa0SGrygorii Strashko u32 supported = PHY_GBIT_FEATURES; 980ffad5fa0SGrygorii Strashko 981ffad5fa0SGrygorii Strashko phydev = phy_connect(priv->bus, 982ffad5fa0SGrygorii Strashko slave->data->phy_addr, 983ffad5fa0SGrygorii Strashko priv->dev, 984ffad5fa0SGrygorii Strashko slave->data->phy_if); 985ffad5fa0SGrygorii Strashko 986ffad5fa0SGrygorii Strashko if (!phydev) 987ffad5fa0SGrygorii Strashko return -1; 988ffad5fa0SGrygorii Strashko 989ffad5fa0SGrygorii Strashko phydev->supported &= supported; 990ffad5fa0SGrygorii Strashko phydev->advertising = phydev->supported; 991ffad5fa0SGrygorii Strashko 992ffad5fa0SGrygorii Strashko #ifdef CONFIG_DM_ETH 993ffad5fa0SGrygorii Strashko if (slave->data->phy_of_handle) 994ffad5fa0SGrygorii Strashko phydev->node = offset_to_ofnode(slave->data->phy_of_handle); 995ffad5fa0SGrygorii Strashko #endif 996ffad5fa0SGrygorii Strashko 997ffad5fa0SGrygorii Strashko priv->phydev = phydev; 998ffad5fa0SGrygorii Strashko phy_config(phydev); 999ffad5fa0SGrygorii Strashko 1000ffad5fa0SGrygorii Strashko return 1; 1001ffad5fa0SGrygorii Strashko } 1002ffad5fa0SGrygorii Strashko 1003ffad5fa0SGrygorii Strashko static void cpsw_phy_addr_update(struct cpsw_priv *priv) 1004ffad5fa0SGrygorii Strashko { 1005ffad5fa0SGrygorii Strashko struct cpsw_platform_data *data = &priv->data; 1006ffad5fa0SGrygorii Strashko u16 alive = mdio_regs->alive & GENMASK(15, 0); 1007ffad5fa0SGrygorii Strashko int active = data->active_slave; 1008ffad5fa0SGrygorii Strashko int new_addr = ffs(alive) - 1; 1009ffad5fa0SGrygorii Strashko 1010ffad5fa0SGrygorii Strashko /* 1011ffad5fa0SGrygorii Strashko * If there is only one phy alive and its address does not match 1012ffad5fa0SGrygorii Strashko * that of active slave, then phy address can safely be updated. 1013ffad5fa0SGrygorii Strashko */ 1014ffad5fa0SGrygorii Strashko if (hweight16(alive) == 1 && 1015ffad5fa0SGrygorii Strashko data->slave_data[active].phy_addr != new_addr) { 1016ffad5fa0SGrygorii Strashko printf("Updated phy address for CPSW#%d, old: %d, new: %d\n", 1017ffad5fa0SGrygorii Strashko active, data->slave_data[active].phy_addr, new_addr); 1018ffad5fa0SGrygorii Strashko data->slave_data[active].phy_addr = new_addr; 1019ffad5fa0SGrygorii Strashko } 1020ffad5fa0SGrygorii Strashko } 1021ffad5fa0SGrygorii Strashko 1022ffad5fa0SGrygorii Strashko int _cpsw_register(struct cpsw_priv *priv) 1023ffad5fa0SGrygorii Strashko { 1024ffad5fa0SGrygorii Strashko struct cpsw_slave *slave; 1025ffad5fa0SGrygorii Strashko struct cpsw_platform_data *data = &priv->data; 1026ffad5fa0SGrygorii Strashko void *regs = (void *)data->cpsw_base; 1027ffad5fa0SGrygorii Strashko 1028ffad5fa0SGrygorii Strashko priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); 1029ffad5fa0SGrygorii Strashko if (!priv->slaves) { 1030ffad5fa0SGrygorii Strashko return -ENOMEM; 1031ffad5fa0SGrygorii Strashko } 1032ffad5fa0SGrygorii Strashko 1033ffad5fa0SGrygorii Strashko priv->host_port = data->host_port_num; 1034ffad5fa0SGrygorii Strashko priv->regs = regs; 1035ffad5fa0SGrygorii Strashko priv->host_port_regs = regs + data->host_port_reg_ofs; 1036ffad5fa0SGrygorii Strashko priv->dma_regs = regs + data->cpdma_reg_ofs; 1037ffad5fa0SGrygorii Strashko priv->ale_regs = regs + data->ale_reg_ofs; 1038ffad5fa0SGrygorii Strashko priv->descs = (void *)regs + data->bd_ram_ofs; 1039ffad5fa0SGrygorii Strashko 1040ffad5fa0SGrygorii Strashko int idx = 0; 1041ffad5fa0SGrygorii Strashko 1042ffad5fa0SGrygorii Strashko for_each_slave(slave, priv) { 1043ffad5fa0SGrygorii Strashko cpsw_slave_setup(slave, idx, priv); 1044ffad5fa0SGrygorii Strashko idx = idx + 1; 1045ffad5fa0SGrygorii Strashko } 1046ffad5fa0SGrygorii Strashko 1047ffad5fa0SGrygorii Strashko cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div); 1048ffad5fa0SGrygorii Strashko 1049ffad5fa0SGrygorii Strashko cpsw_phy_addr_update(priv); 1050ffad5fa0SGrygorii Strashko 1051ffad5fa0SGrygorii Strashko priv->bus = miiphy_get_dev_by_name(priv->dev->name); 1052ffad5fa0SGrygorii Strashko for_active_slave(slave, priv) 1053ffad5fa0SGrygorii Strashko cpsw_phy_init(priv, slave); 1054ffad5fa0SGrygorii Strashko 1055ffad5fa0SGrygorii Strashko return 0; 1056ffad5fa0SGrygorii Strashko } 1057ffad5fa0SGrygorii Strashko 1058ffad5fa0SGrygorii Strashko #ifndef CONFIG_DM_ETH 1059ffad5fa0SGrygorii Strashko static int cpsw_init(struct eth_device *dev, bd_t *bis) 1060ffad5fa0SGrygorii Strashko { 1061ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev->priv; 1062ffad5fa0SGrygorii Strashko 1063ffad5fa0SGrygorii Strashko return _cpsw_init(priv, dev->enetaddr); 1064ffad5fa0SGrygorii Strashko } 1065ffad5fa0SGrygorii Strashko 1066ffad5fa0SGrygorii Strashko static void cpsw_halt(struct eth_device *dev) 1067ffad5fa0SGrygorii Strashko { 1068ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev->priv; 1069ffad5fa0SGrygorii Strashko 1070ffad5fa0SGrygorii Strashko return _cpsw_halt(priv); 1071ffad5fa0SGrygorii Strashko } 1072ffad5fa0SGrygorii Strashko 1073ffad5fa0SGrygorii Strashko static int cpsw_send(struct eth_device *dev, void *packet, int length) 1074ffad5fa0SGrygorii Strashko { 1075ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev->priv; 1076ffad5fa0SGrygorii Strashko 1077ffad5fa0SGrygorii Strashko return _cpsw_send(priv, packet, length); 1078ffad5fa0SGrygorii Strashko } 1079ffad5fa0SGrygorii Strashko 1080ffad5fa0SGrygorii Strashko static int cpsw_recv(struct eth_device *dev) 1081ffad5fa0SGrygorii Strashko { 1082ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev->priv; 1083ffad5fa0SGrygorii Strashko uchar *pkt = NULL; 1084ffad5fa0SGrygorii Strashko int len; 1085ffad5fa0SGrygorii Strashko 1086ffad5fa0SGrygorii Strashko len = _cpsw_recv(priv, &pkt); 1087ffad5fa0SGrygorii Strashko 1088ffad5fa0SGrygorii Strashko if (len > 0) { 1089ffad5fa0SGrygorii Strashko net_process_received_packet(pkt, len); 1090ffad5fa0SGrygorii Strashko cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE); 1091ffad5fa0SGrygorii Strashko } 1092ffad5fa0SGrygorii Strashko 1093ffad5fa0SGrygorii Strashko return len; 1094ffad5fa0SGrygorii Strashko } 1095ffad5fa0SGrygorii Strashko 1096ffad5fa0SGrygorii Strashko int cpsw_register(struct cpsw_platform_data *data) 1097ffad5fa0SGrygorii Strashko { 1098ffad5fa0SGrygorii Strashko struct cpsw_priv *priv; 1099ffad5fa0SGrygorii Strashko struct eth_device *dev; 1100ffad5fa0SGrygorii Strashko int ret; 1101ffad5fa0SGrygorii Strashko 1102ffad5fa0SGrygorii Strashko dev = calloc(sizeof(*dev), 1); 1103ffad5fa0SGrygorii Strashko if (!dev) 1104ffad5fa0SGrygorii Strashko return -ENOMEM; 1105ffad5fa0SGrygorii Strashko 1106ffad5fa0SGrygorii Strashko priv = calloc(sizeof(*priv), 1); 1107ffad5fa0SGrygorii Strashko if (!priv) { 1108ffad5fa0SGrygorii Strashko free(dev); 1109ffad5fa0SGrygorii Strashko return -ENOMEM; 1110ffad5fa0SGrygorii Strashko } 1111ffad5fa0SGrygorii Strashko 1112ffad5fa0SGrygorii Strashko priv->dev = dev; 1113ffad5fa0SGrygorii Strashko priv->data = *data; 1114ffad5fa0SGrygorii Strashko 1115ffad5fa0SGrygorii Strashko strcpy(dev->name, "cpsw"); 1116ffad5fa0SGrygorii Strashko dev->iobase = 0; 1117ffad5fa0SGrygorii Strashko dev->init = cpsw_init; 1118ffad5fa0SGrygorii Strashko dev->halt = cpsw_halt; 1119ffad5fa0SGrygorii Strashko dev->send = cpsw_send; 1120ffad5fa0SGrygorii Strashko dev->recv = cpsw_recv; 1121ffad5fa0SGrygorii Strashko dev->priv = priv; 1122ffad5fa0SGrygorii Strashko 1123ffad5fa0SGrygorii Strashko eth_register(dev); 1124ffad5fa0SGrygorii Strashko 1125ffad5fa0SGrygorii Strashko ret = _cpsw_register(priv); 1126ffad5fa0SGrygorii Strashko if (ret < 0) { 1127ffad5fa0SGrygorii Strashko eth_unregister(dev); 1128ffad5fa0SGrygorii Strashko free(dev); 1129ffad5fa0SGrygorii Strashko free(priv); 1130ffad5fa0SGrygorii Strashko return ret; 1131ffad5fa0SGrygorii Strashko } 1132ffad5fa0SGrygorii Strashko 1133ffad5fa0SGrygorii Strashko return 1; 1134ffad5fa0SGrygorii Strashko } 1135ffad5fa0SGrygorii Strashko #else 1136ffad5fa0SGrygorii Strashko static int cpsw_eth_start(struct udevice *dev) 1137ffad5fa0SGrygorii Strashko { 1138ffad5fa0SGrygorii Strashko struct eth_pdata *pdata = dev_get_platdata(dev); 1139ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1140ffad5fa0SGrygorii Strashko 1141ffad5fa0SGrygorii Strashko return _cpsw_init(priv, pdata->enetaddr); 1142ffad5fa0SGrygorii Strashko } 1143ffad5fa0SGrygorii Strashko 1144ffad5fa0SGrygorii Strashko static int cpsw_eth_send(struct udevice *dev, void *packet, int length) 1145ffad5fa0SGrygorii Strashko { 1146ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1147ffad5fa0SGrygorii Strashko 1148ffad5fa0SGrygorii Strashko return _cpsw_send(priv, packet, length); 1149ffad5fa0SGrygorii Strashko } 1150ffad5fa0SGrygorii Strashko 1151ffad5fa0SGrygorii Strashko static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp) 1152ffad5fa0SGrygorii Strashko { 1153ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1154ffad5fa0SGrygorii Strashko 1155ffad5fa0SGrygorii Strashko return _cpsw_recv(priv, packetp); 1156ffad5fa0SGrygorii Strashko } 1157ffad5fa0SGrygorii Strashko 1158ffad5fa0SGrygorii Strashko static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet, 1159ffad5fa0SGrygorii Strashko int length) 1160ffad5fa0SGrygorii Strashko { 1161ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1162ffad5fa0SGrygorii Strashko 1163ffad5fa0SGrygorii Strashko return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE); 1164ffad5fa0SGrygorii Strashko } 1165ffad5fa0SGrygorii Strashko 1166ffad5fa0SGrygorii Strashko static void cpsw_eth_stop(struct udevice *dev) 1167ffad5fa0SGrygorii Strashko { 1168ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1169ffad5fa0SGrygorii Strashko 1170ffad5fa0SGrygorii Strashko return _cpsw_halt(priv); 1171ffad5fa0SGrygorii Strashko } 1172ffad5fa0SGrygorii Strashko 1173ffad5fa0SGrygorii Strashko 1174ffad5fa0SGrygorii Strashko static int cpsw_eth_probe(struct udevice *dev) 1175ffad5fa0SGrygorii Strashko { 1176ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1177ffad5fa0SGrygorii Strashko 1178ffad5fa0SGrygorii Strashko priv->dev = dev; 1179ffad5fa0SGrygorii Strashko 1180ffad5fa0SGrygorii Strashko return _cpsw_register(priv); 1181ffad5fa0SGrygorii Strashko } 1182ffad5fa0SGrygorii Strashko 1183ffad5fa0SGrygorii Strashko static const struct eth_ops cpsw_eth_ops = { 1184ffad5fa0SGrygorii Strashko .start = cpsw_eth_start, 1185ffad5fa0SGrygorii Strashko .send = cpsw_eth_send, 1186ffad5fa0SGrygorii Strashko .recv = cpsw_eth_recv, 1187ffad5fa0SGrygorii Strashko .free_pkt = cpsw_eth_free_pkt, 1188ffad5fa0SGrygorii Strashko .stop = cpsw_eth_stop, 1189ffad5fa0SGrygorii Strashko }; 1190ffad5fa0SGrygorii Strashko 1191ffad5fa0SGrygorii Strashko static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node) 1192ffad5fa0SGrygorii Strashko { 1193ffad5fa0SGrygorii Strashko return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL, 1194ffad5fa0SGrygorii Strashko false); 1195ffad5fa0SGrygorii Strashko } 1196ffad5fa0SGrygorii Strashko 1197ffad5fa0SGrygorii Strashko static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv, 1198ffad5fa0SGrygorii Strashko phy_interface_t phy_mode) 1199ffad5fa0SGrygorii Strashko { 1200ffad5fa0SGrygorii Strashko u32 reg; 1201ffad5fa0SGrygorii Strashko u32 mask; 1202ffad5fa0SGrygorii Strashko u32 mode = 0; 1203ffad5fa0SGrygorii Strashko bool rgmii_id = false; 1204ffad5fa0SGrygorii Strashko int slave = priv->data.active_slave; 1205ffad5fa0SGrygorii Strashko 1206ffad5fa0SGrygorii Strashko reg = readl(priv->data.gmii_sel); 1207ffad5fa0SGrygorii Strashko 1208ffad5fa0SGrygorii Strashko switch (phy_mode) { 1209ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RMII: 1210ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RMII; 1211ffad5fa0SGrygorii Strashko break; 1212ffad5fa0SGrygorii Strashko 1213ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII: 1214ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RGMII; 1215ffad5fa0SGrygorii Strashko break; 1216ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_ID: 1217ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_RXID: 1218ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_TXID: 1219ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RGMII; 1220ffad5fa0SGrygorii Strashko rgmii_id = true; 1221ffad5fa0SGrygorii Strashko break; 1222ffad5fa0SGrygorii Strashko 1223ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_MII: 1224ffad5fa0SGrygorii Strashko default: 1225ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_MII; 1226ffad5fa0SGrygorii Strashko break; 1227ffad5fa0SGrygorii Strashko }; 1228ffad5fa0SGrygorii Strashko 1229ffad5fa0SGrygorii Strashko mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6); 1230ffad5fa0SGrygorii Strashko mode <<= slave * 2; 1231ffad5fa0SGrygorii Strashko 1232ffad5fa0SGrygorii Strashko if (priv->data.rmii_clock_external) { 1233ffad5fa0SGrygorii Strashko if (slave == 0) 1234ffad5fa0SGrygorii Strashko mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN; 1235ffad5fa0SGrygorii Strashko else 1236ffad5fa0SGrygorii Strashko mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN; 1237ffad5fa0SGrygorii Strashko } 1238ffad5fa0SGrygorii Strashko 1239ffad5fa0SGrygorii Strashko if (rgmii_id) { 1240ffad5fa0SGrygorii Strashko if (slave == 0) 1241ffad5fa0SGrygorii Strashko mode |= AM33XX_GMII_SEL_RGMII1_IDMODE; 1242ffad5fa0SGrygorii Strashko else 1243ffad5fa0SGrygorii Strashko mode |= AM33XX_GMII_SEL_RGMII2_IDMODE; 1244ffad5fa0SGrygorii Strashko } 1245ffad5fa0SGrygorii Strashko 1246ffad5fa0SGrygorii Strashko reg &= ~mask; 1247ffad5fa0SGrygorii Strashko reg |= mode; 1248ffad5fa0SGrygorii Strashko 1249ffad5fa0SGrygorii Strashko writel(reg, priv->data.gmii_sel); 1250ffad5fa0SGrygorii Strashko } 1251ffad5fa0SGrygorii Strashko 1252ffad5fa0SGrygorii Strashko static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv, 1253ffad5fa0SGrygorii Strashko phy_interface_t phy_mode) 1254ffad5fa0SGrygorii Strashko { 1255ffad5fa0SGrygorii Strashko u32 reg; 1256ffad5fa0SGrygorii Strashko u32 mask; 1257ffad5fa0SGrygorii Strashko u32 mode = 0; 1258ffad5fa0SGrygorii Strashko int slave = priv->data.active_slave; 1259ffad5fa0SGrygorii Strashko 1260ffad5fa0SGrygorii Strashko reg = readl(priv->data.gmii_sel); 1261ffad5fa0SGrygorii Strashko 1262ffad5fa0SGrygorii Strashko switch (phy_mode) { 1263ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RMII: 1264ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RMII; 1265ffad5fa0SGrygorii Strashko break; 1266ffad5fa0SGrygorii Strashko 1267ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII: 1268ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_ID: 1269ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_RXID: 1270ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_TXID: 1271ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RGMII; 1272ffad5fa0SGrygorii Strashko break; 1273ffad5fa0SGrygorii Strashko 1274ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_MII: 1275ffad5fa0SGrygorii Strashko default: 1276ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_MII; 1277ffad5fa0SGrygorii Strashko break; 1278ffad5fa0SGrygorii Strashko }; 1279ffad5fa0SGrygorii Strashko 1280ffad5fa0SGrygorii Strashko switch (slave) { 1281ffad5fa0SGrygorii Strashko case 0: 1282ffad5fa0SGrygorii Strashko mask = GMII_SEL_MODE_MASK; 1283ffad5fa0SGrygorii Strashko break; 1284ffad5fa0SGrygorii Strashko case 1: 1285ffad5fa0SGrygorii Strashko mask = GMII_SEL_MODE_MASK << 4; 1286ffad5fa0SGrygorii Strashko mode <<= 4; 1287ffad5fa0SGrygorii Strashko break; 1288ffad5fa0SGrygorii Strashko default: 1289ffad5fa0SGrygorii Strashko dev_err(priv->dev, "invalid slave number...\n"); 1290ffad5fa0SGrygorii Strashko return; 1291ffad5fa0SGrygorii Strashko } 1292ffad5fa0SGrygorii Strashko 1293ffad5fa0SGrygorii Strashko if (priv->data.rmii_clock_external) 1294ffad5fa0SGrygorii Strashko dev_err(priv->dev, "RMII External clock is not supported\n"); 1295ffad5fa0SGrygorii Strashko 1296ffad5fa0SGrygorii Strashko reg &= ~mask; 1297ffad5fa0SGrygorii Strashko reg |= mode; 1298ffad5fa0SGrygorii Strashko 1299ffad5fa0SGrygorii Strashko writel(reg, priv->data.gmii_sel); 1300ffad5fa0SGrygorii Strashko } 1301ffad5fa0SGrygorii Strashko 1302ffad5fa0SGrygorii Strashko static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat, 1303ffad5fa0SGrygorii Strashko phy_interface_t phy_mode) 1304ffad5fa0SGrygorii Strashko { 1305ffad5fa0SGrygorii Strashko if (!strcmp(compat, "ti,am3352-cpsw-phy-sel")) 1306ffad5fa0SGrygorii Strashko cpsw_gmii_sel_am3352(priv, phy_mode); 1307ffad5fa0SGrygorii Strashko if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel")) 1308ffad5fa0SGrygorii Strashko cpsw_gmii_sel_am3352(priv, phy_mode); 1309ffad5fa0SGrygorii Strashko else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel")) 1310ffad5fa0SGrygorii Strashko cpsw_gmii_sel_dra7xx(priv, phy_mode); 1311ffad5fa0SGrygorii Strashko } 1312ffad5fa0SGrygorii Strashko 1313ffad5fa0SGrygorii Strashko static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) 1314ffad5fa0SGrygorii Strashko { 1315ffad5fa0SGrygorii Strashko struct eth_pdata *pdata = dev_get_platdata(dev); 1316ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1317ffad5fa0SGrygorii Strashko struct gpio_desc *mode_gpios; 1318ffad5fa0SGrygorii Strashko const char *phy_mode; 1319ffad5fa0SGrygorii Strashko const char *phy_sel_compat = NULL; 1320ffad5fa0SGrygorii Strashko const void *fdt = gd->fdt_blob; 1321ffad5fa0SGrygorii Strashko int node = dev_of_offset(dev); 1322ffad5fa0SGrygorii Strashko int subnode; 1323ffad5fa0SGrygorii Strashko int slave_index = 0; 1324ffad5fa0SGrygorii Strashko int active_slave; 1325ffad5fa0SGrygorii Strashko int num_mode_gpios; 1326ffad5fa0SGrygorii Strashko int ret; 1327ffad5fa0SGrygorii Strashko 1328ffad5fa0SGrygorii Strashko pdata->iobase = devfdt_get_addr(dev); 1329ffad5fa0SGrygorii Strashko priv->data.version = CPSW_CTRL_VERSION_2; 1330ffad5fa0SGrygorii Strashko priv->data.bd_ram_ofs = CPSW_BD_OFFSET; 1331ffad5fa0SGrygorii Strashko priv->data.ale_reg_ofs = CPSW_ALE_OFFSET; 1332ffad5fa0SGrygorii Strashko priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET; 1333ffad5fa0SGrygorii Strashko priv->data.mdio_div = CPSW_MDIO_DIV; 1334ffad5fa0SGrygorii Strashko priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET, 1335ffad5fa0SGrygorii Strashko 1336ffad5fa0SGrygorii Strashko pdata->phy_interface = -1; 1337ffad5fa0SGrygorii Strashko 1338ffad5fa0SGrygorii Strashko priv->data.cpsw_base = pdata->iobase; 1339ffad5fa0SGrygorii Strashko priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1); 1340ffad5fa0SGrygorii Strashko if (priv->data.channels <= 0) { 1341ffad5fa0SGrygorii Strashko printf("error: cpdma_channels not found in dt\n"); 1342ffad5fa0SGrygorii Strashko return -ENOENT; 1343ffad5fa0SGrygorii Strashko } 1344ffad5fa0SGrygorii Strashko 1345ffad5fa0SGrygorii Strashko priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1); 1346ffad5fa0SGrygorii Strashko if (priv->data.slaves <= 0) { 1347ffad5fa0SGrygorii Strashko printf("error: slaves not found in dt\n"); 1348ffad5fa0SGrygorii Strashko return -ENOENT; 1349ffad5fa0SGrygorii Strashko } 1350ffad5fa0SGrygorii Strashko priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) * 1351ffad5fa0SGrygorii Strashko priv->data.slaves); 1352ffad5fa0SGrygorii Strashko 1353ffad5fa0SGrygorii Strashko priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1); 1354ffad5fa0SGrygorii Strashko if (priv->data.ale_entries <= 0) { 1355ffad5fa0SGrygorii Strashko printf("error: ale_entries not found in dt\n"); 1356ffad5fa0SGrygorii Strashko return -ENOENT; 1357ffad5fa0SGrygorii Strashko } 1358ffad5fa0SGrygorii Strashko 1359ffad5fa0SGrygorii Strashko priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1); 1360ffad5fa0SGrygorii Strashko if (priv->data.bd_ram_ofs <= 0) { 1361ffad5fa0SGrygorii Strashko printf("error: bd_ram_size not found in dt\n"); 1362ffad5fa0SGrygorii Strashko return -ENOENT; 1363ffad5fa0SGrygorii Strashko } 1364ffad5fa0SGrygorii Strashko 1365ffad5fa0SGrygorii Strashko priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1); 1366ffad5fa0SGrygorii Strashko if (priv->data.mac_control <= 0) { 1367ffad5fa0SGrygorii Strashko printf("error: ale_entries not found in dt\n"); 1368ffad5fa0SGrygorii Strashko return -ENOENT; 1369ffad5fa0SGrygorii Strashko } 1370ffad5fa0SGrygorii Strashko 1371ffad5fa0SGrygorii Strashko num_mode_gpios = gpio_get_list_count(dev, "mode-gpios"); 1372ffad5fa0SGrygorii Strashko if (num_mode_gpios > 0) { 1373ffad5fa0SGrygorii Strashko mode_gpios = malloc(sizeof(struct gpio_desc) * 1374ffad5fa0SGrygorii Strashko num_mode_gpios); 1375ffad5fa0SGrygorii Strashko gpio_request_list_by_name(dev, "mode-gpios", mode_gpios, 1376ffad5fa0SGrygorii Strashko num_mode_gpios, GPIOD_IS_OUT); 1377ffad5fa0SGrygorii Strashko free(mode_gpios); 1378ffad5fa0SGrygorii Strashko } 1379ffad5fa0SGrygorii Strashko 1380ffad5fa0SGrygorii Strashko active_slave = fdtdec_get_int(fdt, node, "active_slave", 0); 1381ffad5fa0SGrygorii Strashko priv->data.active_slave = active_slave; 1382ffad5fa0SGrygorii Strashko 1383ffad5fa0SGrygorii Strashko fdt_for_each_subnode(subnode, fdt, node) { 1384ffad5fa0SGrygorii Strashko int len; 1385ffad5fa0SGrygorii Strashko const char *name; 1386ffad5fa0SGrygorii Strashko 1387ffad5fa0SGrygorii Strashko name = fdt_get_name(fdt, subnode, &len); 1388ffad5fa0SGrygorii Strashko if (!strncmp(name, "mdio", 4)) { 1389ffad5fa0SGrygorii Strashko u32 mdio_base; 1390ffad5fa0SGrygorii Strashko 1391ffad5fa0SGrygorii Strashko mdio_base = cpsw_get_addr_by_node(fdt, subnode); 1392ffad5fa0SGrygorii Strashko if (mdio_base == FDT_ADDR_T_NONE) { 1393ffad5fa0SGrygorii Strashko pr_err("Not able to get MDIO address space\n"); 1394ffad5fa0SGrygorii Strashko return -ENOENT; 1395ffad5fa0SGrygorii Strashko } 1396ffad5fa0SGrygorii Strashko priv->data.mdio_base = mdio_base; 1397ffad5fa0SGrygorii Strashko } 1398ffad5fa0SGrygorii Strashko 1399ffad5fa0SGrygorii Strashko if (!strncmp(name, "slave", 5)) { 1400ffad5fa0SGrygorii Strashko u32 phy_id[2]; 1401ffad5fa0SGrygorii Strashko 1402ffad5fa0SGrygorii Strashko if (slave_index >= priv->data.slaves) 1403ffad5fa0SGrygorii Strashko continue; 1404ffad5fa0SGrygorii Strashko phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL); 1405ffad5fa0SGrygorii Strashko if (phy_mode) 1406ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_if = 1407ffad5fa0SGrygorii Strashko phy_get_interface_by_name(phy_mode); 1408ffad5fa0SGrygorii Strashko 1409ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_of_handle = 1410ffad5fa0SGrygorii Strashko fdtdec_lookup_phandle(fdt, subnode, 1411ffad5fa0SGrygorii Strashko "phy-handle"); 1412ffad5fa0SGrygorii Strashko 1413ffad5fa0SGrygorii Strashko if (priv->data.slave_data[slave_index].phy_of_handle >= 0) { 1414ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_addr = 1415ffad5fa0SGrygorii Strashko fdtdec_get_int(gd->fdt_blob, 1416ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_of_handle, 1417ffad5fa0SGrygorii Strashko "reg", -1); 1418ffad5fa0SGrygorii Strashko } else { 1419ffad5fa0SGrygorii Strashko fdtdec_get_int_array(fdt, subnode, "phy_id", 1420ffad5fa0SGrygorii Strashko phy_id, 2); 1421ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_addr = 1422ffad5fa0SGrygorii Strashko phy_id[1]; 1423ffad5fa0SGrygorii Strashko } 1424ffad5fa0SGrygorii Strashko slave_index++; 1425ffad5fa0SGrygorii Strashko } 1426ffad5fa0SGrygorii Strashko 1427ffad5fa0SGrygorii Strashko if (!strncmp(name, "cpsw-phy-sel", 12)) { 1428ffad5fa0SGrygorii Strashko priv->data.gmii_sel = cpsw_get_addr_by_node(fdt, 1429ffad5fa0SGrygorii Strashko subnode); 1430ffad5fa0SGrygorii Strashko 1431ffad5fa0SGrygorii Strashko if (priv->data.gmii_sel == FDT_ADDR_T_NONE) { 1432ffad5fa0SGrygorii Strashko pr_err("Not able to get gmii_sel reg address\n"); 1433ffad5fa0SGrygorii Strashko return -ENOENT; 1434ffad5fa0SGrygorii Strashko } 1435ffad5fa0SGrygorii Strashko 1436ffad5fa0SGrygorii Strashko if (fdt_get_property(fdt, subnode, "rmii-clock-ext", 1437ffad5fa0SGrygorii Strashko NULL)) 1438ffad5fa0SGrygorii Strashko priv->data.rmii_clock_external = true; 1439ffad5fa0SGrygorii Strashko 1440ffad5fa0SGrygorii Strashko phy_sel_compat = fdt_getprop(fdt, subnode, "compatible", 1441ffad5fa0SGrygorii Strashko NULL); 1442ffad5fa0SGrygorii Strashko if (!phy_sel_compat) { 1443ffad5fa0SGrygorii Strashko pr_err("Not able to get gmii_sel compatible\n"); 1444ffad5fa0SGrygorii Strashko return -ENOENT; 1445ffad5fa0SGrygorii Strashko } 1446ffad5fa0SGrygorii Strashko } 1447ffad5fa0SGrygorii Strashko } 1448ffad5fa0SGrygorii Strashko 1449ffad5fa0SGrygorii Strashko priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET; 1450ffad5fa0SGrygorii Strashko priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET; 1451ffad5fa0SGrygorii Strashko 1452ffad5fa0SGrygorii Strashko if (priv->data.slaves == 2) { 1453ffad5fa0SGrygorii Strashko priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET; 1454ffad5fa0SGrygorii Strashko priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET; 1455ffad5fa0SGrygorii Strashko } 1456ffad5fa0SGrygorii Strashko 1457ffad5fa0SGrygorii Strashko ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr); 1458ffad5fa0SGrygorii Strashko if (ret < 0) { 1459ffad5fa0SGrygorii Strashko pr_err("cpsw read efuse mac failed\n"); 1460ffad5fa0SGrygorii Strashko return ret; 1461ffad5fa0SGrygorii Strashko } 1462ffad5fa0SGrygorii Strashko 1463ffad5fa0SGrygorii Strashko pdata->phy_interface = priv->data.slave_data[active_slave].phy_if; 1464ffad5fa0SGrygorii Strashko if (pdata->phy_interface == -1) { 1465ffad5fa0SGrygorii Strashko debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1466ffad5fa0SGrygorii Strashko return -EINVAL; 1467ffad5fa0SGrygorii Strashko } 1468ffad5fa0SGrygorii Strashko 1469ffad5fa0SGrygorii Strashko /* Select phy interface in control module */ 1470ffad5fa0SGrygorii Strashko cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface); 1471ffad5fa0SGrygorii Strashko 1472ffad5fa0SGrygorii Strashko return 0; 1473ffad5fa0SGrygorii Strashko } 1474ffad5fa0SGrygorii Strashko 1475ffad5fa0SGrygorii Strashko int cpsw_get_slave_phy_addr(struct udevice *dev, int slave) 1476ffad5fa0SGrygorii Strashko { 1477ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1478ffad5fa0SGrygorii Strashko struct cpsw_platform_data *data = &priv->data; 1479ffad5fa0SGrygorii Strashko 1480ffad5fa0SGrygorii Strashko return data->slave_data[slave].phy_addr; 1481ffad5fa0SGrygorii Strashko } 1482ffad5fa0SGrygorii Strashko 1483ffad5fa0SGrygorii Strashko static const struct udevice_id cpsw_eth_ids[] = { 1484ffad5fa0SGrygorii Strashko { .compatible = "ti,cpsw" }, 1485ffad5fa0SGrygorii Strashko { .compatible = "ti,am335x-cpsw" }, 1486ffad5fa0SGrygorii Strashko { } 1487ffad5fa0SGrygorii Strashko }; 1488ffad5fa0SGrygorii Strashko 1489ffad5fa0SGrygorii Strashko U_BOOT_DRIVER(eth_cpsw) = { 1490ffad5fa0SGrygorii Strashko .name = "eth_cpsw", 1491ffad5fa0SGrygorii Strashko .id = UCLASS_ETH, 1492ffad5fa0SGrygorii Strashko .of_match = cpsw_eth_ids, 1493ffad5fa0SGrygorii Strashko .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata, 1494ffad5fa0SGrygorii Strashko .probe = cpsw_eth_probe, 1495ffad5fa0SGrygorii Strashko .ops = &cpsw_eth_ops, 1496ffad5fa0SGrygorii Strashko .priv_auto_alloc_size = sizeof(struct cpsw_priv), 1497ffad5fa0SGrygorii Strashko .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1498ffad5fa0SGrygorii Strashko .flags = DM_FLAG_ALLOC_PRIV_DMA, 1499ffad5fa0SGrygorii Strashko }; 1500ffad5fa0SGrygorii Strashko #endif /* CONFIG_DM_ETH */ 1501