1cbec53b4SGrygorii Strashko // SPDX-License-Identifier: GPL-2.0+ 2ffad5fa0SGrygorii Strashko /* 3ffad5fa0SGrygorii Strashko * CPSW Ethernet Switch Driver 4ffad5fa0SGrygorii Strashko * 5cbec53b4SGrygorii Strashko * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/ 6ffad5fa0SGrygorii Strashko */ 7ffad5fa0SGrygorii Strashko 8ffad5fa0SGrygorii Strashko #include <common.h> 9ffad5fa0SGrygorii Strashko #include <command.h> 10ffad5fa0SGrygorii Strashko #include <net.h> 11ffad5fa0SGrygorii Strashko #include <miiphy.h> 12ffad5fa0SGrygorii Strashko #include <malloc.h> 13ffad5fa0SGrygorii Strashko #include <net.h> 14ffad5fa0SGrygorii Strashko #include <netdev.h> 15ffad5fa0SGrygorii Strashko #include <cpsw.h> 16ffad5fa0SGrygorii Strashko #include <linux/errno.h> 17ffad5fa0SGrygorii Strashko #include <asm/gpio.h> 18ffad5fa0SGrygorii Strashko #include <asm/io.h> 19ffad5fa0SGrygorii Strashko #include <phy.h> 20ffad5fa0SGrygorii Strashko #include <asm/arch/cpu.h> 21ffad5fa0SGrygorii Strashko #include <dm.h> 22ffad5fa0SGrygorii Strashko #include <fdt_support.h> 23ffad5fa0SGrygorii Strashko 24*4f41cd9aSGrygorii Strashko #include "cpsw_mdio.h" 25*4f41cd9aSGrygorii Strashko 26ffad5fa0SGrygorii Strashko DECLARE_GLOBAL_DATA_PTR; 27ffad5fa0SGrygorii Strashko 28ffad5fa0SGrygorii Strashko #define BITMASK(bits) (BIT(bits) - 1) 29ffad5fa0SGrygorii Strashko #define NUM_DESCS (PKTBUFSRX * 2) 30ffad5fa0SGrygorii Strashko #define PKT_MIN 60 31ffad5fa0SGrygorii Strashko #define PKT_MAX (1500 + 14 + 4 + 4) 32ffad5fa0SGrygorii Strashko #define CLEAR_BIT 1 33ffad5fa0SGrygorii Strashko #define GIGABITEN BIT(7) 34ffad5fa0SGrygorii Strashko #define FULLDUPLEXEN BIT(0) 35ffad5fa0SGrygorii Strashko #define MIIEN BIT(15) 36ffad5fa0SGrygorii Strashko 37ffad5fa0SGrygorii Strashko /* reg offset */ 38ffad5fa0SGrygorii Strashko #define CPSW_HOST_PORT_OFFSET 0x108 39ffad5fa0SGrygorii Strashko #define CPSW_SLAVE0_OFFSET 0x208 40ffad5fa0SGrygorii Strashko #define CPSW_SLAVE1_OFFSET 0x308 41ffad5fa0SGrygorii Strashko #define CPSW_SLAVE_SIZE 0x100 42ffad5fa0SGrygorii Strashko #define CPSW_CPDMA_OFFSET 0x800 43ffad5fa0SGrygorii Strashko #define CPSW_HW_STATS 0x900 44ffad5fa0SGrygorii Strashko #define CPSW_STATERAM_OFFSET 0xa00 45ffad5fa0SGrygorii Strashko #define CPSW_CPTS_OFFSET 0xc00 46ffad5fa0SGrygorii Strashko #define CPSW_ALE_OFFSET 0xd00 47ffad5fa0SGrygorii Strashko #define CPSW_SLIVER0_OFFSET 0xd80 48ffad5fa0SGrygorii Strashko #define CPSW_SLIVER1_OFFSET 0xdc0 49ffad5fa0SGrygorii Strashko #define CPSW_BD_OFFSET 0x2000 50ffad5fa0SGrygorii Strashko #define CPSW_MDIO_DIV 0xff 51ffad5fa0SGrygorii Strashko 52ffad5fa0SGrygorii Strashko #define AM335X_GMII_SEL_OFFSET 0x630 53ffad5fa0SGrygorii Strashko 54ffad5fa0SGrygorii Strashko /* DMA Registers */ 55ffad5fa0SGrygorii Strashko #define CPDMA_TXCONTROL 0x004 56ffad5fa0SGrygorii Strashko #define CPDMA_RXCONTROL 0x014 57ffad5fa0SGrygorii Strashko #define CPDMA_SOFTRESET 0x01c 58ffad5fa0SGrygorii Strashko #define CPDMA_RXFREE 0x0e0 59ffad5fa0SGrygorii Strashko #define CPDMA_TXHDP_VER1 0x100 60ffad5fa0SGrygorii Strashko #define CPDMA_TXHDP_VER2 0x200 61ffad5fa0SGrygorii Strashko #define CPDMA_RXHDP_VER1 0x120 62ffad5fa0SGrygorii Strashko #define CPDMA_RXHDP_VER2 0x220 63ffad5fa0SGrygorii Strashko #define CPDMA_TXCP_VER1 0x140 64ffad5fa0SGrygorii Strashko #define CPDMA_TXCP_VER2 0x240 65ffad5fa0SGrygorii Strashko #define CPDMA_RXCP_VER1 0x160 66ffad5fa0SGrygorii Strashko #define CPDMA_RXCP_VER2 0x260 67ffad5fa0SGrygorii Strashko 68ffad5fa0SGrygorii Strashko /* Descriptor mode bits */ 69ffad5fa0SGrygorii Strashko #define CPDMA_DESC_SOP BIT(31) 70ffad5fa0SGrygorii Strashko #define CPDMA_DESC_EOP BIT(30) 71ffad5fa0SGrygorii Strashko #define CPDMA_DESC_OWNER BIT(29) 72ffad5fa0SGrygorii Strashko #define CPDMA_DESC_EOQ BIT(28) 73ffad5fa0SGrygorii Strashko 74ffad5fa0SGrygorii Strashko /* 75ffad5fa0SGrygorii Strashko * This timeout definition is a worst-case ultra defensive measure against 76ffad5fa0SGrygorii Strashko * unexpected controller lock ups. Ideally, we should never ever hit this 77ffad5fa0SGrygorii Strashko * scenario in practice. 78ffad5fa0SGrygorii Strashko */ 79ffad5fa0SGrygorii Strashko #define CPDMA_TIMEOUT 100 /* msecs */ 80ffad5fa0SGrygorii Strashko 81ffad5fa0SGrygorii Strashko struct cpsw_regs { 82ffad5fa0SGrygorii Strashko u32 id_ver; 83ffad5fa0SGrygorii Strashko u32 control; 84ffad5fa0SGrygorii Strashko u32 soft_reset; 85ffad5fa0SGrygorii Strashko u32 stat_port_en; 86ffad5fa0SGrygorii Strashko u32 ptype; 87ffad5fa0SGrygorii Strashko }; 88ffad5fa0SGrygorii Strashko 89ffad5fa0SGrygorii Strashko struct cpsw_slave_regs { 90ffad5fa0SGrygorii Strashko u32 max_blks; 91ffad5fa0SGrygorii Strashko u32 blk_cnt; 92ffad5fa0SGrygorii Strashko u32 flow_thresh; 93ffad5fa0SGrygorii Strashko u32 port_vlan; 94ffad5fa0SGrygorii Strashko u32 tx_pri_map; 95ffad5fa0SGrygorii Strashko #ifdef CONFIG_AM33XX 96ffad5fa0SGrygorii Strashko u32 gap_thresh; 97ffad5fa0SGrygorii Strashko #elif defined(CONFIG_TI814X) 98ffad5fa0SGrygorii Strashko u32 ts_ctl; 99ffad5fa0SGrygorii Strashko u32 ts_seq_ltype; 100ffad5fa0SGrygorii Strashko u32 ts_vlan; 101ffad5fa0SGrygorii Strashko #endif 102ffad5fa0SGrygorii Strashko u32 sa_lo; 103ffad5fa0SGrygorii Strashko u32 sa_hi; 104ffad5fa0SGrygorii Strashko }; 105ffad5fa0SGrygorii Strashko 106ffad5fa0SGrygorii Strashko struct cpsw_host_regs { 107ffad5fa0SGrygorii Strashko u32 max_blks; 108ffad5fa0SGrygorii Strashko u32 blk_cnt; 109ffad5fa0SGrygorii Strashko u32 flow_thresh; 110ffad5fa0SGrygorii Strashko u32 port_vlan; 111ffad5fa0SGrygorii Strashko u32 tx_pri_map; 112ffad5fa0SGrygorii Strashko u32 cpdma_tx_pri_map; 113ffad5fa0SGrygorii Strashko u32 cpdma_rx_chan_map; 114ffad5fa0SGrygorii Strashko }; 115ffad5fa0SGrygorii Strashko 116ffad5fa0SGrygorii Strashko struct cpsw_sliver_regs { 117ffad5fa0SGrygorii Strashko u32 id_ver; 118ffad5fa0SGrygorii Strashko u32 mac_control; 119ffad5fa0SGrygorii Strashko u32 mac_status; 120ffad5fa0SGrygorii Strashko u32 soft_reset; 121ffad5fa0SGrygorii Strashko u32 rx_maxlen; 122ffad5fa0SGrygorii Strashko u32 __reserved_0; 123ffad5fa0SGrygorii Strashko u32 rx_pause; 124ffad5fa0SGrygorii Strashko u32 tx_pause; 125ffad5fa0SGrygorii Strashko u32 __reserved_1; 126ffad5fa0SGrygorii Strashko u32 rx_pri_map; 127ffad5fa0SGrygorii Strashko }; 128ffad5fa0SGrygorii Strashko 129ffad5fa0SGrygorii Strashko #define ALE_ENTRY_BITS 68 130ffad5fa0SGrygorii Strashko #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32) 131ffad5fa0SGrygorii Strashko 132ffad5fa0SGrygorii Strashko /* ALE Registers */ 133ffad5fa0SGrygorii Strashko #define ALE_CONTROL 0x08 134ffad5fa0SGrygorii Strashko #define ALE_UNKNOWNVLAN 0x18 135ffad5fa0SGrygorii Strashko #define ALE_TABLE_CONTROL 0x20 136ffad5fa0SGrygorii Strashko #define ALE_TABLE 0x34 137ffad5fa0SGrygorii Strashko #define ALE_PORTCTL 0x40 138ffad5fa0SGrygorii Strashko 139ffad5fa0SGrygorii Strashko #define ALE_TABLE_WRITE BIT(31) 140ffad5fa0SGrygorii Strashko 141ffad5fa0SGrygorii Strashko #define ALE_TYPE_FREE 0 142ffad5fa0SGrygorii Strashko #define ALE_TYPE_ADDR 1 143ffad5fa0SGrygorii Strashko #define ALE_TYPE_VLAN 2 144ffad5fa0SGrygorii Strashko #define ALE_TYPE_VLAN_ADDR 3 145ffad5fa0SGrygorii Strashko 146ffad5fa0SGrygorii Strashko #define ALE_UCAST_PERSISTANT 0 147ffad5fa0SGrygorii Strashko #define ALE_UCAST_UNTOUCHED 1 148ffad5fa0SGrygorii Strashko #define ALE_UCAST_OUI 2 149ffad5fa0SGrygorii Strashko #define ALE_UCAST_TOUCHED 3 150ffad5fa0SGrygorii Strashko 151ffad5fa0SGrygorii Strashko #define ALE_MCAST_FWD 0 152ffad5fa0SGrygorii Strashko #define ALE_MCAST_BLOCK_LEARN_FWD 1 153ffad5fa0SGrygorii Strashko #define ALE_MCAST_FWD_LEARN 2 154ffad5fa0SGrygorii Strashko #define ALE_MCAST_FWD_2 3 155ffad5fa0SGrygorii Strashko 156ffad5fa0SGrygorii Strashko enum cpsw_ale_port_state { 157ffad5fa0SGrygorii Strashko ALE_PORT_STATE_DISABLE = 0x00, 158ffad5fa0SGrygorii Strashko ALE_PORT_STATE_BLOCK = 0x01, 159ffad5fa0SGrygorii Strashko ALE_PORT_STATE_LEARN = 0x02, 160ffad5fa0SGrygorii Strashko ALE_PORT_STATE_FORWARD = 0x03, 161ffad5fa0SGrygorii Strashko }; 162ffad5fa0SGrygorii Strashko 163ffad5fa0SGrygorii Strashko /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */ 164ffad5fa0SGrygorii Strashko #define ALE_SECURE 1 165ffad5fa0SGrygorii Strashko #define ALE_BLOCKED 2 166ffad5fa0SGrygorii Strashko 167ffad5fa0SGrygorii Strashko struct cpsw_slave { 168ffad5fa0SGrygorii Strashko struct cpsw_slave_regs *regs; 169ffad5fa0SGrygorii Strashko struct cpsw_sliver_regs *sliver; 170ffad5fa0SGrygorii Strashko int slave_num; 171ffad5fa0SGrygorii Strashko u32 mac_control; 172ffad5fa0SGrygorii Strashko struct cpsw_slave_data *data; 173ffad5fa0SGrygorii Strashko }; 174ffad5fa0SGrygorii Strashko 175ffad5fa0SGrygorii Strashko struct cpdma_desc { 176ffad5fa0SGrygorii Strashko /* hardware fields */ 177ffad5fa0SGrygorii Strashko u32 hw_next; 178ffad5fa0SGrygorii Strashko u32 hw_buffer; 179ffad5fa0SGrygorii Strashko u32 hw_len; 180ffad5fa0SGrygorii Strashko u32 hw_mode; 181ffad5fa0SGrygorii Strashko /* software fields */ 182ffad5fa0SGrygorii Strashko u32 sw_buffer; 183ffad5fa0SGrygorii Strashko u32 sw_len; 184ffad5fa0SGrygorii Strashko }; 185ffad5fa0SGrygorii Strashko 186ffad5fa0SGrygorii Strashko struct cpdma_chan { 187ffad5fa0SGrygorii Strashko struct cpdma_desc *head, *tail; 188ffad5fa0SGrygorii Strashko void *hdp, *cp, *rxfree; 189ffad5fa0SGrygorii Strashko }; 190ffad5fa0SGrygorii Strashko 191ffad5fa0SGrygorii Strashko /* AM33xx SoC specific definitions for the CONTROL port */ 192ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_MODE_MII 0 193ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_MODE_RMII 1 194ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_MODE_RGMII 2 195ffad5fa0SGrygorii Strashko 196ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4) 197ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5) 198ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6) 199ffad5fa0SGrygorii Strashko #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7) 200ffad5fa0SGrygorii Strashko 201ffad5fa0SGrygorii Strashko #define GMII_SEL_MODE_MASK 0x3 202ffad5fa0SGrygorii Strashko 203ffad5fa0SGrygorii Strashko #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) 204ffad5fa0SGrygorii Strashko #define desc_read(desc, fld) __raw_readl(&(desc)->fld) 205ffad5fa0SGrygorii Strashko #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) 206ffad5fa0SGrygorii Strashko 207ffad5fa0SGrygorii Strashko #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld) 208ffad5fa0SGrygorii Strashko #define chan_read(chan, fld) __raw_readl((chan)->fld) 209ffad5fa0SGrygorii Strashko #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) 210ffad5fa0SGrygorii Strashko 211ffad5fa0SGrygorii Strashko #define for_active_slave(slave, priv) \ 212ffad5fa0SGrygorii Strashko slave = (priv)->slaves + (priv)->data.active_slave; if (slave) 213ffad5fa0SGrygorii Strashko #define for_each_slave(slave, priv) \ 214ffad5fa0SGrygorii Strashko for (slave = (priv)->slaves; slave != (priv)->slaves + \ 215ffad5fa0SGrygorii Strashko (priv)->data.slaves; slave++) 216ffad5fa0SGrygorii Strashko 217ffad5fa0SGrygorii Strashko struct cpsw_priv { 218ffad5fa0SGrygorii Strashko #ifdef CONFIG_DM_ETH 219ffad5fa0SGrygorii Strashko struct udevice *dev; 220ffad5fa0SGrygorii Strashko #else 221ffad5fa0SGrygorii Strashko struct eth_device *dev; 222ffad5fa0SGrygorii Strashko #endif 223ffad5fa0SGrygorii Strashko struct cpsw_platform_data data; 224ffad5fa0SGrygorii Strashko int host_port; 225ffad5fa0SGrygorii Strashko 226ffad5fa0SGrygorii Strashko struct cpsw_regs *regs; 227ffad5fa0SGrygorii Strashko void *dma_regs; 228ffad5fa0SGrygorii Strashko struct cpsw_host_regs *host_port_regs; 229ffad5fa0SGrygorii Strashko void *ale_regs; 230ffad5fa0SGrygorii Strashko 231ffad5fa0SGrygorii Strashko struct cpdma_desc *descs; 232ffad5fa0SGrygorii Strashko struct cpdma_desc *desc_free; 233ffad5fa0SGrygorii Strashko struct cpdma_chan rx_chan, tx_chan; 234ffad5fa0SGrygorii Strashko 235ffad5fa0SGrygorii Strashko struct cpsw_slave *slaves; 236ffad5fa0SGrygorii Strashko struct phy_device *phydev; 237ffad5fa0SGrygorii Strashko struct mii_dev *bus; 238ffad5fa0SGrygorii Strashko 239ffad5fa0SGrygorii Strashko u32 phy_mask; 240ffad5fa0SGrygorii Strashko }; 241ffad5fa0SGrygorii Strashko 242ffad5fa0SGrygorii Strashko static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 243ffad5fa0SGrygorii Strashko { 244ffad5fa0SGrygorii Strashko int idx; 245ffad5fa0SGrygorii Strashko 246ffad5fa0SGrygorii Strashko idx = start / 32; 247ffad5fa0SGrygorii Strashko start -= idx * 32; 248ffad5fa0SGrygorii Strashko idx = 2 - idx; /* flip */ 249ffad5fa0SGrygorii Strashko return (ale_entry[idx] >> start) & BITMASK(bits); 250ffad5fa0SGrygorii Strashko } 251ffad5fa0SGrygorii Strashko 252ffad5fa0SGrygorii Strashko static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 253ffad5fa0SGrygorii Strashko u32 value) 254ffad5fa0SGrygorii Strashko { 255ffad5fa0SGrygorii Strashko int idx; 256ffad5fa0SGrygorii Strashko 257ffad5fa0SGrygorii Strashko value &= BITMASK(bits); 258ffad5fa0SGrygorii Strashko idx = start / 32; 259ffad5fa0SGrygorii Strashko start -= idx * 32; 260ffad5fa0SGrygorii Strashko idx = 2 - idx; /* flip */ 261ffad5fa0SGrygorii Strashko ale_entry[idx] &= ~(BITMASK(bits) << start); 262ffad5fa0SGrygorii Strashko ale_entry[idx] |= (value << start); 263ffad5fa0SGrygorii Strashko } 264ffad5fa0SGrygorii Strashko 265ffad5fa0SGrygorii Strashko #define DEFINE_ALE_FIELD(name, start, bits) \ 266ffad5fa0SGrygorii Strashko static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 267ffad5fa0SGrygorii Strashko { \ 268ffad5fa0SGrygorii Strashko return cpsw_ale_get_field(ale_entry, start, bits); \ 269ffad5fa0SGrygorii Strashko } \ 270ffad5fa0SGrygorii Strashko static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 271ffad5fa0SGrygorii Strashko { \ 272ffad5fa0SGrygorii Strashko cpsw_ale_set_field(ale_entry, start, bits, value); \ 273ffad5fa0SGrygorii Strashko } 274ffad5fa0SGrygorii Strashko 275ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(entry_type, 60, 2) 276ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(mcast_state, 62, 2) 277ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(port_mask, 66, 3) 278ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(ucast_type, 62, 2) 279ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(port_num, 66, 2) 280ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(blocked, 65, 1) 281ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(secure, 64, 1) 282ffad5fa0SGrygorii Strashko DEFINE_ALE_FIELD(mcast, 40, 1) 283ffad5fa0SGrygorii Strashko 284ffad5fa0SGrygorii Strashko /* The MAC address field in the ALE entry cannot be macroized as above */ 285ffad5fa0SGrygorii Strashko static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 286ffad5fa0SGrygorii Strashko { 287ffad5fa0SGrygorii Strashko int i; 288ffad5fa0SGrygorii Strashko 289ffad5fa0SGrygorii Strashko for (i = 0; i < 6; i++) 290ffad5fa0SGrygorii Strashko addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 291ffad5fa0SGrygorii Strashko } 292ffad5fa0SGrygorii Strashko 293ffad5fa0SGrygorii Strashko static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) 294ffad5fa0SGrygorii Strashko { 295ffad5fa0SGrygorii Strashko int i; 296ffad5fa0SGrygorii Strashko 297ffad5fa0SGrygorii Strashko for (i = 0; i < 6; i++) 298ffad5fa0SGrygorii Strashko cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 299ffad5fa0SGrygorii Strashko } 300ffad5fa0SGrygorii Strashko 301ffad5fa0SGrygorii Strashko static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) 302ffad5fa0SGrygorii Strashko { 303ffad5fa0SGrygorii Strashko int i; 304ffad5fa0SGrygorii Strashko 305ffad5fa0SGrygorii Strashko __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); 306ffad5fa0SGrygorii Strashko 307ffad5fa0SGrygorii Strashko for (i = 0; i < ALE_ENTRY_WORDS; i++) 308ffad5fa0SGrygorii Strashko ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); 309ffad5fa0SGrygorii Strashko 310ffad5fa0SGrygorii Strashko return idx; 311ffad5fa0SGrygorii Strashko } 312ffad5fa0SGrygorii Strashko 313ffad5fa0SGrygorii Strashko static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) 314ffad5fa0SGrygorii Strashko { 315ffad5fa0SGrygorii Strashko int i; 316ffad5fa0SGrygorii Strashko 317ffad5fa0SGrygorii Strashko for (i = 0; i < ALE_ENTRY_WORDS; i++) 318ffad5fa0SGrygorii Strashko __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); 319ffad5fa0SGrygorii Strashko 320ffad5fa0SGrygorii Strashko __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); 321ffad5fa0SGrygorii Strashko 322ffad5fa0SGrygorii Strashko return idx; 323ffad5fa0SGrygorii Strashko } 324ffad5fa0SGrygorii Strashko 325ffad5fa0SGrygorii Strashko static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr) 326ffad5fa0SGrygorii Strashko { 327ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS]; 328ffad5fa0SGrygorii Strashko int type, idx; 329ffad5fa0SGrygorii Strashko 330ffad5fa0SGrygorii Strashko for (idx = 0; idx < priv->data.ale_entries; idx++) { 331ffad5fa0SGrygorii Strashko u8 entry_addr[6]; 332ffad5fa0SGrygorii Strashko 333ffad5fa0SGrygorii Strashko cpsw_ale_read(priv, idx, ale_entry); 334ffad5fa0SGrygorii Strashko type = cpsw_ale_get_entry_type(ale_entry); 335ffad5fa0SGrygorii Strashko if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 336ffad5fa0SGrygorii Strashko continue; 337ffad5fa0SGrygorii Strashko cpsw_ale_get_addr(ale_entry, entry_addr); 338ffad5fa0SGrygorii Strashko if (memcmp(entry_addr, addr, 6) == 0) 339ffad5fa0SGrygorii Strashko return idx; 340ffad5fa0SGrygorii Strashko } 341ffad5fa0SGrygorii Strashko return -ENOENT; 342ffad5fa0SGrygorii Strashko } 343ffad5fa0SGrygorii Strashko 344ffad5fa0SGrygorii Strashko static int cpsw_ale_match_free(struct cpsw_priv *priv) 345ffad5fa0SGrygorii Strashko { 346ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS]; 347ffad5fa0SGrygorii Strashko int type, idx; 348ffad5fa0SGrygorii Strashko 349ffad5fa0SGrygorii Strashko for (idx = 0; idx < priv->data.ale_entries; idx++) { 350ffad5fa0SGrygorii Strashko cpsw_ale_read(priv, idx, ale_entry); 351ffad5fa0SGrygorii Strashko type = cpsw_ale_get_entry_type(ale_entry); 352ffad5fa0SGrygorii Strashko if (type == ALE_TYPE_FREE) 353ffad5fa0SGrygorii Strashko return idx; 354ffad5fa0SGrygorii Strashko } 355ffad5fa0SGrygorii Strashko return -ENOENT; 356ffad5fa0SGrygorii Strashko } 357ffad5fa0SGrygorii Strashko 358ffad5fa0SGrygorii Strashko static int cpsw_ale_find_ageable(struct cpsw_priv *priv) 359ffad5fa0SGrygorii Strashko { 360ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS]; 361ffad5fa0SGrygorii Strashko int type, idx; 362ffad5fa0SGrygorii Strashko 363ffad5fa0SGrygorii Strashko for (idx = 0; idx < priv->data.ale_entries; idx++) { 364ffad5fa0SGrygorii Strashko cpsw_ale_read(priv, idx, ale_entry); 365ffad5fa0SGrygorii Strashko type = cpsw_ale_get_entry_type(ale_entry); 366ffad5fa0SGrygorii Strashko if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 367ffad5fa0SGrygorii Strashko continue; 368ffad5fa0SGrygorii Strashko if (cpsw_ale_get_mcast(ale_entry)) 369ffad5fa0SGrygorii Strashko continue; 370ffad5fa0SGrygorii Strashko type = cpsw_ale_get_ucast_type(ale_entry); 371ffad5fa0SGrygorii Strashko if (type != ALE_UCAST_PERSISTANT && 372ffad5fa0SGrygorii Strashko type != ALE_UCAST_OUI) 373ffad5fa0SGrygorii Strashko return idx; 374ffad5fa0SGrygorii Strashko } 375ffad5fa0SGrygorii Strashko return -ENOENT; 376ffad5fa0SGrygorii Strashko } 377ffad5fa0SGrygorii Strashko 378ffad5fa0SGrygorii Strashko static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr, 379ffad5fa0SGrygorii Strashko int port, int flags) 380ffad5fa0SGrygorii Strashko { 381ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 382ffad5fa0SGrygorii Strashko int idx; 383ffad5fa0SGrygorii Strashko 384ffad5fa0SGrygorii Strashko cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 385ffad5fa0SGrygorii Strashko cpsw_ale_set_addr(ale_entry, addr); 386ffad5fa0SGrygorii Strashko cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 387ffad5fa0SGrygorii Strashko cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 388ffad5fa0SGrygorii Strashko cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 389ffad5fa0SGrygorii Strashko cpsw_ale_set_port_num(ale_entry, port); 390ffad5fa0SGrygorii Strashko 391ffad5fa0SGrygorii Strashko idx = cpsw_ale_match_addr(priv, addr); 392ffad5fa0SGrygorii Strashko if (idx < 0) 393ffad5fa0SGrygorii Strashko idx = cpsw_ale_match_free(priv); 394ffad5fa0SGrygorii Strashko if (idx < 0) 395ffad5fa0SGrygorii Strashko idx = cpsw_ale_find_ageable(priv); 396ffad5fa0SGrygorii Strashko if (idx < 0) 397ffad5fa0SGrygorii Strashko return -ENOMEM; 398ffad5fa0SGrygorii Strashko 399ffad5fa0SGrygorii Strashko cpsw_ale_write(priv, idx, ale_entry); 400ffad5fa0SGrygorii Strashko return 0; 401ffad5fa0SGrygorii Strashko } 402ffad5fa0SGrygorii Strashko 403ffad5fa0SGrygorii Strashko static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr, 404ffad5fa0SGrygorii Strashko int port_mask) 405ffad5fa0SGrygorii Strashko { 406ffad5fa0SGrygorii Strashko u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 407ffad5fa0SGrygorii Strashko int idx, mask; 408ffad5fa0SGrygorii Strashko 409ffad5fa0SGrygorii Strashko idx = cpsw_ale_match_addr(priv, addr); 410ffad5fa0SGrygorii Strashko if (idx >= 0) 411ffad5fa0SGrygorii Strashko cpsw_ale_read(priv, idx, ale_entry); 412ffad5fa0SGrygorii Strashko 413ffad5fa0SGrygorii Strashko cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 414ffad5fa0SGrygorii Strashko cpsw_ale_set_addr(ale_entry, addr); 415ffad5fa0SGrygorii Strashko cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2); 416ffad5fa0SGrygorii Strashko 417ffad5fa0SGrygorii Strashko mask = cpsw_ale_get_port_mask(ale_entry); 418ffad5fa0SGrygorii Strashko port_mask |= mask; 419ffad5fa0SGrygorii Strashko cpsw_ale_set_port_mask(ale_entry, port_mask); 420ffad5fa0SGrygorii Strashko 421ffad5fa0SGrygorii Strashko if (idx < 0) 422ffad5fa0SGrygorii Strashko idx = cpsw_ale_match_free(priv); 423ffad5fa0SGrygorii Strashko if (idx < 0) 424ffad5fa0SGrygorii Strashko idx = cpsw_ale_find_ageable(priv); 425ffad5fa0SGrygorii Strashko if (idx < 0) 426ffad5fa0SGrygorii Strashko return -ENOMEM; 427ffad5fa0SGrygorii Strashko 428ffad5fa0SGrygorii Strashko cpsw_ale_write(priv, idx, ale_entry); 429ffad5fa0SGrygorii Strashko return 0; 430ffad5fa0SGrygorii Strashko } 431ffad5fa0SGrygorii Strashko 432ffad5fa0SGrygorii Strashko static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val) 433ffad5fa0SGrygorii Strashko { 434ffad5fa0SGrygorii Strashko u32 tmp, mask = BIT(bit); 435ffad5fa0SGrygorii Strashko 436ffad5fa0SGrygorii Strashko tmp = __raw_readl(priv->ale_regs + ALE_CONTROL); 437ffad5fa0SGrygorii Strashko tmp &= ~mask; 438ffad5fa0SGrygorii Strashko tmp |= val ? mask : 0; 439ffad5fa0SGrygorii Strashko __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); 440ffad5fa0SGrygorii Strashko } 441ffad5fa0SGrygorii Strashko 442ffad5fa0SGrygorii Strashko #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val) 443ffad5fa0SGrygorii Strashko #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val) 444ffad5fa0SGrygorii Strashko #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val) 445ffad5fa0SGrygorii Strashko 446ffad5fa0SGrygorii Strashko static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, 447ffad5fa0SGrygorii Strashko int val) 448ffad5fa0SGrygorii Strashko { 449ffad5fa0SGrygorii Strashko int offset = ALE_PORTCTL + 4 * port; 450ffad5fa0SGrygorii Strashko u32 tmp, mask = 0x3; 451ffad5fa0SGrygorii Strashko 452ffad5fa0SGrygorii Strashko tmp = __raw_readl(priv->ale_regs + offset); 453ffad5fa0SGrygorii Strashko tmp &= ~mask; 454ffad5fa0SGrygorii Strashko tmp |= val & mask; 455ffad5fa0SGrygorii Strashko __raw_writel(tmp, priv->ale_regs + offset); 456ffad5fa0SGrygorii Strashko } 457ffad5fa0SGrygorii Strashko 458ffad5fa0SGrygorii Strashko /* Set a self-clearing bit in a register, and wait for it to clear */ 459ffad5fa0SGrygorii Strashko static inline void setbit_and_wait_for_clear32(void *addr) 460ffad5fa0SGrygorii Strashko { 461ffad5fa0SGrygorii Strashko __raw_writel(CLEAR_BIT, addr); 462ffad5fa0SGrygorii Strashko while (__raw_readl(addr) & CLEAR_BIT) 463ffad5fa0SGrygorii Strashko ; 464ffad5fa0SGrygorii Strashko } 465ffad5fa0SGrygorii Strashko 466ffad5fa0SGrygorii Strashko #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 467ffad5fa0SGrygorii Strashko ((mac)[2] << 16) | ((mac)[3] << 24)) 468ffad5fa0SGrygorii Strashko #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 469ffad5fa0SGrygorii Strashko 470ffad5fa0SGrygorii Strashko static void cpsw_set_slave_mac(struct cpsw_slave *slave, 471ffad5fa0SGrygorii Strashko struct cpsw_priv *priv) 472ffad5fa0SGrygorii Strashko { 473ffad5fa0SGrygorii Strashko #ifdef CONFIG_DM_ETH 474ffad5fa0SGrygorii Strashko struct eth_pdata *pdata = dev_get_platdata(priv->dev); 475ffad5fa0SGrygorii Strashko 476ffad5fa0SGrygorii Strashko writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi); 477ffad5fa0SGrygorii Strashko writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo); 478ffad5fa0SGrygorii Strashko #else 479ffad5fa0SGrygorii Strashko __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi); 480ffad5fa0SGrygorii Strashko __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); 481ffad5fa0SGrygorii Strashko #endif 482ffad5fa0SGrygorii Strashko } 483ffad5fa0SGrygorii Strashko 484ffad5fa0SGrygorii Strashko static int cpsw_slave_update_link(struct cpsw_slave *slave, 485ffad5fa0SGrygorii Strashko struct cpsw_priv *priv, int *link) 486ffad5fa0SGrygorii Strashko { 487ffad5fa0SGrygorii Strashko struct phy_device *phy; 488ffad5fa0SGrygorii Strashko u32 mac_control = 0; 489ffad5fa0SGrygorii Strashko int ret = -ENODEV; 490ffad5fa0SGrygorii Strashko 491ffad5fa0SGrygorii Strashko phy = priv->phydev; 492ffad5fa0SGrygorii Strashko if (!phy) 493ffad5fa0SGrygorii Strashko goto out; 494ffad5fa0SGrygorii Strashko 495ffad5fa0SGrygorii Strashko ret = phy_startup(phy); 496ffad5fa0SGrygorii Strashko if (ret) 497ffad5fa0SGrygorii Strashko goto out; 498ffad5fa0SGrygorii Strashko 499ffad5fa0SGrygorii Strashko if (link) 500ffad5fa0SGrygorii Strashko *link = phy->link; 501ffad5fa0SGrygorii Strashko 502ffad5fa0SGrygorii Strashko if (phy->link) { /* link up */ 503ffad5fa0SGrygorii Strashko mac_control = priv->data.mac_control; 504ffad5fa0SGrygorii Strashko if (phy->speed == 1000) 505ffad5fa0SGrygorii Strashko mac_control |= GIGABITEN; 506ffad5fa0SGrygorii Strashko if (phy->duplex == DUPLEX_FULL) 507ffad5fa0SGrygorii Strashko mac_control |= FULLDUPLEXEN; 508ffad5fa0SGrygorii Strashko if (phy->speed == 100) 509ffad5fa0SGrygorii Strashko mac_control |= MIIEN; 510ffad5fa0SGrygorii Strashko } 511ffad5fa0SGrygorii Strashko 512ffad5fa0SGrygorii Strashko if (mac_control == slave->mac_control) 513ffad5fa0SGrygorii Strashko goto out; 514ffad5fa0SGrygorii Strashko 515ffad5fa0SGrygorii Strashko if (mac_control) { 516ffad5fa0SGrygorii Strashko printf("link up on port %d, speed %d, %s duplex\n", 517ffad5fa0SGrygorii Strashko slave->slave_num, phy->speed, 518ffad5fa0SGrygorii Strashko (phy->duplex == DUPLEX_FULL) ? "full" : "half"); 519ffad5fa0SGrygorii Strashko } else { 520ffad5fa0SGrygorii Strashko printf("link down on port %d\n", slave->slave_num); 521ffad5fa0SGrygorii Strashko } 522ffad5fa0SGrygorii Strashko 523ffad5fa0SGrygorii Strashko __raw_writel(mac_control, &slave->sliver->mac_control); 524ffad5fa0SGrygorii Strashko slave->mac_control = mac_control; 525ffad5fa0SGrygorii Strashko 526ffad5fa0SGrygorii Strashko out: 527ffad5fa0SGrygorii Strashko return ret; 528ffad5fa0SGrygorii Strashko } 529ffad5fa0SGrygorii Strashko 530ffad5fa0SGrygorii Strashko static int cpsw_update_link(struct cpsw_priv *priv) 531ffad5fa0SGrygorii Strashko { 532ffad5fa0SGrygorii Strashko int ret = -ENODEV; 533ffad5fa0SGrygorii Strashko struct cpsw_slave *slave; 534ffad5fa0SGrygorii Strashko 535ffad5fa0SGrygorii Strashko for_active_slave(slave, priv) 536ffad5fa0SGrygorii Strashko ret = cpsw_slave_update_link(slave, priv, NULL); 537ffad5fa0SGrygorii Strashko 538ffad5fa0SGrygorii Strashko return ret; 539ffad5fa0SGrygorii Strashko } 540ffad5fa0SGrygorii Strashko 541ffad5fa0SGrygorii Strashko static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 542ffad5fa0SGrygorii Strashko { 543ffad5fa0SGrygorii Strashko if (priv->host_port == 0) 544ffad5fa0SGrygorii Strashko return slave_num + 1; 545ffad5fa0SGrygorii Strashko else 546ffad5fa0SGrygorii Strashko return slave_num; 547ffad5fa0SGrygorii Strashko } 548ffad5fa0SGrygorii Strashko 549ffad5fa0SGrygorii Strashko static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) 550ffad5fa0SGrygorii Strashko { 551ffad5fa0SGrygorii Strashko u32 slave_port; 552ffad5fa0SGrygorii Strashko 553ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(&slave->sliver->soft_reset); 554ffad5fa0SGrygorii Strashko 555ffad5fa0SGrygorii Strashko /* setup priority mapping */ 556ffad5fa0SGrygorii Strashko __raw_writel(0x76543210, &slave->sliver->rx_pri_map); 557ffad5fa0SGrygorii Strashko __raw_writel(0x33221100, &slave->regs->tx_pri_map); 558ffad5fa0SGrygorii Strashko 559ffad5fa0SGrygorii Strashko /* setup max packet size, and mac address */ 560ffad5fa0SGrygorii Strashko __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen); 561ffad5fa0SGrygorii Strashko cpsw_set_slave_mac(slave, priv); 562ffad5fa0SGrygorii Strashko 563ffad5fa0SGrygorii Strashko slave->mac_control = 0; /* no link yet */ 564ffad5fa0SGrygorii Strashko 565ffad5fa0SGrygorii Strashko /* enable forwarding */ 566ffad5fa0SGrygorii Strashko slave_port = cpsw_get_slave_port(priv, slave->slave_num); 567ffad5fa0SGrygorii Strashko cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); 568ffad5fa0SGrygorii Strashko 569ffad5fa0SGrygorii Strashko cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port); 570ffad5fa0SGrygorii Strashko 571ffad5fa0SGrygorii Strashko priv->phy_mask |= 1 << slave->data->phy_addr; 572ffad5fa0SGrygorii Strashko } 573ffad5fa0SGrygorii Strashko 574ffad5fa0SGrygorii Strashko static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) 575ffad5fa0SGrygorii Strashko { 576ffad5fa0SGrygorii Strashko struct cpdma_desc *desc = priv->desc_free; 577ffad5fa0SGrygorii Strashko 578ffad5fa0SGrygorii Strashko if (desc) 579ffad5fa0SGrygorii Strashko priv->desc_free = desc_read_ptr(desc, hw_next); 580ffad5fa0SGrygorii Strashko return desc; 581ffad5fa0SGrygorii Strashko } 582ffad5fa0SGrygorii Strashko 583ffad5fa0SGrygorii Strashko static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc) 584ffad5fa0SGrygorii Strashko { 585ffad5fa0SGrygorii Strashko if (desc) { 586ffad5fa0SGrygorii Strashko desc_write(desc, hw_next, priv->desc_free); 587ffad5fa0SGrygorii Strashko priv->desc_free = desc; 588ffad5fa0SGrygorii Strashko } 589ffad5fa0SGrygorii Strashko } 590ffad5fa0SGrygorii Strashko 591ffad5fa0SGrygorii Strashko static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan, 592ffad5fa0SGrygorii Strashko void *buffer, int len) 593ffad5fa0SGrygorii Strashko { 594ffad5fa0SGrygorii Strashko struct cpdma_desc *desc, *prev; 595ffad5fa0SGrygorii Strashko u32 mode; 596ffad5fa0SGrygorii Strashko 597ffad5fa0SGrygorii Strashko desc = cpdma_desc_alloc(priv); 598ffad5fa0SGrygorii Strashko if (!desc) 599ffad5fa0SGrygorii Strashko return -ENOMEM; 600ffad5fa0SGrygorii Strashko 601ffad5fa0SGrygorii Strashko if (len < PKT_MIN) 602ffad5fa0SGrygorii Strashko len = PKT_MIN; 603ffad5fa0SGrygorii Strashko 604ffad5fa0SGrygorii Strashko mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; 605ffad5fa0SGrygorii Strashko 606ffad5fa0SGrygorii Strashko desc_write(desc, hw_next, 0); 607ffad5fa0SGrygorii Strashko desc_write(desc, hw_buffer, buffer); 608ffad5fa0SGrygorii Strashko desc_write(desc, hw_len, len); 609ffad5fa0SGrygorii Strashko desc_write(desc, hw_mode, mode | len); 610ffad5fa0SGrygorii Strashko desc_write(desc, sw_buffer, buffer); 611ffad5fa0SGrygorii Strashko desc_write(desc, sw_len, len); 612ffad5fa0SGrygorii Strashko 613ffad5fa0SGrygorii Strashko if (!chan->head) { 614ffad5fa0SGrygorii Strashko /* simple case - first packet enqueued */ 615ffad5fa0SGrygorii Strashko chan->head = desc; 616ffad5fa0SGrygorii Strashko chan->tail = desc; 617ffad5fa0SGrygorii Strashko chan_write(chan, hdp, desc); 618ffad5fa0SGrygorii Strashko goto done; 619ffad5fa0SGrygorii Strashko } 620ffad5fa0SGrygorii Strashko 621ffad5fa0SGrygorii Strashko /* not the first packet - enqueue at the tail */ 622ffad5fa0SGrygorii Strashko prev = chan->tail; 623ffad5fa0SGrygorii Strashko desc_write(prev, hw_next, desc); 624ffad5fa0SGrygorii Strashko chan->tail = desc; 625ffad5fa0SGrygorii Strashko 626ffad5fa0SGrygorii Strashko /* next check if EOQ has been triggered already */ 627ffad5fa0SGrygorii Strashko if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ) 628ffad5fa0SGrygorii Strashko chan_write(chan, hdp, desc); 629ffad5fa0SGrygorii Strashko 630ffad5fa0SGrygorii Strashko done: 631ffad5fa0SGrygorii Strashko if (chan->rxfree) 632ffad5fa0SGrygorii Strashko chan_write(chan, rxfree, 1); 633ffad5fa0SGrygorii Strashko return 0; 634ffad5fa0SGrygorii Strashko } 635ffad5fa0SGrygorii Strashko 636ffad5fa0SGrygorii Strashko static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, 637ffad5fa0SGrygorii Strashko void **buffer, int *len) 638ffad5fa0SGrygorii Strashko { 639ffad5fa0SGrygorii Strashko struct cpdma_desc *desc = chan->head; 640ffad5fa0SGrygorii Strashko u32 status; 641ffad5fa0SGrygorii Strashko 642ffad5fa0SGrygorii Strashko if (!desc) 643ffad5fa0SGrygorii Strashko return -ENOENT; 644ffad5fa0SGrygorii Strashko 645ffad5fa0SGrygorii Strashko status = desc_read(desc, hw_mode); 646ffad5fa0SGrygorii Strashko 647ffad5fa0SGrygorii Strashko if (len) 648ffad5fa0SGrygorii Strashko *len = status & 0x7ff; 649ffad5fa0SGrygorii Strashko 650ffad5fa0SGrygorii Strashko if (buffer) 651ffad5fa0SGrygorii Strashko *buffer = desc_read_ptr(desc, sw_buffer); 652ffad5fa0SGrygorii Strashko 653ffad5fa0SGrygorii Strashko if (status & CPDMA_DESC_OWNER) { 654ffad5fa0SGrygorii Strashko if (chan_read(chan, hdp) == 0) { 655ffad5fa0SGrygorii Strashko if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER) 656ffad5fa0SGrygorii Strashko chan_write(chan, hdp, desc); 657ffad5fa0SGrygorii Strashko } 658ffad5fa0SGrygorii Strashko 659ffad5fa0SGrygorii Strashko return -EBUSY; 660ffad5fa0SGrygorii Strashko } 661ffad5fa0SGrygorii Strashko 662ffad5fa0SGrygorii Strashko chan->head = desc_read_ptr(desc, hw_next); 663ffad5fa0SGrygorii Strashko chan_write(chan, cp, desc); 664ffad5fa0SGrygorii Strashko 665ffad5fa0SGrygorii Strashko cpdma_desc_free(priv, desc); 666ffad5fa0SGrygorii Strashko return 0; 667ffad5fa0SGrygorii Strashko } 668ffad5fa0SGrygorii Strashko 669ffad5fa0SGrygorii Strashko static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) 670ffad5fa0SGrygorii Strashko { 671ffad5fa0SGrygorii Strashko struct cpsw_slave *slave; 672ffad5fa0SGrygorii Strashko int i, ret; 673ffad5fa0SGrygorii Strashko 674ffad5fa0SGrygorii Strashko /* soft reset the controller and initialize priv */ 675ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(&priv->regs->soft_reset); 676ffad5fa0SGrygorii Strashko 677ffad5fa0SGrygorii Strashko /* initialize and reset the address lookup engine */ 678ffad5fa0SGrygorii Strashko cpsw_ale_enable(priv, 1); 679ffad5fa0SGrygorii Strashko cpsw_ale_clear(priv, 1); 680ffad5fa0SGrygorii Strashko cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */ 681ffad5fa0SGrygorii Strashko 682ffad5fa0SGrygorii Strashko /* setup host port priority mapping */ 683ffad5fa0SGrygorii Strashko __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); 684ffad5fa0SGrygorii Strashko __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 685ffad5fa0SGrygorii Strashko 686ffad5fa0SGrygorii Strashko /* disable priority elevation and enable statistics on all ports */ 687ffad5fa0SGrygorii Strashko __raw_writel(0, &priv->regs->ptype); 688ffad5fa0SGrygorii Strashko 689ffad5fa0SGrygorii Strashko /* enable statistics collection only on the host port */ 690ffad5fa0SGrygorii Strashko __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); 691ffad5fa0SGrygorii Strashko __raw_writel(0x7, &priv->regs->stat_port_en); 692ffad5fa0SGrygorii Strashko 693ffad5fa0SGrygorii Strashko cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); 694ffad5fa0SGrygorii Strashko 695ffad5fa0SGrygorii Strashko cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE); 696ffad5fa0SGrygorii Strashko cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port); 697ffad5fa0SGrygorii Strashko 698ffad5fa0SGrygorii Strashko for_active_slave(slave, priv) 699ffad5fa0SGrygorii Strashko cpsw_slave_init(slave, priv); 700ffad5fa0SGrygorii Strashko 701ffad5fa0SGrygorii Strashko ret = cpsw_update_link(priv); 702ffad5fa0SGrygorii Strashko if (ret) 703ffad5fa0SGrygorii Strashko goto out; 704ffad5fa0SGrygorii Strashko 705ffad5fa0SGrygorii Strashko /* init descriptor pool */ 706ffad5fa0SGrygorii Strashko for (i = 0; i < NUM_DESCS; i++) { 707ffad5fa0SGrygorii Strashko desc_write(&priv->descs[i], hw_next, 708ffad5fa0SGrygorii Strashko (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]); 709ffad5fa0SGrygorii Strashko } 710ffad5fa0SGrygorii Strashko priv->desc_free = &priv->descs[0]; 711ffad5fa0SGrygorii Strashko 712ffad5fa0SGrygorii Strashko /* initialize channels */ 713ffad5fa0SGrygorii Strashko if (priv->data.version == CPSW_CTRL_VERSION_2) { 714ffad5fa0SGrygorii Strashko memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 715ffad5fa0SGrygorii Strashko priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2; 716ffad5fa0SGrygorii Strashko priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2; 717ffad5fa0SGrygorii Strashko priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 718ffad5fa0SGrygorii Strashko 719ffad5fa0SGrygorii Strashko memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 720ffad5fa0SGrygorii Strashko priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2; 721ffad5fa0SGrygorii Strashko priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2; 722ffad5fa0SGrygorii Strashko } else { 723ffad5fa0SGrygorii Strashko memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 724ffad5fa0SGrygorii Strashko priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1; 725ffad5fa0SGrygorii Strashko priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1; 726ffad5fa0SGrygorii Strashko priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 727ffad5fa0SGrygorii Strashko 728ffad5fa0SGrygorii Strashko memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 729ffad5fa0SGrygorii Strashko priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1; 730ffad5fa0SGrygorii Strashko priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1; 731ffad5fa0SGrygorii Strashko } 732ffad5fa0SGrygorii Strashko 733ffad5fa0SGrygorii Strashko /* clear dma state */ 734ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 735ffad5fa0SGrygorii Strashko 736ffad5fa0SGrygorii Strashko if (priv->data.version == CPSW_CTRL_VERSION_2) { 737ffad5fa0SGrygorii Strashko for (i = 0; i < priv->data.channels; i++) { 738ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 739ffad5fa0SGrygorii Strashko * i); 740ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 741ffad5fa0SGrygorii Strashko * i); 742ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 743ffad5fa0SGrygorii Strashko * i); 744ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 745ffad5fa0SGrygorii Strashko * i); 746ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 747ffad5fa0SGrygorii Strashko * i); 748ffad5fa0SGrygorii Strashko } 749ffad5fa0SGrygorii Strashko } else { 750ffad5fa0SGrygorii Strashko for (i = 0; i < priv->data.channels; i++) { 751ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 752ffad5fa0SGrygorii Strashko * i); 753ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 754ffad5fa0SGrygorii Strashko * i); 755ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 756ffad5fa0SGrygorii Strashko * i); 757ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 758ffad5fa0SGrygorii Strashko * i); 759ffad5fa0SGrygorii Strashko __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 760ffad5fa0SGrygorii Strashko * i); 761ffad5fa0SGrygorii Strashko 762ffad5fa0SGrygorii Strashko } 763ffad5fa0SGrygorii Strashko } 764ffad5fa0SGrygorii Strashko 765ffad5fa0SGrygorii Strashko __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL); 766ffad5fa0SGrygorii Strashko __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL); 767ffad5fa0SGrygorii Strashko 768ffad5fa0SGrygorii Strashko /* submit rx descs */ 769ffad5fa0SGrygorii Strashko for (i = 0; i < PKTBUFSRX; i++) { 770ffad5fa0SGrygorii Strashko ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i], 771ffad5fa0SGrygorii Strashko PKTSIZE); 772ffad5fa0SGrygorii Strashko if (ret < 0) { 773ffad5fa0SGrygorii Strashko printf("error %d submitting rx desc\n", ret); 774ffad5fa0SGrygorii Strashko break; 775ffad5fa0SGrygorii Strashko } 776ffad5fa0SGrygorii Strashko } 777ffad5fa0SGrygorii Strashko 778ffad5fa0SGrygorii Strashko out: 779ffad5fa0SGrygorii Strashko return ret; 780ffad5fa0SGrygorii Strashko } 781ffad5fa0SGrygorii Strashko 782ffad5fa0SGrygorii Strashko static int cpsw_reap_completed_packets(struct cpsw_priv *priv) 783ffad5fa0SGrygorii Strashko { 784ffad5fa0SGrygorii Strashko int timeout = CPDMA_TIMEOUT; 785ffad5fa0SGrygorii Strashko 786ffad5fa0SGrygorii Strashko /* reap completed packets */ 787ffad5fa0SGrygorii Strashko while (timeout-- && 788ffad5fa0SGrygorii Strashko (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0)) 789ffad5fa0SGrygorii Strashko ; 790ffad5fa0SGrygorii Strashko 791ffad5fa0SGrygorii Strashko return timeout; 792ffad5fa0SGrygorii Strashko } 793ffad5fa0SGrygorii Strashko 794ffad5fa0SGrygorii Strashko static void _cpsw_halt(struct cpsw_priv *priv) 795ffad5fa0SGrygorii Strashko { 796ffad5fa0SGrygorii Strashko cpsw_reap_completed_packets(priv); 797ffad5fa0SGrygorii Strashko 798ffad5fa0SGrygorii Strashko writel(0, priv->dma_regs + CPDMA_TXCONTROL); 799ffad5fa0SGrygorii Strashko writel(0, priv->dma_regs + CPDMA_RXCONTROL); 800ffad5fa0SGrygorii Strashko 801ffad5fa0SGrygorii Strashko /* soft reset the controller and initialize priv */ 802ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(&priv->regs->soft_reset); 803ffad5fa0SGrygorii Strashko 804ffad5fa0SGrygorii Strashko /* clear dma state */ 805ffad5fa0SGrygorii Strashko setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 806ffad5fa0SGrygorii Strashko 807ffad5fa0SGrygorii Strashko } 808ffad5fa0SGrygorii Strashko 809ffad5fa0SGrygorii Strashko static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) 810ffad5fa0SGrygorii Strashko { 811ffad5fa0SGrygorii Strashko int timeout; 812ffad5fa0SGrygorii Strashko 813ffad5fa0SGrygorii Strashko flush_dcache_range((unsigned long)packet, 814ffad5fa0SGrygorii Strashko (unsigned long)packet + ALIGN(length, PKTALIGN)); 815ffad5fa0SGrygorii Strashko 816ffad5fa0SGrygorii Strashko timeout = cpsw_reap_completed_packets(priv); 817ffad5fa0SGrygorii Strashko if (timeout == -1) { 818ffad5fa0SGrygorii Strashko printf("cpdma_process timeout\n"); 819ffad5fa0SGrygorii Strashko return -ETIMEDOUT; 820ffad5fa0SGrygorii Strashko } 821ffad5fa0SGrygorii Strashko 822ffad5fa0SGrygorii Strashko return cpdma_submit(priv, &priv->tx_chan, packet, length); 823ffad5fa0SGrygorii Strashko } 824ffad5fa0SGrygorii Strashko 825ffad5fa0SGrygorii Strashko static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt) 826ffad5fa0SGrygorii Strashko { 827ffad5fa0SGrygorii Strashko void *buffer; 828ffad5fa0SGrygorii Strashko int len; 829ffad5fa0SGrygorii Strashko int ret; 830ffad5fa0SGrygorii Strashko 831ffad5fa0SGrygorii Strashko ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len); 832ffad5fa0SGrygorii Strashko if (ret < 0) 833ffad5fa0SGrygorii Strashko return ret; 834ffad5fa0SGrygorii Strashko 835ffad5fa0SGrygorii Strashko invalidate_dcache_range((unsigned long)buffer, 836ffad5fa0SGrygorii Strashko (unsigned long)buffer + PKTSIZE_ALIGN); 837ffad5fa0SGrygorii Strashko *pkt = buffer; 838ffad5fa0SGrygorii Strashko 839ffad5fa0SGrygorii Strashko return len; 840ffad5fa0SGrygorii Strashko } 841ffad5fa0SGrygorii Strashko 842ffad5fa0SGrygorii Strashko static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, 843ffad5fa0SGrygorii Strashko struct cpsw_priv *priv) 844ffad5fa0SGrygorii Strashko { 845ffad5fa0SGrygorii Strashko void *regs = priv->regs; 846ffad5fa0SGrygorii Strashko struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 847ffad5fa0SGrygorii Strashko slave->slave_num = slave_num; 848ffad5fa0SGrygorii Strashko slave->data = data; 849ffad5fa0SGrygorii Strashko slave->regs = regs + data->slave_reg_ofs; 850ffad5fa0SGrygorii Strashko slave->sliver = regs + data->sliver_reg_ofs; 851ffad5fa0SGrygorii Strashko } 852ffad5fa0SGrygorii Strashko 853ffad5fa0SGrygorii Strashko static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) 854ffad5fa0SGrygorii Strashko { 855ffad5fa0SGrygorii Strashko struct phy_device *phydev; 856ffad5fa0SGrygorii Strashko u32 supported = PHY_GBIT_FEATURES; 857ffad5fa0SGrygorii Strashko 858ffad5fa0SGrygorii Strashko phydev = phy_connect(priv->bus, 859ffad5fa0SGrygorii Strashko slave->data->phy_addr, 860ffad5fa0SGrygorii Strashko priv->dev, 861ffad5fa0SGrygorii Strashko slave->data->phy_if); 862ffad5fa0SGrygorii Strashko 863ffad5fa0SGrygorii Strashko if (!phydev) 864ffad5fa0SGrygorii Strashko return -1; 865ffad5fa0SGrygorii Strashko 866ffad5fa0SGrygorii Strashko phydev->supported &= supported; 867ffad5fa0SGrygorii Strashko phydev->advertising = phydev->supported; 868ffad5fa0SGrygorii Strashko 869ffad5fa0SGrygorii Strashko #ifdef CONFIG_DM_ETH 870ffad5fa0SGrygorii Strashko if (slave->data->phy_of_handle) 871ffad5fa0SGrygorii Strashko phydev->node = offset_to_ofnode(slave->data->phy_of_handle); 872ffad5fa0SGrygorii Strashko #endif 873ffad5fa0SGrygorii Strashko 874ffad5fa0SGrygorii Strashko priv->phydev = phydev; 875ffad5fa0SGrygorii Strashko phy_config(phydev); 876ffad5fa0SGrygorii Strashko 877ffad5fa0SGrygorii Strashko return 1; 878ffad5fa0SGrygorii Strashko } 879ffad5fa0SGrygorii Strashko 880ffad5fa0SGrygorii Strashko static void cpsw_phy_addr_update(struct cpsw_priv *priv) 881ffad5fa0SGrygorii Strashko { 882ffad5fa0SGrygorii Strashko struct cpsw_platform_data *data = &priv->data; 883*4f41cd9aSGrygorii Strashko u16 alive = cpsw_mdio_get_alive(priv->bus); 884ffad5fa0SGrygorii Strashko int active = data->active_slave; 885ffad5fa0SGrygorii Strashko int new_addr = ffs(alive) - 1; 886ffad5fa0SGrygorii Strashko 887ffad5fa0SGrygorii Strashko /* 888ffad5fa0SGrygorii Strashko * If there is only one phy alive and its address does not match 889ffad5fa0SGrygorii Strashko * that of active slave, then phy address can safely be updated. 890ffad5fa0SGrygorii Strashko */ 891ffad5fa0SGrygorii Strashko if (hweight16(alive) == 1 && 892ffad5fa0SGrygorii Strashko data->slave_data[active].phy_addr != new_addr) { 893ffad5fa0SGrygorii Strashko printf("Updated phy address for CPSW#%d, old: %d, new: %d\n", 894ffad5fa0SGrygorii Strashko active, data->slave_data[active].phy_addr, new_addr); 895ffad5fa0SGrygorii Strashko data->slave_data[active].phy_addr = new_addr; 896ffad5fa0SGrygorii Strashko } 897ffad5fa0SGrygorii Strashko } 898ffad5fa0SGrygorii Strashko 899ffad5fa0SGrygorii Strashko int _cpsw_register(struct cpsw_priv *priv) 900ffad5fa0SGrygorii Strashko { 901ffad5fa0SGrygorii Strashko struct cpsw_slave *slave; 902ffad5fa0SGrygorii Strashko struct cpsw_platform_data *data = &priv->data; 903ffad5fa0SGrygorii Strashko void *regs = (void *)data->cpsw_base; 904ffad5fa0SGrygorii Strashko 905ffad5fa0SGrygorii Strashko priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); 906ffad5fa0SGrygorii Strashko if (!priv->slaves) { 907ffad5fa0SGrygorii Strashko return -ENOMEM; 908ffad5fa0SGrygorii Strashko } 909ffad5fa0SGrygorii Strashko 910ffad5fa0SGrygorii Strashko priv->host_port = data->host_port_num; 911ffad5fa0SGrygorii Strashko priv->regs = regs; 912ffad5fa0SGrygorii Strashko priv->host_port_regs = regs + data->host_port_reg_ofs; 913ffad5fa0SGrygorii Strashko priv->dma_regs = regs + data->cpdma_reg_ofs; 914ffad5fa0SGrygorii Strashko priv->ale_regs = regs + data->ale_reg_ofs; 915ffad5fa0SGrygorii Strashko priv->descs = (void *)regs + data->bd_ram_ofs; 916ffad5fa0SGrygorii Strashko 917ffad5fa0SGrygorii Strashko int idx = 0; 918ffad5fa0SGrygorii Strashko 919ffad5fa0SGrygorii Strashko for_each_slave(slave, priv) { 920ffad5fa0SGrygorii Strashko cpsw_slave_setup(slave, idx, priv); 921ffad5fa0SGrygorii Strashko idx = idx + 1; 922ffad5fa0SGrygorii Strashko } 923ffad5fa0SGrygorii Strashko 924*4f41cd9aSGrygorii Strashko priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0); 925*4f41cd9aSGrygorii Strashko if (!priv->bus) 926*4f41cd9aSGrygorii Strashko return -EFAULT; 927ffad5fa0SGrygorii Strashko 928ffad5fa0SGrygorii Strashko cpsw_phy_addr_update(priv); 929ffad5fa0SGrygorii Strashko 930ffad5fa0SGrygorii Strashko for_active_slave(slave, priv) 931ffad5fa0SGrygorii Strashko cpsw_phy_init(priv, slave); 932ffad5fa0SGrygorii Strashko 933ffad5fa0SGrygorii Strashko return 0; 934ffad5fa0SGrygorii Strashko } 935ffad5fa0SGrygorii Strashko 936ffad5fa0SGrygorii Strashko #ifndef CONFIG_DM_ETH 937ffad5fa0SGrygorii Strashko static int cpsw_init(struct eth_device *dev, bd_t *bis) 938ffad5fa0SGrygorii Strashko { 939ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev->priv; 940ffad5fa0SGrygorii Strashko 941ffad5fa0SGrygorii Strashko return _cpsw_init(priv, dev->enetaddr); 942ffad5fa0SGrygorii Strashko } 943ffad5fa0SGrygorii Strashko 944ffad5fa0SGrygorii Strashko static void cpsw_halt(struct eth_device *dev) 945ffad5fa0SGrygorii Strashko { 946ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev->priv; 947ffad5fa0SGrygorii Strashko 948ffad5fa0SGrygorii Strashko return _cpsw_halt(priv); 949ffad5fa0SGrygorii Strashko } 950ffad5fa0SGrygorii Strashko 951ffad5fa0SGrygorii Strashko static int cpsw_send(struct eth_device *dev, void *packet, int length) 952ffad5fa0SGrygorii Strashko { 953ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev->priv; 954ffad5fa0SGrygorii Strashko 955ffad5fa0SGrygorii Strashko return _cpsw_send(priv, packet, length); 956ffad5fa0SGrygorii Strashko } 957ffad5fa0SGrygorii Strashko 958ffad5fa0SGrygorii Strashko static int cpsw_recv(struct eth_device *dev) 959ffad5fa0SGrygorii Strashko { 960ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev->priv; 961ffad5fa0SGrygorii Strashko uchar *pkt = NULL; 962ffad5fa0SGrygorii Strashko int len; 963ffad5fa0SGrygorii Strashko 964ffad5fa0SGrygorii Strashko len = _cpsw_recv(priv, &pkt); 965ffad5fa0SGrygorii Strashko 966ffad5fa0SGrygorii Strashko if (len > 0) { 967ffad5fa0SGrygorii Strashko net_process_received_packet(pkt, len); 968ffad5fa0SGrygorii Strashko cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE); 969ffad5fa0SGrygorii Strashko } 970ffad5fa0SGrygorii Strashko 971ffad5fa0SGrygorii Strashko return len; 972ffad5fa0SGrygorii Strashko } 973ffad5fa0SGrygorii Strashko 974ffad5fa0SGrygorii Strashko int cpsw_register(struct cpsw_platform_data *data) 975ffad5fa0SGrygorii Strashko { 976ffad5fa0SGrygorii Strashko struct cpsw_priv *priv; 977ffad5fa0SGrygorii Strashko struct eth_device *dev; 978ffad5fa0SGrygorii Strashko int ret; 979ffad5fa0SGrygorii Strashko 980ffad5fa0SGrygorii Strashko dev = calloc(sizeof(*dev), 1); 981ffad5fa0SGrygorii Strashko if (!dev) 982ffad5fa0SGrygorii Strashko return -ENOMEM; 983ffad5fa0SGrygorii Strashko 984ffad5fa0SGrygorii Strashko priv = calloc(sizeof(*priv), 1); 985ffad5fa0SGrygorii Strashko if (!priv) { 986ffad5fa0SGrygorii Strashko free(dev); 987ffad5fa0SGrygorii Strashko return -ENOMEM; 988ffad5fa0SGrygorii Strashko } 989ffad5fa0SGrygorii Strashko 990ffad5fa0SGrygorii Strashko priv->dev = dev; 991ffad5fa0SGrygorii Strashko priv->data = *data; 992ffad5fa0SGrygorii Strashko 993ffad5fa0SGrygorii Strashko strcpy(dev->name, "cpsw"); 994ffad5fa0SGrygorii Strashko dev->iobase = 0; 995ffad5fa0SGrygorii Strashko dev->init = cpsw_init; 996ffad5fa0SGrygorii Strashko dev->halt = cpsw_halt; 997ffad5fa0SGrygorii Strashko dev->send = cpsw_send; 998ffad5fa0SGrygorii Strashko dev->recv = cpsw_recv; 999ffad5fa0SGrygorii Strashko dev->priv = priv; 1000ffad5fa0SGrygorii Strashko 1001ffad5fa0SGrygorii Strashko eth_register(dev); 1002ffad5fa0SGrygorii Strashko 1003ffad5fa0SGrygorii Strashko ret = _cpsw_register(priv); 1004ffad5fa0SGrygorii Strashko if (ret < 0) { 1005ffad5fa0SGrygorii Strashko eth_unregister(dev); 1006ffad5fa0SGrygorii Strashko free(dev); 1007ffad5fa0SGrygorii Strashko free(priv); 1008ffad5fa0SGrygorii Strashko return ret; 1009ffad5fa0SGrygorii Strashko } 1010ffad5fa0SGrygorii Strashko 1011ffad5fa0SGrygorii Strashko return 1; 1012ffad5fa0SGrygorii Strashko } 1013ffad5fa0SGrygorii Strashko #else 1014ffad5fa0SGrygorii Strashko static int cpsw_eth_start(struct udevice *dev) 1015ffad5fa0SGrygorii Strashko { 1016ffad5fa0SGrygorii Strashko struct eth_pdata *pdata = dev_get_platdata(dev); 1017ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1018ffad5fa0SGrygorii Strashko 1019ffad5fa0SGrygorii Strashko return _cpsw_init(priv, pdata->enetaddr); 1020ffad5fa0SGrygorii Strashko } 1021ffad5fa0SGrygorii Strashko 1022ffad5fa0SGrygorii Strashko static int cpsw_eth_send(struct udevice *dev, void *packet, int length) 1023ffad5fa0SGrygorii Strashko { 1024ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1025ffad5fa0SGrygorii Strashko 1026ffad5fa0SGrygorii Strashko return _cpsw_send(priv, packet, length); 1027ffad5fa0SGrygorii Strashko } 1028ffad5fa0SGrygorii Strashko 1029ffad5fa0SGrygorii Strashko static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp) 1030ffad5fa0SGrygorii Strashko { 1031ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1032ffad5fa0SGrygorii Strashko 1033ffad5fa0SGrygorii Strashko return _cpsw_recv(priv, packetp); 1034ffad5fa0SGrygorii Strashko } 1035ffad5fa0SGrygorii Strashko 1036ffad5fa0SGrygorii Strashko static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet, 1037ffad5fa0SGrygorii Strashko int length) 1038ffad5fa0SGrygorii Strashko { 1039ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1040ffad5fa0SGrygorii Strashko 1041ffad5fa0SGrygorii Strashko return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE); 1042ffad5fa0SGrygorii Strashko } 1043ffad5fa0SGrygorii Strashko 1044ffad5fa0SGrygorii Strashko static void cpsw_eth_stop(struct udevice *dev) 1045ffad5fa0SGrygorii Strashko { 1046ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1047ffad5fa0SGrygorii Strashko 1048ffad5fa0SGrygorii Strashko return _cpsw_halt(priv); 1049ffad5fa0SGrygorii Strashko } 1050ffad5fa0SGrygorii Strashko 1051ffad5fa0SGrygorii Strashko 1052ffad5fa0SGrygorii Strashko static int cpsw_eth_probe(struct udevice *dev) 1053ffad5fa0SGrygorii Strashko { 1054ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1055ffad5fa0SGrygorii Strashko 1056ffad5fa0SGrygorii Strashko priv->dev = dev; 1057ffad5fa0SGrygorii Strashko 1058ffad5fa0SGrygorii Strashko return _cpsw_register(priv); 1059ffad5fa0SGrygorii Strashko } 1060ffad5fa0SGrygorii Strashko 1061ffad5fa0SGrygorii Strashko static const struct eth_ops cpsw_eth_ops = { 1062ffad5fa0SGrygorii Strashko .start = cpsw_eth_start, 1063ffad5fa0SGrygorii Strashko .send = cpsw_eth_send, 1064ffad5fa0SGrygorii Strashko .recv = cpsw_eth_recv, 1065ffad5fa0SGrygorii Strashko .free_pkt = cpsw_eth_free_pkt, 1066ffad5fa0SGrygorii Strashko .stop = cpsw_eth_stop, 1067ffad5fa0SGrygorii Strashko }; 1068ffad5fa0SGrygorii Strashko 1069ffad5fa0SGrygorii Strashko static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node) 1070ffad5fa0SGrygorii Strashko { 1071ffad5fa0SGrygorii Strashko return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL, 1072ffad5fa0SGrygorii Strashko false); 1073ffad5fa0SGrygorii Strashko } 1074ffad5fa0SGrygorii Strashko 1075ffad5fa0SGrygorii Strashko static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv, 1076ffad5fa0SGrygorii Strashko phy_interface_t phy_mode) 1077ffad5fa0SGrygorii Strashko { 1078ffad5fa0SGrygorii Strashko u32 reg; 1079ffad5fa0SGrygorii Strashko u32 mask; 1080ffad5fa0SGrygorii Strashko u32 mode = 0; 1081ffad5fa0SGrygorii Strashko bool rgmii_id = false; 1082ffad5fa0SGrygorii Strashko int slave = priv->data.active_slave; 1083ffad5fa0SGrygorii Strashko 1084ffad5fa0SGrygorii Strashko reg = readl(priv->data.gmii_sel); 1085ffad5fa0SGrygorii Strashko 1086ffad5fa0SGrygorii Strashko switch (phy_mode) { 1087ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RMII: 1088ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RMII; 1089ffad5fa0SGrygorii Strashko break; 1090ffad5fa0SGrygorii Strashko 1091ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII: 1092ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RGMII; 1093ffad5fa0SGrygorii Strashko break; 1094ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_ID: 1095ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_RXID: 1096ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_TXID: 1097ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RGMII; 1098ffad5fa0SGrygorii Strashko rgmii_id = true; 1099ffad5fa0SGrygorii Strashko break; 1100ffad5fa0SGrygorii Strashko 1101ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_MII: 1102ffad5fa0SGrygorii Strashko default: 1103ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_MII; 1104ffad5fa0SGrygorii Strashko break; 1105ffad5fa0SGrygorii Strashko }; 1106ffad5fa0SGrygorii Strashko 1107ffad5fa0SGrygorii Strashko mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6); 1108ffad5fa0SGrygorii Strashko mode <<= slave * 2; 1109ffad5fa0SGrygorii Strashko 1110ffad5fa0SGrygorii Strashko if (priv->data.rmii_clock_external) { 1111ffad5fa0SGrygorii Strashko if (slave == 0) 1112ffad5fa0SGrygorii Strashko mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN; 1113ffad5fa0SGrygorii Strashko else 1114ffad5fa0SGrygorii Strashko mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN; 1115ffad5fa0SGrygorii Strashko } 1116ffad5fa0SGrygorii Strashko 1117ffad5fa0SGrygorii Strashko if (rgmii_id) { 1118ffad5fa0SGrygorii Strashko if (slave == 0) 1119ffad5fa0SGrygorii Strashko mode |= AM33XX_GMII_SEL_RGMII1_IDMODE; 1120ffad5fa0SGrygorii Strashko else 1121ffad5fa0SGrygorii Strashko mode |= AM33XX_GMII_SEL_RGMII2_IDMODE; 1122ffad5fa0SGrygorii Strashko } 1123ffad5fa0SGrygorii Strashko 1124ffad5fa0SGrygorii Strashko reg &= ~mask; 1125ffad5fa0SGrygorii Strashko reg |= mode; 1126ffad5fa0SGrygorii Strashko 1127ffad5fa0SGrygorii Strashko writel(reg, priv->data.gmii_sel); 1128ffad5fa0SGrygorii Strashko } 1129ffad5fa0SGrygorii Strashko 1130ffad5fa0SGrygorii Strashko static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv, 1131ffad5fa0SGrygorii Strashko phy_interface_t phy_mode) 1132ffad5fa0SGrygorii Strashko { 1133ffad5fa0SGrygorii Strashko u32 reg; 1134ffad5fa0SGrygorii Strashko u32 mask; 1135ffad5fa0SGrygorii Strashko u32 mode = 0; 1136ffad5fa0SGrygorii Strashko int slave = priv->data.active_slave; 1137ffad5fa0SGrygorii Strashko 1138ffad5fa0SGrygorii Strashko reg = readl(priv->data.gmii_sel); 1139ffad5fa0SGrygorii Strashko 1140ffad5fa0SGrygorii Strashko switch (phy_mode) { 1141ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RMII: 1142ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RMII; 1143ffad5fa0SGrygorii Strashko break; 1144ffad5fa0SGrygorii Strashko 1145ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII: 1146ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_ID: 1147ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_RXID: 1148ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_RGMII_TXID: 1149ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_RGMII; 1150ffad5fa0SGrygorii Strashko break; 1151ffad5fa0SGrygorii Strashko 1152ffad5fa0SGrygorii Strashko case PHY_INTERFACE_MODE_MII: 1153ffad5fa0SGrygorii Strashko default: 1154ffad5fa0SGrygorii Strashko mode = AM33XX_GMII_SEL_MODE_MII; 1155ffad5fa0SGrygorii Strashko break; 1156ffad5fa0SGrygorii Strashko }; 1157ffad5fa0SGrygorii Strashko 1158ffad5fa0SGrygorii Strashko switch (slave) { 1159ffad5fa0SGrygorii Strashko case 0: 1160ffad5fa0SGrygorii Strashko mask = GMII_SEL_MODE_MASK; 1161ffad5fa0SGrygorii Strashko break; 1162ffad5fa0SGrygorii Strashko case 1: 1163ffad5fa0SGrygorii Strashko mask = GMII_SEL_MODE_MASK << 4; 1164ffad5fa0SGrygorii Strashko mode <<= 4; 1165ffad5fa0SGrygorii Strashko break; 1166ffad5fa0SGrygorii Strashko default: 1167ffad5fa0SGrygorii Strashko dev_err(priv->dev, "invalid slave number...\n"); 1168ffad5fa0SGrygorii Strashko return; 1169ffad5fa0SGrygorii Strashko } 1170ffad5fa0SGrygorii Strashko 1171ffad5fa0SGrygorii Strashko if (priv->data.rmii_clock_external) 1172ffad5fa0SGrygorii Strashko dev_err(priv->dev, "RMII External clock is not supported\n"); 1173ffad5fa0SGrygorii Strashko 1174ffad5fa0SGrygorii Strashko reg &= ~mask; 1175ffad5fa0SGrygorii Strashko reg |= mode; 1176ffad5fa0SGrygorii Strashko 1177ffad5fa0SGrygorii Strashko writel(reg, priv->data.gmii_sel); 1178ffad5fa0SGrygorii Strashko } 1179ffad5fa0SGrygorii Strashko 1180ffad5fa0SGrygorii Strashko static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat, 1181ffad5fa0SGrygorii Strashko phy_interface_t phy_mode) 1182ffad5fa0SGrygorii Strashko { 1183ffad5fa0SGrygorii Strashko if (!strcmp(compat, "ti,am3352-cpsw-phy-sel")) 1184ffad5fa0SGrygorii Strashko cpsw_gmii_sel_am3352(priv, phy_mode); 1185ffad5fa0SGrygorii Strashko if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel")) 1186ffad5fa0SGrygorii Strashko cpsw_gmii_sel_am3352(priv, phy_mode); 1187ffad5fa0SGrygorii Strashko else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel")) 1188ffad5fa0SGrygorii Strashko cpsw_gmii_sel_dra7xx(priv, phy_mode); 1189ffad5fa0SGrygorii Strashko } 1190ffad5fa0SGrygorii Strashko 1191ffad5fa0SGrygorii Strashko static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) 1192ffad5fa0SGrygorii Strashko { 1193ffad5fa0SGrygorii Strashko struct eth_pdata *pdata = dev_get_platdata(dev); 1194ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1195ffad5fa0SGrygorii Strashko struct gpio_desc *mode_gpios; 1196ffad5fa0SGrygorii Strashko const char *phy_mode; 1197ffad5fa0SGrygorii Strashko const char *phy_sel_compat = NULL; 1198ffad5fa0SGrygorii Strashko const void *fdt = gd->fdt_blob; 1199ffad5fa0SGrygorii Strashko int node = dev_of_offset(dev); 1200ffad5fa0SGrygorii Strashko int subnode; 1201ffad5fa0SGrygorii Strashko int slave_index = 0; 1202ffad5fa0SGrygorii Strashko int active_slave; 1203ffad5fa0SGrygorii Strashko int num_mode_gpios; 1204ffad5fa0SGrygorii Strashko int ret; 1205ffad5fa0SGrygorii Strashko 1206ffad5fa0SGrygorii Strashko pdata->iobase = devfdt_get_addr(dev); 1207ffad5fa0SGrygorii Strashko priv->data.version = CPSW_CTRL_VERSION_2; 1208ffad5fa0SGrygorii Strashko priv->data.bd_ram_ofs = CPSW_BD_OFFSET; 1209ffad5fa0SGrygorii Strashko priv->data.ale_reg_ofs = CPSW_ALE_OFFSET; 1210ffad5fa0SGrygorii Strashko priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET; 1211ffad5fa0SGrygorii Strashko priv->data.mdio_div = CPSW_MDIO_DIV; 1212ffad5fa0SGrygorii Strashko priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET, 1213ffad5fa0SGrygorii Strashko 1214ffad5fa0SGrygorii Strashko pdata->phy_interface = -1; 1215ffad5fa0SGrygorii Strashko 1216ffad5fa0SGrygorii Strashko priv->data.cpsw_base = pdata->iobase; 1217ffad5fa0SGrygorii Strashko priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1); 1218ffad5fa0SGrygorii Strashko if (priv->data.channels <= 0) { 1219ffad5fa0SGrygorii Strashko printf("error: cpdma_channels not found in dt\n"); 1220ffad5fa0SGrygorii Strashko return -ENOENT; 1221ffad5fa0SGrygorii Strashko } 1222ffad5fa0SGrygorii Strashko 1223ffad5fa0SGrygorii Strashko priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1); 1224ffad5fa0SGrygorii Strashko if (priv->data.slaves <= 0) { 1225ffad5fa0SGrygorii Strashko printf("error: slaves not found in dt\n"); 1226ffad5fa0SGrygorii Strashko return -ENOENT; 1227ffad5fa0SGrygorii Strashko } 1228ffad5fa0SGrygorii Strashko priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) * 1229ffad5fa0SGrygorii Strashko priv->data.slaves); 1230ffad5fa0SGrygorii Strashko 1231ffad5fa0SGrygorii Strashko priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1); 1232ffad5fa0SGrygorii Strashko if (priv->data.ale_entries <= 0) { 1233ffad5fa0SGrygorii Strashko printf("error: ale_entries not found in dt\n"); 1234ffad5fa0SGrygorii Strashko return -ENOENT; 1235ffad5fa0SGrygorii Strashko } 1236ffad5fa0SGrygorii Strashko 1237ffad5fa0SGrygorii Strashko priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1); 1238ffad5fa0SGrygorii Strashko if (priv->data.bd_ram_ofs <= 0) { 1239ffad5fa0SGrygorii Strashko printf("error: bd_ram_size not found in dt\n"); 1240ffad5fa0SGrygorii Strashko return -ENOENT; 1241ffad5fa0SGrygorii Strashko } 1242ffad5fa0SGrygorii Strashko 1243ffad5fa0SGrygorii Strashko priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1); 1244ffad5fa0SGrygorii Strashko if (priv->data.mac_control <= 0) { 1245ffad5fa0SGrygorii Strashko printf("error: ale_entries not found in dt\n"); 1246ffad5fa0SGrygorii Strashko return -ENOENT; 1247ffad5fa0SGrygorii Strashko } 1248ffad5fa0SGrygorii Strashko 1249ffad5fa0SGrygorii Strashko num_mode_gpios = gpio_get_list_count(dev, "mode-gpios"); 1250ffad5fa0SGrygorii Strashko if (num_mode_gpios > 0) { 1251ffad5fa0SGrygorii Strashko mode_gpios = malloc(sizeof(struct gpio_desc) * 1252ffad5fa0SGrygorii Strashko num_mode_gpios); 1253ffad5fa0SGrygorii Strashko gpio_request_list_by_name(dev, "mode-gpios", mode_gpios, 1254ffad5fa0SGrygorii Strashko num_mode_gpios, GPIOD_IS_OUT); 1255ffad5fa0SGrygorii Strashko free(mode_gpios); 1256ffad5fa0SGrygorii Strashko } 1257ffad5fa0SGrygorii Strashko 1258ffad5fa0SGrygorii Strashko active_slave = fdtdec_get_int(fdt, node, "active_slave", 0); 1259ffad5fa0SGrygorii Strashko priv->data.active_slave = active_slave; 1260ffad5fa0SGrygorii Strashko 1261ffad5fa0SGrygorii Strashko fdt_for_each_subnode(subnode, fdt, node) { 1262ffad5fa0SGrygorii Strashko int len; 1263ffad5fa0SGrygorii Strashko const char *name; 1264ffad5fa0SGrygorii Strashko 1265ffad5fa0SGrygorii Strashko name = fdt_get_name(fdt, subnode, &len); 1266ffad5fa0SGrygorii Strashko if (!strncmp(name, "mdio", 4)) { 1267ffad5fa0SGrygorii Strashko u32 mdio_base; 1268ffad5fa0SGrygorii Strashko 1269ffad5fa0SGrygorii Strashko mdio_base = cpsw_get_addr_by_node(fdt, subnode); 1270ffad5fa0SGrygorii Strashko if (mdio_base == FDT_ADDR_T_NONE) { 1271ffad5fa0SGrygorii Strashko pr_err("Not able to get MDIO address space\n"); 1272ffad5fa0SGrygorii Strashko return -ENOENT; 1273ffad5fa0SGrygorii Strashko } 1274ffad5fa0SGrygorii Strashko priv->data.mdio_base = mdio_base; 1275ffad5fa0SGrygorii Strashko } 1276ffad5fa0SGrygorii Strashko 1277ffad5fa0SGrygorii Strashko if (!strncmp(name, "slave", 5)) { 1278ffad5fa0SGrygorii Strashko u32 phy_id[2]; 1279ffad5fa0SGrygorii Strashko 1280ffad5fa0SGrygorii Strashko if (slave_index >= priv->data.slaves) 1281ffad5fa0SGrygorii Strashko continue; 1282ffad5fa0SGrygorii Strashko phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL); 1283ffad5fa0SGrygorii Strashko if (phy_mode) 1284ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_if = 1285ffad5fa0SGrygorii Strashko phy_get_interface_by_name(phy_mode); 1286ffad5fa0SGrygorii Strashko 1287ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_of_handle = 1288ffad5fa0SGrygorii Strashko fdtdec_lookup_phandle(fdt, subnode, 1289ffad5fa0SGrygorii Strashko "phy-handle"); 1290ffad5fa0SGrygorii Strashko 1291ffad5fa0SGrygorii Strashko if (priv->data.slave_data[slave_index].phy_of_handle >= 0) { 1292ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_addr = 1293ffad5fa0SGrygorii Strashko fdtdec_get_int(gd->fdt_blob, 1294ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_of_handle, 1295ffad5fa0SGrygorii Strashko "reg", -1); 1296ffad5fa0SGrygorii Strashko } else { 1297ffad5fa0SGrygorii Strashko fdtdec_get_int_array(fdt, subnode, "phy_id", 1298ffad5fa0SGrygorii Strashko phy_id, 2); 1299ffad5fa0SGrygorii Strashko priv->data.slave_data[slave_index].phy_addr = 1300ffad5fa0SGrygorii Strashko phy_id[1]; 1301ffad5fa0SGrygorii Strashko } 1302ffad5fa0SGrygorii Strashko slave_index++; 1303ffad5fa0SGrygorii Strashko } 1304ffad5fa0SGrygorii Strashko 1305ffad5fa0SGrygorii Strashko if (!strncmp(name, "cpsw-phy-sel", 12)) { 1306ffad5fa0SGrygorii Strashko priv->data.gmii_sel = cpsw_get_addr_by_node(fdt, 1307ffad5fa0SGrygorii Strashko subnode); 1308ffad5fa0SGrygorii Strashko 1309ffad5fa0SGrygorii Strashko if (priv->data.gmii_sel == FDT_ADDR_T_NONE) { 1310ffad5fa0SGrygorii Strashko pr_err("Not able to get gmii_sel reg address\n"); 1311ffad5fa0SGrygorii Strashko return -ENOENT; 1312ffad5fa0SGrygorii Strashko } 1313ffad5fa0SGrygorii Strashko 1314ffad5fa0SGrygorii Strashko if (fdt_get_property(fdt, subnode, "rmii-clock-ext", 1315ffad5fa0SGrygorii Strashko NULL)) 1316ffad5fa0SGrygorii Strashko priv->data.rmii_clock_external = true; 1317ffad5fa0SGrygorii Strashko 1318ffad5fa0SGrygorii Strashko phy_sel_compat = fdt_getprop(fdt, subnode, "compatible", 1319ffad5fa0SGrygorii Strashko NULL); 1320ffad5fa0SGrygorii Strashko if (!phy_sel_compat) { 1321ffad5fa0SGrygorii Strashko pr_err("Not able to get gmii_sel compatible\n"); 1322ffad5fa0SGrygorii Strashko return -ENOENT; 1323ffad5fa0SGrygorii Strashko } 1324ffad5fa0SGrygorii Strashko } 1325ffad5fa0SGrygorii Strashko } 1326ffad5fa0SGrygorii Strashko 1327ffad5fa0SGrygorii Strashko priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET; 1328ffad5fa0SGrygorii Strashko priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET; 1329ffad5fa0SGrygorii Strashko 1330ffad5fa0SGrygorii Strashko if (priv->data.slaves == 2) { 1331ffad5fa0SGrygorii Strashko priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET; 1332ffad5fa0SGrygorii Strashko priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET; 1333ffad5fa0SGrygorii Strashko } 1334ffad5fa0SGrygorii Strashko 1335ffad5fa0SGrygorii Strashko ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr); 1336ffad5fa0SGrygorii Strashko if (ret < 0) { 1337ffad5fa0SGrygorii Strashko pr_err("cpsw read efuse mac failed\n"); 1338ffad5fa0SGrygorii Strashko return ret; 1339ffad5fa0SGrygorii Strashko } 1340ffad5fa0SGrygorii Strashko 1341ffad5fa0SGrygorii Strashko pdata->phy_interface = priv->data.slave_data[active_slave].phy_if; 1342ffad5fa0SGrygorii Strashko if (pdata->phy_interface == -1) { 1343ffad5fa0SGrygorii Strashko debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1344ffad5fa0SGrygorii Strashko return -EINVAL; 1345ffad5fa0SGrygorii Strashko } 1346ffad5fa0SGrygorii Strashko 1347ffad5fa0SGrygorii Strashko /* Select phy interface in control module */ 1348ffad5fa0SGrygorii Strashko cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface); 1349ffad5fa0SGrygorii Strashko 1350ffad5fa0SGrygorii Strashko return 0; 1351ffad5fa0SGrygorii Strashko } 1352ffad5fa0SGrygorii Strashko 1353ffad5fa0SGrygorii Strashko int cpsw_get_slave_phy_addr(struct udevice *dev, int slave) 1354ffad5fa0SGrygorii Strashko { 1355ffad5fa0SGrygorii Strashko struct cpsw_priv *priv = dev_get_priv(dev); 1356ffad5fa0SGrygorii Strashko struct cpsw_platform_data *data = &priv->data; 1357ffad5fa0SGrygorii Strashko 1358ffad5fa0SGrygorii Strashko return data->slave_data[slave].phy_addr; 1359ffad5fa0SGrygorii Strashko } 1360ffad5fa0SGrygorii Strashko 1361ffad5fa0SGrygorii Strashko static const struct udevice_id cpsw_eth_ids[] = { 1362ffad5fa0SGrygorii Strashko { .compatible = "ti,cpsw" }, 1363ffad5fa0SGrygorii Strashko { .compatible = "ti,am335x-cpsw" }, 1364ffad5fa0SGrygorii Strashko { } 1365ffad5fa0SGrygorii Strashko }; 1366ffad5fa0SGrygorii Strashko 1367ffad5fa0SGrygorii Strashko U_BOOT_DRIVER(eth_cpsw) = { 1368ffad5fa0SGrygorii Strashko .name = "eth_cpsw", 1369ffad5fa0SGrygorii Strashko .id = UCLASS_ETH, 1370ffad5fa0SGrygorii Strashko .of_match = cpsw_eth_ids, 1371ffad5fa0SGrygorii Strashko .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata, 1372ffad5fa0SGrygorii Strashko .probe = cpsw_eth_probe, 1373ffad5fa0SGrygorii Strashko .ops = &cpsw_eth_ops, 1374ffad5fa0SGrygorii Strashko .priv_auto_alloc_size = sizeof(struct cpsw_priv), 1375ffad5fa0SGrygorii Strashko .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1376ffad5fa0SGrygorii Strashko .flags = DM_FLAG_ALLOC_PRIV_DMA, 1377ffad5fa0SGrygorii Strashko }; 1378ffad5fa0SGrygorii Strashko #endif /* CONFIG_DM_ETH */ 1379