1 /* 2 * (C) Copyright 2016 3 * Author: Amit Singh Tomar, amittomer25@gmail.com 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Ethernet driver for H3/A64/A83T based SoC's 8 * 9 * It is derived from the work done by 10 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS! 11 * 12 */ 13 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/gpio.h> 17 #include <common.h> 18 #include <dm.h> 19 #include <fdt_support.h> 20 #include <linux/err.h> 21 #include <malloc.h> 22 #include <miiphy.h> 23 #include <net.h> 24 25 #define MDIO_CMD_MII_BUSY BIT(0) 26 #define MDIO_CMD_MII_WRITE BIT(1) 27 28 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0 29 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4 30 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000 31 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12 32 33 #define CONFIG_TX_DESCR_NUM 32 34 #define CONFIG_RX_DESCR_NUM 32 35 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */ 36 37 /* 38 * The datasheet says that each descriptor can transfers up to 4096 bytes 39 * But later, the register documentation reduces that value to 2048, 40 * using 2048 cause strange behaviours and even BSP driver use 2047 41 */ 42 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */ 43 44 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) 45 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) 46 47 #define H3_EPHY_DEFAULT_VALUE 0x58000 48 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15) 49 #define H3_EPHY_ADDR_SHIFT 20 50 #define REG_PHY_ADDR_MASK GENMASK(4, 0) 51 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 52 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 53 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 54 55 #define SC_RMII_EN BIT(13) 56 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */ 57 #define SC_ETCS_MASK GENMASK(1, 0) 58 #define SC_ETCS_EXT_GMII 0x1 59 #define SC_ETCS_INT_GMII 0x2 60 61 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) 62 63 #define AHB_GATE_OFFSET_EPHY 0 64 65 #if defined(CONFIG_MACH_SUN8I_H3) 66 #define SUN8I_GPD8_GMAC 2 67 #else 68 #define SUN8I_GPD8_GMAC 4 69 #endif 70 71 /* H3/A64 EMAC Register's offset */ 72 #define EMAC_CTL0 0x00 73 #define EMAC_CTL1 0x04 74 #define EMAC_INT_STA 0x08 75 #define EMAC_INT_EN 0x0c 76 #define EMAC_TX_CTL0 0x10 77 #define EMAC_TX_CTL1 0x14 78 #define EMAC_TX_FLOW_CTL 0x1c 79 #define EMAC_TX_DMA_DESC 0x20 80 #define EMAC_RX_CTL0 0x24 81 #define EMAC_RX_CTL1 0x28 82 #define EMAC_RX_DMA_DESC 0x34 83 #define EMAC_MII_CMD 0x48 84 #define EMAC_MII_DATA 0x4c 85 #define EMAC_ADDR0_HIGH 0x50 86 #define EMAC_ADDR0_LOW 0x54 87 #define EMAC_TX_DMA_STA 0xb0 88 #define EMAC_TX_CUR_DESC 0xb4 89 #define EMAC_TX_CUR_BUF 0xb8 90 #define EMAC_RX_DMA_STA 0xc0 91 #define EMAC_RX_CUR_DESC 0xc4 92 93 DECLARE_GLOBAL_DATA_PTR; 94 95 enum emac_variant { 96 A83T_EMAC = 1, 97 H3_EMAC, 98 A64_EMAC, 99 }; 100 101 struct emac_dma_desc { 102 u32 status; 103 u32 st; 104 u32 buf_addr; 105 u32 next; 106 } __aligned(ARCH_DMA_MINALIGN); 107 108 struct emac_eth_dev { 109 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM]; 110 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM]; 111 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 112 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 113 114 u32 interface; 115 u32 phyaddr; 116 u32 link; 117 u32 speed; 118 u32 duplex; 119 u32 phy_configured; 120 u32 tx_currdescnum; 121 u32 rx_currdescnum; 122 u32 addr; 123 u32 tx_slot; 124 bool use_internal_phy; 125 126 enum emac_variant variant; 127 void *mac_reg; 128 phys_addr_t sysctl_reg; 129 struct phy_device *phydev; 130 struct mii_dev *bus; 131 }; 132 133 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 134 { 135 struct emac_eth_dev *priv = bus->priv; 136 ulong start; 137 u32 miiaddr = 0; 138 int timeout = CONFIG_MDIO_TIMEOUT; 139 140 miiaddr &= ~MDIO_CMD_MII_WRITE; 141 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; 142 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & 143 MDIO_CMD_MII_PHY_REG_ADDR_MASK; 144 145 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK; 146 147 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & 148 MDIO_CMD_MII_PHY_ADDR_MASK; 149 150 miiaddr |= MDIO_CMD_MII_BUSY; 151 152 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); 153 154 start = get_timer(0); 155 while (get_timer(start) < timeout) { 156 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY)) 157 return readl(priv->mac_reg + EMAC_MII_DATA); 158 udelay(10); 159 }; 160 161 return -1; 162 } 163 164 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 165 u16 val) 166 { 167 struct emac_eth_dev *priv = bus->priv; 168 ulong start; 169 u32 miiaddr = 0; 170 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; 171 172 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; 173 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & 174 MDIO_CMD_MII_PHY_REG_ADDR_MASK; 175 176 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK; 177 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & 178 MDIO_CMD_MII_PHY_ADDR_MASK; 179 180 miiaddr |= MDIO_CMD_MII_WRITE; 181 miiaddr |= MDIO_CMD_MII_BUSY; 182 183 writel(val, priv->mac_reg + EMAC_MII_DATA); 184 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); 185 186 start = get_timer(0); 187 while (get_timer(start) < timeout) { 188 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & 189 MDIO_CMD_MII_BUSY)) { 190 ret = 0; 191 break; 192 } 193 udelay(10); 194 }; 195 196 return ret; 197 } 198 199 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id) 200 { 201 u32 macid_lo, macid_hi; 202 203 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + 204 (mac_id[3] << 24); 205 macid_hi = mac_id[4] + (mac_id[5] << 8); 206 207 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH); 208 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW); 209 210 return 0; 211 } 212 213 static void sun8i_adjust_link(struct emac_eth_dev *priv, 214 struct phy_device *phydev) 215 { 216 u32 v; 217 218 v = readl(priv->mac_reg + EMAC_CTL0); 219 220 if (phydev->duplex) 221 v |= BIT(0); 222 else 223 v &= ~BIT(0); 224 225 v &= ~0x0C; 226 227 switch (phydev->speed) { 228 case 1000: 229 break; 230 case 100: 231 v |= BIT(2); 232 v |= BIT(3); 233 break; 234 case 10: 235 v |= BIT(3); 236 break; 237 } 238 writel(v, priv->mac_reg + EMAC_CTL0); 239 } 240 241 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg) 242 { 243 if (priv->use_internal_phy) { 244 /* H3 based SoC's that has an Internal 100MBit PHY 245 * needs to be configured and powered up before use 246 */ 247 *reg &= ~H3_EPHY_DEFAULT_MASK; 248 *reg |= H3_EPHY_DEFAULT_VALUE; 249 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT; 250 *reg &= ~H3_EPHY_SHUTDOWN; 251 *reg |= H3_EPHY_SELECT; 252 } else 253 /* This is to select External Gigabit PHY on 254 * the boards with H3 SoC. 255 */ 256 *reg &= ~H3_EPHY_SELECT; 257 258 return 0; 259 } 260 261 static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) 262 { 263 int ret; 264 u32 reg; 265 266 reg = readl(priv->sysctl_reg); 267 268 if (priv->variant == H3_EMAC) { 269 ret = sun8i_emac_set_syscon_ephy(priv, ®); 270 if (ret) 271 return ret; 272 } 273 274 reg &= ~(SC_ETCS_MASK | SC_EPIT); 275 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC) 276 reg &= ~SC_RMII_EN; 277 278 switch (priv->interface) { 279 case PHY_INTERFACE_MODE_MII: 280 /* default */ 281 break; 282 case PHY_INTERFACE_MODE_RGMII: 283 reg |= SC_EPIT | SC_ETCS_INT_GMII; 284 break; 285 case PHY_INTERFACE_MODE_RMII: 286 if (priv->variant == H3_EMAC || 287 priv->variant == A64_EMAC) { 288 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII; 289 break; 290 } 291 /* RMII not supported on A83T */ 292 default: 293 debug("%s: Invalid PHY interface\n", __func__); 294 return -EINVAL; 295 } 296 297 writel(reg, priv->sysctl_reg); 298 299 return 0; 300 } 301 302 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev) 303 { 304 struct phy_device *phydev; 305 306 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); 307 if (!phydev) 308 return -ENODEV; 309 310 phy_connect_dev(phydev, dev); 311 312 priv->phydev = phydev; 313 phy_config(priv->phydev); 314 315 return 0; 316 } 317 318 static void rx_descs_init(struct emac_eth_dev *priv) 319 { 320 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0]; 321 char *rxbuffs = &priv->rxbuffer[0]; 322 struct emac_dma_desc *desc_p; 323 u32 idx; 324 325 /* flush Rx buffers */ 326 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs + 327 RX_TOTAL_BUFSIZE); 328 329 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { 330 desc_p = &desc_table_p[idx]; 331 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE] 332 ; 333 desc_p->next = (uintptr_t)&desc_table_p[idx + 1]; 334 desc_p->st |= CONFIG_ETH_RXSIZE; 335 desc_p->status = BIT(31); 336 } 337 338 /* Correcting the last pointer of the chain */ 339 desc_p->next = (uintptr_t)&desc_table_p[0]; 340 341 flush_dcache_range((uintptr_t)priv->rx_chain, 342 (uintptr_t)priv->rx_chain + 343 sizeof(priv->rx_chain)); 344 345 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC)); 346 priv->rx_currdescnum = 0; 347 } 348 349 static void tx_descs_init(struct emac_eth_dev *priv) 350 { 351 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0]; 352 char *txbuffs = &priv->txbuffer[0]; 353 struct emac_dma_desc *desc_p; 354 u32 idx; 355 356 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { 357 desc_p = &desc_table_p[idx]; 358 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE] 359 ; 360 desc_p->next = (uintptr_t)&desc_table_p[idx + 1]; 361 desc_p->status = (1 << 31); 362 desc_p->st = 0; 363 } 364 365 /* Correcting the last pointer of the chain */ 366 desc_p->next = (uintptr_t)&desc_table_p[0]; 367 368 /* Flush all Tx buffer descriptors */ 369 flush_dcache_range((uintptr_t)priv->tx_chain, 370 (uintptr_t)priv->tx_chain + 371 sizeof(priv->tx_chain)); 372 373 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC); 374 priv->tx_currdescnum = 0; 375 } 376 377 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) 378 { 379 u32 reg, v; 380 int timeout = 100; 381 382 reg = readl((priv->mac_reg + EMAC_CTL1)); 383 384 if (!(reg & 0x1)) { 385 /* Soft reset MAC */ 386 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1); 387 do { 388 reg = readl(priv->mac_reg + EMAC_CTL1); 389 } while ((reg & 0x01) != 0 && (--timeout)); 390 if (!timeout) { 391 printf("%s: Timeout\n", __func__); 392 return -1; 393 } 394 } 395 396 /* Rewrite mac address after reset */ 397 _sun8i_write_hwaddr(priv, enetaddr); 398 399 v = readl(priv->mac_reg + EMAC_TX_CTL1); 400 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/ 401 v |= BIT(1); 402 writel(v, priv->mac_reg + EMAC_TX_CTL1); 403 404 v = readl(priv->mac_reg + EMAC_RX_CTL1); 405 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a 406 * complete frame has been written to RX DMA FIFO 407 */ 408 v |= BIT(1); 409 writel(v, priv->mac_reg + EMAC_RX_CTL1); 410 411 /* DMA */ 412 writel(8 << 24, priv->mac_reg + EMAC_CTL1); 413 414 /* Initialize rx/tx descriptors */ 415 rx_descs_init(priv); 416 tx_descs_init(priv); 417 418 /* PHY Start Up */ 419 genphy_parse_link(priv->phydev); 420 421 sun8i_adjust_link(priv, priv->phydev); 422 423 /* Start RX DMA */ 424 v = readl(priv->mac_reg + EMAC_RX_CTL1); 425 v |= BIT(30); 426 writel(v, priv->mac_reg + EMAC_RX_CTL1); 427 /* Start TX DMA */ 428 v = readl(priv->mac_reg + EMAC_TX_CTL1); 429 v |= BIT(30); 430 writel(v, priv->mac_reg + EMAC_TX_CTL1); 431 432 /* Enable RX/TX */ 433 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31)); 434 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31)); 435 436 return 0; 437 } 438 439 static int parse_phy_pins(struct udevice *dev) 440 { 441 int offset; 442 const char *pin_name; 443 int drive, pull, i; 444 445 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 446 "pinctrl-0"); 447 if (offset < 0) { 448 printf("WARNING: emac: cannot find pinctrl-0 node\n"); 449 return offset; 450 } 451 452 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, 453 "allwinner,drive", 4); 454 pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, 455 "allwinner,pull", 0); 456 for (i = 0; ; i++) { 457 int pin; 458 459 pin_name = fdt_stringlist_get(gd->fdt_blob, offset, 460 "allwinner,pins", i, NULL); 461 if (!pin_name) 462 break; 463 if (pin_name[0] != 'P') 464 continue; 465 pin = (pin_name[1] - 'A') << 5; 466 if (pin >= 26 << 5) 467 continue; 468 pin += simple_strtol(&pin_name[2], NULL, 10); 469 470 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC); 471 sunxi_gpio_set_drv(pin, drive); 472 sunxi_gpio_set_pull(pin, pull); 473 } 474 475 if (!i) { 476 printf("WARNING: emac: cannot find allwinner,pins property\n"); 477 return -2; 478 } 479 480 return 0; 481 } 482 483 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp) 484 { 485 u32 status, desc_num = priv->rx_currdescnum; 486 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; 487 int length = -EAGAIN; 488 int good_packet = 1; 489 uintptr_t desc_start = (uintptr_t)desc_p; 490 uintptr_t desc_end = desc_start + 491 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 492 493 ulong data_start = (uintptr_t)desc_p->buf_addr; 494 ulong data_end; 495 496 /* Invalidate entire buffer descriptor */ 497 invalidate_dcache_range(desc_start, desc_end); 498 499 status = desc_p->status; 500 501 /* Check for DMA own bit */ 502 if (!(status & BIT(31))) { 503 length = (desc_p->status >> 16) & 0x3FFF; 504 505 if (length < 0x40) { 506 good_packet = 0; 507 debug("RX: Bad Packet (runt)\n"); 508 } 509 510 data_end = data_start + length; 511 /* Invalidate received data */ 512 invalidate_dcache_range(rounddown(data_start, 513 ARCH_DMA_MINALIGN), 514 roundup(data_end, 515 ARCH_DMA_MINALIGN)); 516 if (good_packet) { 517 if (length > CONFIG_ETH_RXSIZE) { 518 printf("Received packet is too big (len=%d)\n", 519 length); 520 return -EMSGSIZE; 521 } 522 *packetp = (uchar *)(ulong)desc_p->buf_addr; 523 return length; 524 } 525 } 526 527 return length; 528 } 529 530 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet, 531 int len) 532 { 533 u32 v, desc_num = priv->tx_currdescnum; 534 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num]; 535 uintptr_t desc_start = (uintptr_t)desc_p; 536 uintptr_t desc_end = desc_start + 537 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); 538 539 uintptr_t data_start = (uintptr_t)desc_p->buf_addr; 540 uintptr_t data_end = data_start + 541 roundup(len, ARCH_DMA_MINALIGN); 542 543 /* Invalidate entire buffer descriptor */ 544 invalidate_dcache_range(desc_start, desc_end); 545 546 desc_p->st = len; 547 /* Mandatory undocumented bit */ 548 desc_p->st |= BIT(24); 549 550 memcpy((void *)data_start, packet, len); 551 552 /* Flush data to be sent */ 553 flush_dcache_range(data_start, data_end); 554 555 /* frame end */ 556 desc_p->st |= BIT(30); 557 desc_p->st |= BIT(31); 558 559 /*frame begin */ 560 desc_p->st |= BIT(29); 561 desc_p->status = BIT(31); 562 563 /*Descriptors st and status field has changed, so FLUSH it */ 564 flush_dcache_range(desc_start, desc_end); 565 566 /* Move to next Descriptor and wrap around */ 567 if (++desc_num >= CONFIG_TX_DESCR_NUM) 568 desc_num = 0; 569 priv->tx_currdescnum = desc_num; 570 571 /* Start the DMA */ 572 v = readl(priv->mac_reg + EMAC_TX_CTL1); 573 v |= BIT(31);/* mandatory */ 574 v |= BIT(30);/* mandatory */ 575 writel(v, priv->mac_reg + EMAC_TX_CTL1); 576 577 return 0; 578 } 579 580 static int sun8i_eth_write_hwaddr(struct udevice *dev) 581 { 582 struct eth_pdata *pdata = dev_get_platdata(dev); 583 struct emac_eth_dev *priv = dev_get_priv(dev); 584 585 return _sun8i_write_hwaddr(priv, pdata->enetaddr); 586 } 587 588 static void sun8i_emac_board_setup(struct emac_eth_dev *priv) 589 { 590 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 591 592 if (priv->use_internal_phy) { 593 /* Set clock gating for ephy */ 594 setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); 595 596 /* Deassert EPHY */ 597 setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); 598 } 599 600 /* Set clock gating for emac */ 601 setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); 602 603 /* De-assert EMAC */ 604 setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); 605 } 606 607 static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv) 608 { 609 struct mii_dev *bus = mdio_alloc(); 610 611 if (!bus) { 612 debug("Failed to allocate MDIO bus\n"); 613 return -ENOMEM; 614 } 615 616 bus->read = sun8i_mdio_read; 617 bus->write = sun8i_mdio_write; 618 snprintf(bus->name, sizeof(bus->name), name); 619 bus->priv = (void *)priv; 620 621 return mdio_register(bus); 622 } 623 624 static int sun8i_emac_eth_start(struct udevice *dev) 625 { 626 struct eth_pdata *pdata = dev_get_platdata(dev); 627 628 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr); 629 } 630 631 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length) 632 { 633 struct emac_eth_dev *priv = dev_get_priv(dev); 634 635 return _sun8i_emac_eth_send(priv, packet, length); 636 } 637 638 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp) 639 { 640 struct emac_eth_dev *priv = dev_get_priv(dev); 641 642 return _sun8i_eth_recv(priv, packetp); 643 } 644 645 static int _sun8i_free_pkt(struct emac_eth_dev *priv) 646 { 647 u32 desc_num = priv->rx_currdescnum; 648 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; 649 uintptr_t desc_start = (uintptr_t)desc_p; 650 uintptr_t desc_end = desc_start + 651 roundup(sizeof(u32), ARCH_DMA_MINALIGN); 652 653 /* Make the current descriptor valid again */ 654 desc_p->status |= BIT(31); 655 656 /* Flush Status field of descriptor */ 657 flush_dcache_range(desc_start, desc_end); 658 659 /* Move to next desc and wrap-around condition. */ 660 if (++desc_num >= CONFIG_RX_DESCR_NUM) 661 desc_num = 0; 662 priv->rx_currdescnum = desc_num; 663 664 return 0; 665 } 666 667 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet, 668 int length) 669 { 670 struct emac_eth_dev *priv = dev_get_priv(dev); 671 672 return _sun8i_free_pkt(priv); 673 } 674 675 static void sun8i_emac_eth_stop(struct udevice *dev) 676 { 677 struct emac_eth_dev *priv = dev_get_priv(dev); 678 679 /* Stop Rx/Tx transmitter */ 680 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31)); 681 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31)); 682 683 /* Stop TX DMA */ 684 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30)); 685 686 phy_shutdown(priv->phydev); 687 } 688 689 static int sun8i_emac_eth_probe(struct udevice *dev) 690 { 691 struct eth_pdata *pdata = dev_get_platdata(dev); 692 struct emac_eth_dev *priv = dev_get_priv(dev); 693 694 priv->mac_reg = (void *)pdata->iobase; 695 696 sun8i_emac_board_setup(priv); 697 sun8i_emac_set_syscon(priv); 698 699 sun8i_mdio_init(dev->name, priv); 700 priv->bus = miiphy_get_dev_by_name(dev->name); 701 702 return sun8i_phy_init(priv, dev); 703 } 704 705 static const struct eth_ops sun8i_emac_eth_ops = { 706 .start = sun8i_emac_eth_start, 707 .write_hwaddr = sun8i_eth_write_hwaddr, 708 .send = sun8i_emac_eth_send, 709 .recv = sun8i_emac_eth_recv, 710 .free_pkt = sun8i_eth_free_pkt, 711 .stop = sun8i_emac_eth_stop, 712 }; 713 714 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) 715 { 716 struct eth_pdata *pdata = dev_get_platdata(dev); 717 struct emac_eth_dev *priv = dev_get_priv(dev); 718 const char *phy_mode; 719 int offset = 0; 720 721 pdata->iobase = dev_get_addr_name(dev, "emac"); 722 priv->sysctl_reg = dev_get_addr_name(dev, "syscon"); 723 724 pdata->phy_interface = -1; 725 priv->phyaddr = -1; 726 priv->use_internal_phy = false; 727 728 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, 729 "phy"); 730 if (offset > 0) 731 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", 732 -1); 733 734 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 735 736 if (phy_mode) 737 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 738 printf("phy interface%d\n", pdata->phy_interface); 739 740 if (pdata->phy_interface == -1) { 741 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 742 return -EINVAL; 743 } 744 745 priv->variant = dev_get_driver_data(dev); 746 747 if (!priv->variant) { 748 printf("%s: Missing variant '%s'\n", __func__, 749 (char *)priv->variant); 750 return -EINVAL; 751 } 752 753 if (priv->variant == H3_EMAC) { 754 if (fdt_getprop(gd->fdt_blob, dev->of_offset, 755 "allwinner,use-internal-phy", NULL)) 756 priv->use_internal_phy = true; 757 } 758 759 priv->interface = pdata->phy_interface; 760 761 if (!priv->use_internal_phy) 762 parse_phy_pins(dev); 763 764 return 0; 765 } 766 767 static const struct udevice_id sun8i_emac_eth_ids[] = { 768 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC }, 769 {.compatible = "allwinner,sun50i-a64-emac", 770 .data = (uintptr_t)A64_EMAC }, 771 {.compatible = "allwinner,sun8i-a83t-emac", 772 .data = (uintptr_t)A83T_EMAC }, 773 { } 774 }; 775 776 U_BOOT_DRIVER(eth_sun8i_emac) = { 777 .name = "eth_sun8i_emac", 778 .id = UCLASS_ETH, 779 .of_match = sun8i_emac_eth_ids, 780 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata, 781 .probe = sun8i_emac_eth_probe, 782 .ops = &sun8i_emac_eth_ops, 783 .priv_auto_alloc_size = sizeof(struct emac_eth_dev), 784 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 785 .flags = DM_FLAG_ALLOC_PRIV_DMA, 786 }; 787