1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
5 *
6 * Ethernet driver for H3/A64/A83T based SoC's
7 *
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
10 *
11 */
12
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/gpio.h>
16 #include <common.h>
17 #include <dm.h>
18 #include <fdt_support.h>
19 #include <linux/err.h>
20 #include <malloc.h>
21 #include <miiphy.h>
22 #include <net.h>
23 #include <dt-bindings/pinctrl/sun4i-a10.h>
24 #ifdef CONFIG_DM_GPIO
25 #include <asm-generic/gpio.h>
26 #endif
27
28 #define MDIO_CMD_MII_BUSY BIT(0)
29 #define MDIO_CMD_MII_WRITE BIT(1)
30
31 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
32 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
33 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
34 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
35
36 #define CONFIG_TX_DESCR_NUM 32
37 #define CONFIG_RX_DESCR_NUM 32
38 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
39
40 /*
41 * The datasheet says that each descriptor can transfers up to 4096 bytes
42 * But later, the register documentation reduces that value to 2048,
43 * using 2048 cause strange behaviours and even BSP driver use 2047
44 */
45 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
46
47 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
48 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
49
50 #define H3_EPHY_DEFAULT_VALUE 0x58000
51 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
52 #define H3_EPHY_ADDR_SHIFT 20
53 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
54 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
55 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
56 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
57
58 #define SC_RMII_EN BIT(13)
59 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
60 #define SC_ETCS_MASK GENMASK(1, 0)
61 #define SC_ETCS_EXT_GMII 0x1
62 #define SC_ETCS_INT_GMII 0x2
63 #define SC_ETXDC_MASK GENMASK(12, 10)
64 #define SC_ETXDC_OFFSET 10
65 #define SC_ERXDC_MASK GENMASK(9, 5)
66 #define SC_ERXDC_OFFSET 5
67
68 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
69
70 #define AHB_GATE_OFFSET_EPHY 0
71
72 /* IO mux settings */
73 #define SUN8I_IOMUX_H3 2
74 #define SUN8I_IOMUX_R40 5
75 #define SUN8I_IOMUX 4
76
77 /* H3/A64 EMAC Register's offset */
78 #define EMAC_CTL0 0x00
79 #define EMAC_CTL1 0x04
80 #define EMAC_INT_STA 0x08
81 #define EMAC_INT_EN 0x0c
82 #define EMAC_TX_CTL0 0x10
83 #define EMAC_TX_CTL1 0x14
84 #define EMAC_TX_FLOW_CTL 0x1c
85 #define EMAC_TX_DMA_DESC 0x20
86 #define EMAC_RX_CTL0 0x24
87 #define EMAC_RX_CTL1 0x28
88 #define EMAC_RX_DMA_DESC 0x34
89 #define EMAC_MII_CMD 0x48
90 #define EMAC_MII_DATA 0x4c
91 #define EMAC_ADDR0_HIGH 0x50
92 #define EMAC_ADDR0_LOW 0x54
93 #define EMAC_TX_DMA_STA 0xb0
94 #define EMAC_TX_CUR_DESC 0xb4
95 #define EMAC_TX_CUR_BUF 0xb8
96 #define EMAC_RX_DMA_STA 0xc0
97 #define EMAC_RX_CUR_DESC 0xc4
98
99 DECLARE_GLOBAL_DATA_PTR;
100
101 enum emac_variant {
102 A83T_EMAC = 1,
103 H3_EMAC,
104 A64_EMAC,
105 R40_GMAC,
106 };
107
108 struct emac_dma_desc {
109 u32 status;
110 u32 st;
111 u32 buf_addr;
112 u32 next;
113 } __aligned(ARCH_DMA_MINALIGN);
114
115 struct emac_eth_dev {
116 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
117 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
118 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
119 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
120
121 u32 interface;
122 u32 phyaddr;
123 u32 link;
124 u32 speed;
125 u32 duplex;
126 u32 phy_configured;
127 u32 tx_currdescnum;
128 u32 rx_currdescnum;
129 u32 addr;
130 u32 tx_slot;
131 bool use_internal_phy;
132
133 enum emac_variant variant;
134 void *mac_reg;
135 phys_addr_t sysctl_reg;
136 struct phy_device *phydev;
137 struct mii_dev *bus;
138 #ifdef CONFIG_DM_GPIO
139 struct gpio_desc reset_gpio;
140 #endif
141 };
142
143
144 struct sun8i_eth_pdata {
145 struct eth_pdata eth_pdata;
146 u32 reset_delays[3];
147 int tx_delay_ps;
148 int rx_delay_ps;
149 };
150
151
sun8i_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)152 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
153 {
154 struct udevice *dev = bus->priv;
155 struct emac_eth_dev *priv = dev_get_priv(dev);
156 ulong start;
157 u32 miiaddr = 0;
158 int timeout = CONFIG_MDIO_TIMEOUT;
159
160 miiaddr &= ~MDIO_CMD_MII_WRITE;
161 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
162 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
163 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
164
165 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
166
167 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
168 MDIO_CMD_MII_PHY_ADDR_MASK;
169
170 miiaddr |= MDIO_CMD_MII_BUSY;
171
172 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
173
174 start = get_timer(0);
175 while (get_timer(start) < timeout) {
176 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
177 return readl(priv->mac_reg + EMAC_MII_DATA);
178 udelay(10);
179 };
180
181 return -1;
182 }
183
sun8i_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)184 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
185 u16 val)
186 {
187 struct udevice *dev = bus->priv;
188 struct emac_eth_dev *priv = dev_get_priv(dev);
189 ulong start;
190 u32 miiaddr = 0;
191 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
192
193 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
194 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
195 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
196
197 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
198 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
199 MDIO_CMD_MII_PHY_ADDR_MASK;
200
201 miiaddr |= MDIO_CMD_MII_WRITE;
202 miiaddr |= MDIO_CMD_MII_BUSY;
203
204 writel(val, priv->mac_reg + EMAC_MII_DATA);
205 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
206
207 start = get_timer(0);
208 while (get_timer(start) < timeout) {
209 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
210 MDIO_CMD_MII_BUSY)) {
211 ret = 0;
212 break;
213 }
214 udelay(10);
215 };
216
217 return ret;
218 }
219
_sun8i_write_hwaddr(struct emac_eth_dev * priv,u8 * mac_id)220 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
221 {
222 u32 macid_lo, macid_hi;
223
224 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
225 (mac_id[3] << 24);
226 macid_hi = mac_id[4] + (mac_id[5] << 8);
227
228 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
229 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
230
231 return 0;
232 }
233
sun8i_adjust_link(struct emac_eth_dev * priv,struct phy_device * phydev)234 static void sun8i_adjust_link(struct emac_eth_dev *priv,
235 struct phy_device *phydev)
236 {
237 u32 v;
238
239 v = readl(priv->mac_reg + EMAC_CTL0);
240
241 if (phydev->duplex)
242 v |= BIT(0);
243 else
244 v &= ~BIT(0);
245
246 v &= ~0x0C;
247
248 switch (phydev->speed) {
249 case 1000:
250 break;
251 case 100:
252 v |= BIT(2);
253 v |= BIT(3);
254 break;
255 case 10:
256 v |= BIT(3);
257 break;
258 }
259 writel(v, priv->mac_reg + EMAC_CTL0);
260 }
261
sun8i_emac_set_syscon_ephy(struct emac_eth_dev * priv,u32 * reg)262 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
263 {
264 if (priv->use_internal_phy) {
265 /* H3 based SoC's that has an Internal 100MBit PHY
266 * needs to be configured and powered up before use
267 */
268 *reg &= ~H3_EPHY_DEFAULT_MASK;
269 *reg |= H3_EPHY_DEFAULT_VALUE;
270 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
271 *reg &= ~H3_EPHY_SHUTDOWN;
272 *reg |= H3_EPHY_SELECT;
273 } else
274 /* This is to select External Gigabit PHY on
275 * the boards with H3 SoC.
276 */
277 *reg &= ~H3_EPHY_SELECT;
278
279 return 0;
280 }
281
sun8i_emac_set_syscon(struct sun8i_eth_pdata * pdata,struct emac_eth_dev * priv)282 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
283 struct emac_eth_dev *priv)
284 {
285 int ret;
286 u32 reg;
287
288 reg = readl(priv->sysctl_reg + 0x30);
289
290 if (priv->variant == R40_GMAC)
291 return 0;
292
293 if (priv->variant == H3_EMAC) {
294 ret = sun8i_emac_set_syscon_ephy(priv, ®);
295 if (ret)
296 return ret;
297 }
298
299 reg &= ~(SC_ETCS_MASK | SC_EPIT);
300 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
301 reg &= ~SC_RMII_EN;
302
303 switch (priv->interface) {
304 case PHY_INTERFACE_MODE_MII:
305 /* default */
306 break;
307 case PHY_INTERFACE_MODE_RGMII:
308 reg |= SC_EPIT | SC_ETCS_INT_GMII;
309 break;
310 case PHY_INTERFACE_MODE_RMII:
311 if (priv->variant == H3_EMAC ||
312 priv->variant == A64_EMAC) {
313 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
314 break;
315 }
316 /* RMII not supported on A83T */
317 default:
318 debug("%s: Invalid PHY interface\n", __func__);
319 return -EINVAL;
320 }
321
322 if (pdata->tx_delay_ps)
323 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
324 & SC_ETXDC_MASK;
325
326 if (pdata->rx_delay_ps)
327 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
328 & SC_ERXDC_MASK;
329
330 writel(reg, priv->sysctl_reg + 0x30);
331
332 return 0;
333 }
334
sun8i_phy_init(struct emac_eth_dev * priv,void * dev)335 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
336 {
337 struct phy_device *phydev;
338
339 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
340 if (!phydev)
341 return -ENODEV;
342
343 phy_connect_dev(phydev, dev);
344
345 priv->phydev = phydev;
346 phy_config(priv->phydev);
347
348 return 0;
349 }
350
rx_descs_init(struct emac_eth_dev * priv)351 static void rx_descs_init(struct emac_eth_dev *priv)
352 {
353 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
354 char *rxbuffs = &priv->rxbuffer[0];
355 struct emac_dma_desc *desc_p;
356 u32 idx;
357
358 /* flush Rx buffers */
359 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
360 RX_TOTAL_BUFSIZE);
361
362 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
363 desc_p = &desc_table_p[idx];
364 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
365 ;
366 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
367 desc_p->st |= CONFIG_ETH_RXSIZE;
368 desc_p->status = BIT(31);
369 }
370
371 /* Correcting the last pointer of the chain */
372 desc_p->next = (uintptr_t)&desc_table_p[0];
373
374 flush_dcache_range((uintptr_t)priv->rx_chain,
375 (uintptr_t)priv->rx_chain +
376 sizeof(priv->rx_chain));
377
378 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
379 priv->rx_currdescnum = 0;
380 }
381
tx_descs_init(struct emac_eth_dev * priv)382 static void tx_descs_init(struct emac_eth_dev *priv)
383 {
384 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
385 char *txbuffs = &priv->txbuffer[0];
386 struct emac_dma_desc *desc_p;
387 u32 idx;
388
389 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
390 desc_p = &desc_table_p[idx];
391 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
392 ;
393 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
394 desc_p->status = (1 << 31);
395 desc_p->st = 0;
396 }
397
398 /* Correcting the last pointer of the chain */
399 desc_p->next = (uintptr_t)&desc_table_p[0];
400
401 /* Flush all Tx buffer descriptors */
402 flush_dcache_range((uintptr_t)priv->tx_chain,
403 (uintptr_t)priv->tx_chain +
404 sizeof(priv->tx_chain));
405
406 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
407 priv->tx_currdescnum = 0;
408 }
409
_sun8i_emac_eth_init(struct emac_eth_dev * priv,u8 * enetaddr)410 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
411 {
412 u32 reg, v;
413 int timeout = 100;
414
415 reg = readl((priv->mac_reg + EMAC_CTL1));
416
417 if (!(reg & 0x1)) {
418 /* Soft reset MAC */
419 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
420 do {
421 reg = readl(priv->mac_reg + EMAC_CTL1);
422 } while ((reg & 0x01) != 0 && (--timeout));
423 if (!timeout) {
424 printf("%s: Timeout\n", __func__);
425 return -1;
426 }
427 }
428
429 /* Rewrite mac address after reset */
430 _sun8i_write_hwaddr(priv, enetaddr);
431
432 v = readl(priv->mac_reg + EMAC_TX_CTL1);
433 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
434 v |= BIT(1);
435 writel(v, priv->mac_reg + EMAC_TX_CTL1);
436
437 v = readl(priv->mac_reg + EMAC_RX_CTL1);
438 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
439 * complete frame has been written to RX DMA FIFO
440 */
441 v |= BIT(1);
442 writel(v, priv->mac_reg + EMAC_RX_CTL1);
443
444 /* DMA */
445 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
446
447 /* Initialize rx/tx descriptors */
448 rx_descs_init(priv);
449 tx_descs_init(priv);
450
451 /* PHY Start Up */
452 phy_startup(priv->phydev);
453
454 sun8i_adjust_link(priv, priv->phydev);
455
456 /* Start RX DMA */
457 v = readl(priv->mac_reg + EMAC_RX_CTL1);
458 v |= BIT(30);
459 writel(v, priv->mac_reg + EMAC_RX_CTL1);
460 /* Start TX DMA */
461 v = readl(priv->mac_reg + EMAC_TX_CTL1);
462 v |= BIT(30);
463 writel(v, priv->mac_reg + EMAC_TX_CTL1);
464
465 /* Enable RX/TX */
466 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
467 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
468
469 return 0;
470 }
471
parse_phy_pins(struct udevice * dev)472 static int parse_phy_pins(struct udevice *dev)
473 {
474 struct emac_eth_dev *priv = dev_get_priv(dev);
475 int offset;
476 const char *pin_name;
477 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
478
479 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
480 "pinctrl-0");
481 if (offset < 0) {
482 printf("WARNING: emac: cannot find pinctrl-0 node\n");
483 return offset;
484 }
485
486 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
487 "drive-strength", ~0);
488 if (drive != ~0) {
489 if (drive <= 10)
490 drive = SUN4I_PINCTRL_10_MA;
491 else if (drive <= 20)
492 drive = SUN4I_PINCTRL_20_MA;
493 else if (drive <= 30)
494 drive = SUN4I_PINCTRL_30_MA;
495 else
496 drive = SUN4I_PINCTRL_40_MA;
497 }
498
499 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
500 pull = SUN4I_PINCTRL_PULL_UP;
501 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
502 pull = SUN4I_PINCTRL_PULL_DOWN;
503
504 for (i = 0; ; i++) {
505 int pin;
506
507 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
508 "pins", i, NULL);
509 if (!pin_name)
510 break;
511
512 pin = sunxi_name_to_gpio(pin_name);
513 if (pin < 0)
514 continue;
515
516 if (priv->variant == H3_EMAC)
517 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
518 else if (priv->variant == R40_GMAC)
519 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
520 else
521 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
522
523 if (drive != ~0)
524 sunxi_gpio_set_drv(pin, drive);
525 if (pull != ~0)
526 sunxi_gpio_set_pull(pin, pull);
527 }
528
529 if (!i) {
530 printf("WARNING: emac: cannot find pins property\n");
531 return -2;
532 }
533
534 return 0;
535 }
536
_sun8i_eth_recv(struct emac_eth_dev * priv,uchar ** packetp)537 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
538 {
539 u32 status, desc_num = priv->rx_currdescnum;
540 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
541 int length = -EAGAIN;
542 int good_packet = 1;
543 uintptr_t desc_start = (uintptr_t)desc_p;
544 uintptr_t desc_end = desc_start +
545 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
546
547 ulong data_start = (uintptr_t)desc_p->buf_addr;
548 ulong data_end;
549
550 /* Invalidate entire buffer descriptor */
551 invalidate_dcache_range(desc_start, desc_end);
552
553 status = desc_p->status;
554
555 /* Check for DMA own bit */
556 if (!(status & BIT(31))) {
557 length = (desc_p->status >> 16) & 0x3FFF;
558
559 if (length < 0x40) {
560 good_packet = 0;
561 debug("RX: Bad Packet (runt)\n");
562 }
563
564 data_end = data_start + length;
565 /* Invalidate received data */
566 invalidate_dcache_range(rounddown(data_start,
567 ARCH_DMA_MINALIGN),
568 roundup(data_end,
569 ARCH_DMA_MINALIGN));
570 if (good_packet) {
571 if (length > CONFIG_ETH_RXSIZE) {
572 printf("Received packet is too big (len=%d)\n",
573 length);
574 return -EMSGSIZE;
575 }
576 *packetp = (uchar *)(ulong)desc_p->buf_addr;
577 return length;
578 }
579 }
580
581 return length;
582 }
583
_sun8i_emac_eth_send(struct emac_eth_dev * priv,void * packet,int len)584 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
585 int len)
586 {
587 u32 v, desc_num = priv->tx_currdescnum;
588 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
589 uintptr_t desc_start = (uintptr_t)desc_p;
590 uintptr_t desc_end = desc_start +
591 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
592
593 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
594 uintptr_t data_end = data_start +
595 roundup(len, ARCH_DMA_MINALIGN);
596
597 /* Invalidate entire buffer descriptor */
598 invalidate_dcache_range(desc_start, desc_end);
599
600 desc_p->st = len;
601 /* Mandatory undocumented bit */
602 desc_p->st |= BIT(24);
603
604 memcpy((void *)data_start, packet, len);
605
606 /* Flush data to be sent */
607 flush_dcache_range(data_start, data_end);
608
609 /* frame end */
610 desc_p->st |= BIT(30);
611 desc_p->st |= BIT(31);
612
613 /*frame begin */
614 desc_p->st |= BIT(29);
615 desc_p->status = BIT(31);
616
617 /*Descriptors st and status field has changed, so FLUSH it */
618 flush_dcache_range(desc_start, desc_end);
619
620 /* Move to next Descriptor and wrap around */
621 if (++desc_num >= CONFIG_TX_DESCR_NUM)
622 desc_num = 0;
623 priv->tx_currdescnum = desc_num;
624
625 /* Start the DMA */
626 v = readl(priv->mac_reg + EMAC_TX_CTL1);
627 v |= BIT(31);/* mandatory */
628 v |= BIT(30);/* mandatory */
629 writel(v, priv->mac_reg + EMAC_TX_CTL1);
630
631 return 0;
632 }
633
sun8i_eth_write_hwaddr(struct udevice * dev)634 static int sun8i_eth_write_hwaddr(struct udevice *dev)
635 {
636 struct eth_pdata *pdata = dev_get_platdata(dev);
637 struct emac_eth_dev *priv = dev_get_priv(dev);
638
639 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
640 }
641
sun8i_emac_board_setup(struct emac_eth_dev * priv)642 static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
643 {
644 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
645
646 if (priv->variant == H3_EMAC) {
647 /* Only H3/H5 have clock controls for internal EPHY */
648 if (priv->use_internal_phy) {
649 /* Set clock gating for ephy */
650 setbits_le32(&ccm->bus_gate4,
651 BIT(AHB_GATE_OFFSET_EPHY));
652
653 /* Deassert EPHY */
654 setbits_le32(&ccm->ahb_reset2_cfg,
655 BIT(AHB_RESET_OFFSET_EPHY));
656 }
657 }
658
659 if (priv->variant == R40_GMAC) {
660 /* Set clock gating for emac */
661 setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
662
663 /* De-assert EMAC */
664 setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
665
666 /* Select RGMII for R40 */
667 setbits_le32(&ccm->gmac_clk_cfg,
668 CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
669 CCM_GMAC_CTRL_GPIT_RGMII);
670 setbits_le32(&ccm->gmac_clk_cfg,
671 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
672 } else {
673 /* Set clock gating for emac */
674 setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
675
676 /* De-assert EMAC */
677 setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
678 }
679 }
680
681 #if defined(CONFIG_DM_GPIO)
sun8i_mdio_reset(struct mii_dev * bus)682 static int sun8i_mdio_reset(struct mii_dev *bus)
683 {
684 struct udevice *dev = bus->priv;
685 struct emac_eth_dev *priv = dev_get_priv(dev);
686 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
687 int ret;
688
689 if (!dm_gpio_is_valid(&priv->reset_gpio))
690 return 0;
691
692 /* reset the phy */
693 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
694 if (ret)
695 return ret;
696
697 udelay(pdata->reset_delays[0]);
698
699 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
700 if (ret)
701 return ret;
702
703 udelay(pdata->reset_delays[1]);
704
705 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
706 if (ret)
707 return ret;
708
709 udelay(pdata->reset_delays[2]);
710
711 return 0;
712 }
713 #endif
714
sun8i_mdio_init(const char * name,struct udevice * priv)715 static int sun8i_mdio_init(const char *name, struct udevice *priv)
716 {
717 struct mii_dev *bus = mdio_alloc();
718
719 if (!bus) {
720 debug("Failed to allocate MDIO bus\n");
721 return -ENOMEM;
722 }
723
724 bus->read = sun8i_mdio_read;
725 bus->write = sun8i_mdio_write;
726 snprintf(bus->name, sizeof(bus->name), name);
727 bus->priv = (void *)priv;
728 #if defined(CONFIG_DM_GPIO)
729 bus->reset = sun8i_mdio_reset;
730 #endif
731
732 return mdio_register(bus);
733 }
734
sun8i_emac_eth_start(struct udevice * dev)735 static int sun8i_emac_eth_start(struct udevice *dev)
736 {
737 struct eth_pdata *pdata = dev_get_platdata(dev);
738
739 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
740 }
741
sun8i_emac_eth_send(struct udevice * dev,void * packet,int length)742 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
743 {
744 struct emac_eth_dev *priv = dev_get_priv(dev);
745
746 return _sun8i_emac_eth_send(priv, packet, length);
747 }
748
sun8i_emac_eth_recv(struct udevice * dev,int flags,uchar ** packetp)749 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
750 {
751 struct emac_eth_dev *priv = dev_get_priv(dev);
752
753 return _sun8i_eth_recv(priv, packetp);
754 }
755
_sun8i_free_pkt(struct emac_eth_dev * priv)756 static int _sun8i_free_pkt(struct emac_eth_dev *priv)
757 {
758 u32 desc_num = priv->rx_currdescnum;
759 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
760 uintptr_t desc_start = (uintptr_t)desc_p;
761 uintptr_t desc_end = desc_start +
762 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
763
764 /* Make the current descriptor valid again */
765 desc_p->status |= BIT(31);
766
767 /* Flush Status field of descriptor */
768 flush_dcache_range(desc_start, desc_end);
769
770 /* Move to next desc and wrap-around condition. */
771 if (++desc_num >= CONFIG_RX_DESCR_NUM)
772 desc_num = 0;
773 priv->rx_currdescnum = desc_num;
774
775 return 0;
776 }
777
sun8i_eth_free_pkt(struct udevice * dev,uchar * packet,int length)778 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
779 int length)
780 {
781 struct emac_eth_dev *priv = dev_get_priv(dev);
782
783 return _sun8i_free_pkt(priv);
784 }
785
sun8i_emac_eth_stop(struct udevice * dev)786 static void sun8i_emac_eth_stop(struct udevice *dev)
787 {
788 struct emac_eth_dev *priv = dev_get_priv(dev);
789
790 /* Stop Rx/Tx transmitter */
791 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
792 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
793
794 /* Stop TX DMA */
795 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
796
797 phy_shutdown(priv->phydev);
798 }
799
sun8i_emac_eth_probe(struct udevice * dev)800 static int sun8i_emac_eth_probe(struct udevice *dev)
801 {
802 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
803 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
804 struct emac_eth_dev *priv = dev_get_priv(dev);
805
806 priv->mac_reg = (void *)pdata->iobase;
807
808 sun8i_emac_board_setup(priv);
809 sun8i_emac_set_syscon(sun8i_pdata, priv);
810
811 sun8i_mdio_init(dev->name, dev);
812 priv->bus = miiphy_get_dev_by_name(dev->name);
813
814 return sun8i_phy_init(priv, dev);
815 }
816
817 static const struct eth_ops sun8i_emac_eth_ops = {
818 .start = sun8i_emac_eth_start,
819 .write_hwaddr = sun8i_eth_write_hwaddr,
820 .send = sun8i_emac_eth_send,
821 .recv = sun8i_emac_eth_recv,
822 .free_pkt = sun8i_eth_free_pkt,
823 .stop = sun8i_emac_eth_stop,
824 };
825
sun8i_emac_eth_ofdata_to_platdata(struct udevice * dev)826 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
827 {
828 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
829 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
830 struct emac_eth_dev *priv = dev_get_priv(dev);
831 const char *phy_mode;
832 const fdt32_t *reg;
833 int node = dev_of_offset(dev);
834 int offset = 0;
835 #ifdef CONFIG_DM_GPIO
836 int reset_flags = GPIOD_IS_OUT;
837 int ret = 0;
838 #endif
839
840 pdata->iobase = devfdt_get_addr(dev);
841 if (pdata->iobase == FDT_ADDR_T_NONE) {
842 debug("%s: Cannot find MAC base address\n", __func__);
843 return -EINVAL;
844 }
845
846 priv->variant = dev_get_driver_data(dev);
847
848 if (!priv->variant) {
849 printf("%s: Missing variant\n", __func__);
850 return -EINVAL;
851 }
852
853 if (priv->variant != R40_GMAC) {
854 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
855 if (offset < 0) {
856 debug("%s: cannot find syscon node\n", __func__);
857 return -EINVAL;
858 }
859 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
860 if (!reg) {
861 debug("%s: cannot find reg property in syscon node\n",
862 __func__);
863 return -EINVAL;
864 }
865 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
866 offset, reg);
867 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
868 debug("%s: Cannot find syscon base address\n",
869 __func__);
870 return -EINVAL;
871 }
872 }
873
874 pdata->phy_interface = -1;
875 priv->phyaddr = -1;
876 priv->use_internal_phy = false;
877
878 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
879 if (offset < 0) {
880 debug("%s: Cannot find PHY address\n", __func__);
881 return -EINVAL;
882 }
883 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
884
885 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
886
887 if (phy_mode)
888 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
889 printf("phy interface%d\n", pdata->phy_interface);
890
891 if (pdata->phy_interface == -1) {
892 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
893 return -EINVAL;
894 }
895
896 if (priv->variant == H3_EMAC) {
897 int parent = fdt_parent_offset(gd->fdt_blob, offset);
898
899 if (parent >= 0 &&
900 !fdt_node_check_compatible(gd->fdt_blob, parent,
901 "allwinner,sun8i-h3-mdio-internal"))
902 priv->use_internal_phy = true;
903 }
904
905 priv->interface = pdata->phy_interface;
906
907 if (!priv->use_internal_phy)
908 parse_phy_pins(dev);
909
910 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
911 "allwinner,tx-delay-ps", 0);
912 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
913 printf("%s: Invalid TX delay value %d\n", __func__,
914 sun8i_pdata->tx_delay_ps);
915
916 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
917 "allwinner,rx-delay-ps", 0);
918 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
919 printf("%s: Invalid RX delay value %d\n", __func__,
920 sun8i_pdata->rx_delay_ps);
921
922 #ifdef CONFIG_DM_GPIO
923 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
924 "snps,reset-active-low"))
925 reset_flags |= GPIOD_ACTIVE_LOW;
926
927 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
928 &priv->reset_gpio, reset_flags);
929
930 if (ret == 0) {
931 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
932 "snps,reset-delays-us",
933 sun8i_pdata->reset_delays, 3);
934 } else if (ret == -ENOENT) {
935 ret = 0;
936 }
937 #endif
938
939 return 0;
940 }
941
942 static const struct udevice_id sun8i_emac_eth_ids[] = {
943 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
944 {.compatible = "allwinner,sun50i-a64-emac",
945 .data = (uintptr_t)A64_EMAC },
946 {.compatible = "allwinner,sun8i-a83t-emac",
947 .data = (uintptr_t)A83T_EMAC },
948 {.compatible = "allwinner,sun8i-r40-gmac",
949 .data = (uintptr_t)R40_GMAC },
950 { }
951 };
952
953 U_BOOT_DRIVER(eth_sun8i_emac) = {
954 .name = "eth_sun8i_emac",
955 .id = UCLASS_ETH,
956 .of_match = sun8i_emac_eth_ids,
957 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
958 .probe = sun8i_emac_eth_probe,
959 .ops = &sun8i_emac_eth_ops,
960 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
961 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
962 .flags = DM_FLAG_ALLOC_PRIV_DMA,
963 };
964