1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * sni_ave.c - Socionext UniPhier AVE ethernet driver 4 * Copyright 2016-2018 Socionext inc. 5 */ 6 7 #include <clk.h> 8 #include <dm.h> 9 #include <fdt_support.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <miiphy.h> 13 #include <net.h> 14 #include <regmap.h> 15 #include <reset.h> 16 #include <syscon.h> 17 18 #define AVE_GRST_DELAY_MSEC 40 19 #define AVE_MIN_XMITSIZE 60 20 #define AVE_SEND_TIMEOUT_COUNT 1000 21 #define AVE_MDIO_TIMEOUT_USEC 10000 22 #define AVE_HALT_TIMEOUT_USEC 10000 23 24 /* General Register Group */ 25 #define AVE_IDR 0x000 /* ID */ 26 #define AVE_VR 0x004 /* Version */ 27 #define AVE_GRR 0x008 /* Global Reset */ 28 #define AVE_CFGR 0x00c /* Configuration */ 29 30 /* Interrupt Register Group */ 31 #define AVE_GIMR 0x100 /* Global Interrupt Mask */ 32 #define AVE_GISR 0x104 /* Global Interrupt Status */ 33 34 /* MAC Register Group */ 35 #define AVE_TXCR 0x200 /* TX Setup */ 36 #define AVE_RXCR 0x204 /* RX Setup */ 37 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */ 38 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */ 39 #define AVE_MDIOCTR 0x214 /* MDIO Control */ 40 #define AVE_MDIOAR 0x218 /* MDIO Address */ 41 #define AVE_MDIOWDR 0x21c /* MDIO Data */ 42 #define AVE_MDIOSR 0x220 /* MDIO Status */ 43 #define AVE_MDIORDR 0x224 /* MDIO Rd Data */ 44 45 /* Descriptor Control Register Group */ 46 #define AVE_DESCC 0x300 /* Descriptor Control */ 47 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */ 48 #define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */ 49 #define AVE_IIRQC 0x34c /* Interval IRQ Control */ 50 51 /* 64bit descriptor memory */ 52 #define AVE_DESC_SIZE_64 12 /* Descriptor Size */ 53 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */ 54 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */ 55 56 /* 32bit descriptor memory */ 57 #define AVE_DESC_SIZE_32 8 /* Descriptor Size */ 58 #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */ 59 #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */ 60 61 /* RMII Bridge Register Group */ 62 #define AVE_RSTCTRL 0x8028 /* Reset control */ 63 #define AVE_RSTCTRL_RMIIRST BIT(16) 64 #define AVE_LINKSEL 0x8034 /* Link speed setting */ 65 #define AVE_LINKSEL_100M BIT(0) 66 67 /* AVE_GRR */ 68 #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ 69 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */ 70 71 /* AVE_CFGR */ 72 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ 73 74 /* AVE_GISR (common with GIMR) */ 75 #define AVE_GIMR_CLR 0 76 #define AVE_GISR_CLR GENMASK(31, 0) 77 78 /* AVE_TXCR */ 79 #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ 80 #define AVE_TXCR_TXSPD_1G BIT(17) 81 #define AVE_TXCR_TXSPD_100 BIT(16) 82 83 /* AVE_RXCR */ 84 #define AVE_RXCR_RXEN BIT(30) /* Rx enable */ 85 #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ 86 #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ 87 88 /* AVE_MDIOCTR */ 89 #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ 90 #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ 91 92 /* AVE_MDIOSR */ 93 #define AVE_MDIOSR_STS BIT(0) /* access status */ 94 95 /* AVE_DESCC */ 96 #define AVE_DESCC_RXDSTPSTS BIT(20) 97 #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ 98 #define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */ 99 #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ 100 101 /* AVE_TXDC/RXDC */ 102 #define AVE_DESC_SIZE(priv, num) \ 103 ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \ 104 AVE_DESC_SIZE_32)) 105 106 /* Command status for descriptor */ 107 #define AVE_STS_OWN BIT(31) /* Descriptor ownership */ 108 #define AVE_STS_OK BIT(27) /* Normal transmit */ 109 #define AVE_STS_1ST BIT(26) /* Head of buffer chain */ 110 #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ 111 #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0) 112 #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0) 113 114 #define AVE_DESC_OFS_CMDSTS 0 115 #define AVE_DESC_OFS_ADDRL 4 116 #define AVE_DESC_OFS_ADDRU 8 117 118 /* Parameter for ethernet frame */ 119 #define AVE_RXCR_MTU 1518 120 121 /* SG */ 122 #define SG_ETPINMODE 0x540 123 #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ 124 #define SG_ETPINMODE_RMII(ins) BIT(ins) 125 126 #define AVE_MAX_CLKS 4 127 #define AVE_MAX_RSTS 2 128 129 enum desc_id { 130 AVE_DESCID_TX, 131 AVE_DESCID_RX, 132 }; 133 134 struct ave_private { 135 phys_addr_t iobase; 136 unsigned int nclks; 137 struct clk clk[AVE_MAX_CLKS]; 138 unsigned int nrsts; 139 struct reset_ctl rst[AVE_MAX_RSTS]; 140 struct regmap *regmap; 141 unsigned int regmap_arg; 142 143 struct mii_dev *bus; 144 struct phy_device *phydev; 145 int phy_mode; 146 int max_speed; 147 148 int rx_pos; 149 int rx_siz; 150 int rx_off; 151 int tx_num; 152 153 u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN]; 154 void *tx_adj_buf; 155 156 const struct ave_soc_data *data; 157 }; 158 159 struct ave_soc_data { 160 bool is_desc_64bit; 161 const char *clock_names[AVE_MAX_CLKS]; 162 const char *reset_names[AVE_MAX_RSTS]; 163 int (*get_pinmode)(struct ave_private *priv); 164 }; 165 166 static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry, 167 int offset) 168 { 169 int desc_size; 170 u32 addr; 171 172 if (priv->data->is_desc_64bit) { 173 desc_size = AVE_DESC_SIZE_64; 174 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; 175 } else { 176 desc_size = AVE_DESC_SIZE_32; 177 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; 178 } 179 180 addr += entry * desc_size + offset; 181 182 return readl(priv->iobase + addr); 183 } 184 185 static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id, 186 int entry) 187 { 188 return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS); 189 } 190 191 static void ave_desc_write(struct ave_private *priv, enum desc_id id, 192 int entry, int offset, u32 val) 193 { 194 int desc_size; 195 u32 addr; 196 197 if (priv->data->is_desc_64bit) { 198 desc_size = AVE_DESC_SIZE_64; 199 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; 200 } else { 201 desc_size = AVE_DESC_SIZE_32; 202 addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; 203 } 204 205 addr += entry * desc_size + offset; 206 writel(val, priv->iobase + addr); 207 } 208 209 static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id, 210 int entry, u32 val) 211 { 212 ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val); 213 } 214 215 static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id, 216 int entry, uintptr_t paddr) 217 { 218 ave_desc_write(priv, id, entry, 219 AVE_DESC_OFS_ADDRL, lower_32_bits(paddr)); 220 if (priv->data->is_desc_64bit) 221 ave_desc_write(priv, id, entry, 222 AVE_DESC_OFS_ADDRU, upper_32_bits(paddr)); 223 } 224 225 static void ave_cache_invalidate(uintptr_t vaddr, int len) 226 { 227 invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), 228 roundup(vaddr + len, ARCH_DMA_MINALIGN)); 229 } 230 231 static void ave_cache_flush(uintptr_t vaddr, int len) 232 { 233 flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), 234 roundup(vaddr + len, ARCH_DMA_MINALIGN)); 235 } 236 237 static int ave_mdiobus_read(struct mii_dev *bus, 238 int phyid, int devad, int regnum) 239 { 240 struct ave_private *priv = bus->priv; 241 u32 mdioctl, mdiosr; 242 int ret; 243 244 /* write address */ 245 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); 246 247 /* read request */ 248 mdioctl = readl(priv->iobase + AVE_MDIOCTR); 249 writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR); 250 251 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, 252 !(mdiosr & AVE_MDIOSR_STS), 253 AVE_MDIO_TIMEOUT_USEC); 254 if (ret) { 255 pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n", 256 priv->phydev->dev->name, phyid, regnum); 257 return ret; 258 } 259 260 return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0); 261 } 262 263 static int ave_mdiobus_write(struct mii_dev *bus, 264 int phyid, int devad, int regnum, u16 val) 265 { 266 struct ave_private *priv = bus->priv; 267 u32 mdioctl, mdiosr; 268 int ret; 269 270 /* write address */ 271 writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); 272 273 /* write data */ 274 writel(val, priv->iobase + AVE_MDIOWDR); 275 276 /* write request */ 277 mdioctl = readl(priv->iobase + AVE_MDIOCTR); 278 writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ, 279 priv->iobase + AVE_MDIOCTR); 280 281 ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, 282 !(mdiosr & AVE_MDIOSR_STS), 283 AVE_MDIO_TIMEOUT_USEC); 284 if (ret) 285 pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n", 286 priv->phydev->dev->name, phyid, regnum); 287 288 return ret; 289 } 290 291 static int ave_adjust_link(struct ave_private *priv) 292 { 293 struct phy_device *phydev = priv->phydev; 294 struct eth_pdata *pdata = dev_get_platdata(phydev->dev); 295 u32 val, txcr, rxcr, rxcr_org; 296 u16 rmt_adv = 0, lcl_adv = 0; 297 u8 cap; 298 299 /* set RGMII speed */ 300 val = readl(priv->iobase + AVE_TXCR); 301 val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); 302 303 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) 304 val |= AVE_TXCR_TXSPD_1G; 305 else if (phydev->speed == SPEED_100) 306 val |= AVE_TXCR_TXSPD_100; 307 308 writel(val, priv->iobase + AVE_TXCR); 309 310 /* set RMII speed (100M/10M only) */ 311 if (!phy_interface_is_rgmii(phydev)) { 312 val = readl(priv->iobase + AVE_LINKSEL); 313 if (phydev->speed == SPEED_10) 314 val &= ~AVE_LINKSEL_100M; 315 else 316 val |= AVE_LINKSEL_100M; 317 writel(val, priv->iobase + AVE_LINKSEL); 318 } 319 320 /* check current RXCR/TXCR */ 321 rxcr = readl(priv->iobase + AVE_RXCR); 322 txcr = readl(priv->iobase + AVE_TXCR); 323 rxcr_org = rxcr; 324 325 if (phydev->duplex) { 326 rxcr |= AVE_RXCR_FDUPEN; 327 328 if (phydev->pause) 329 rmt_adv |= LPA_PAUSE_CAP; 330 if (phydev->asym_pause) 331 rmt_adv |= LPA_PAUSE_ASYM; 332 if (phydev->advertising & ADVERTISED_Pause) 333 lcl_adv |= ADVERTISE_PAUSE_CAP; 334 if (phydev->advertising & ADVERTISED_Asym_Pause) 335 lcl_adv |= ADVERTISE_PAUSE_ASYM; 336 337 cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 338 if (cap & FLOW_CTRL_TX) 339 txcr |= AVE_TXCR_FLOCTR; 340 else 341 txcr &= ~AVE_TXCR_FLOCTR; 342 if (cap & FLOW_CTRL_RX) 343 rxcr |= AVE_RXCR_FLOCTR; 344 else 345 rxcr &= ~AVE_RXCR_FLOCTR; 346 } else { 347 rxcr &= ~AVE_RXCR_FDUPEN; 348 rxcr &= ~AVE_RXCR_FLOCTR; 349 txcr &= ~AVE_TXCR_FLOCTR; 350 } 351 352 if (rxcr_org != rxcr) { 353 /* disable Rx mac */ 354 writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR); 355 /* change and enable TX/Rx mac */ 356 writel(txcr, priv->iobase + AVE_TXCR); 357 writel(rxcr, priv->iobase + AVE_RXCR); 358 } 359 360 pr_notice("%s: phy:%s speed:%d mac:%pM\n", 361 phydev->dev->name, phydev->drv->name, phydev->speed, 362 pdata->enetaddr); 363 364 return phydev->link; 365 } 366 367 static int ave_mdiobus_init(struct ave_private *priv, const char *name) 368 { 369 struct mii_dev *bus = mdio_alloc(); 370 371 if (!bus) 372 return -ENOMEM; 373 374 bus->read = ave_mdiobus_read; 375 bus->write = ave_mdiobus_write; 376 snprintf(bus->name, sizeof(bus->name), "%s", name); 377 bus->priv = priv; 378 379 return mdio_register(bus); 380 } 381 382 static int ave_phy_init(struct ave_private *priv, void *dev) 383 { 384 struct phy_device *phydev; 385 int mask = GENMASK(31, 0), ret; 386 387 phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode); 388 if (!phydev) 389 return -ENODEV; 390 391 phy_connect_dev(phydev, dev); 392 393 phydev->supported &= PHY_GBIT_FEATURES; 394 if (priv->max_speed) { 395 ret = phy_set_supported(phydev, priv->max_speed); 396 if (ret) 397 return ret; 398 } 399 phydev->advertising = phydev->supported; 400 401 priv->phydev = phydev; 402 phy_config(phydev); 403 404 return 0; 405 } 406 407 static void ave_stop(struct udevice *dev) 408 { 409 struct ave_private *priv = dev_get_priv(dev); 410 u32 val; 411 int ret; 412 413 val = readl(priv->iobase + AVE_GRR); 414 if (val) 415 return; 416 417 val = readl(priv->iobase + AVE_RXCR); 418 val &= ~AVE_RXCR_RXEN; 419 writel(val, priv->iobase + AVE_RXCR); 420 421 writel(0, priv->iobase + AVE_DESCC); 422 ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val, 423 AVE_HALT_TIMEOUT_USEC); 424 if (ret) 425 pr_warn("%s: halt timeout\n", priv->phydev->dev->name); 426 427 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); 428 429 phy_shutdown(priv->phydev); 430 } 431 432 static void ave_reset(struct ave_private *priv) 433 { 434 u32 val; 435 436 /* reset RMII register */ 437 val = readl(priv->iobase + AVE_RSTCTRL); 438 val &= ~AVE_RSTCTRL_RMIIRST; 439 writel(val, priv->iobase + AVE_RSTCTRL); 440 441 /* assert reset */ 442 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR); 443 mdelay(AVE_GRST_DELAY_MSEC); 444 445 /* 1st, negate PHY reset only */ 446 writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); 447 mdelay(AVE_GRST_DELAY_MSEC); 448 449 /* negate reset */ 450 writel(0, priv->iobase + AVE_GRR); 451 mdelay(AVE_GRST_DELAY_MSEC); 452 453 /* negate RMII register */ 454 val = readl(priv->iobase + AVE_RSTCTRL); 455 val |= AVE_RSTCTRL_RMIIRST; 456 writel(val, priv->iobase + AVE_RSTCTRL); 457 } 458 459 static int ave_start(struct udevice *dev) 460 { 461 struct ave_private *priv = dev_get_priv(dev); 462 uintptr_t paddr; 463 u32 val; 464 int i; 465 466 ave_reset(priv); 467 468 priv->rx_pos = 0; 469 priv->rx_off = 2; /* RX data has 2byte offsets */ 470 priv->tx_num = 0; 471 priv->tx_adj_buf = 472 (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0], 473 PKTALIGN); 474 priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off); 475 476 val = 0; 477 if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII) 478 val |= AVE_CFGR_MII; 479 writel(val, priv->iobase + AVE_CFGR); 480 481 /* use one descriptor for Tx */ 482 writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC); 483 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0); 484 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0); 485 486 /* use PKTBUFSRX descriptors for Rx */ 487 writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC); 488 for (i = 0; i < PKTBUFSRX; i++) { 489 paddr = (uintptr_t)net_rx_packets[i]; 490 ave_cache_flush(paddr, priv->rx_siz + priv->rx_off); 491 ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr); 492 ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz); 493 } 494 495 writel(AVE_GISR_CLR, priv->iobase + AVE_GISR); 496 writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR); 497 498 writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU, 499 priv->iobase + AVE_RXCR); 500 writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC); 501 502 phy_startup(priv->phydev); 503 ave_adjust_link(priv); 504 505 return 0; 506 } 507 508 static int ave_write_hwaddr(struct udevice *dev) 509 { 510 struct ave_private *priv = dev_get_priv(dev); 511 struct eth_pdata *pdata = dev_get_platdata(dev); 512 u8 *mac = pdata->enetaddr; 513 514 writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, 515 priv->iobase + AVE_RXMAC1R); 516 writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R); 517 518 return 0; 519 } 520 521 static int ave_send(struct udevice *dev, void *packet, int length) 522 { 523 struct ave_private *priv = dev_get_priv(dev); 524 u32 val; 525 void *ptr = packet; 526 int count; 527 528 /* adjust alignment for descriptor */ 529 if ((uintptr_t)ptr & 0x3) { 530 memcpy(priv->tx_adj_buf, (const void *)ptr, length); 531 ptr = priv->tx_adj_buf; 532 } 533 534 /* padding for minimum length */ 535 if (length < AVE_MIN_XMITSIZE) { 536 memset(ptr + length, 0, AVE_MIN_XMITSIZE - length); 537 length = AVE_MIN_XMITSIZE; 538 } 539 540 /* check ownership and wait for previous xmit done */ 541 count = AVE_SEND_TIMEOUT_COUNT; 542 do { 543 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); 544 } while ((val & AVE_STS_OWN) && --count); 545 if (!count) 546 return -ETIMEDOUT; 547 548 ave_cache_flush((uintptr_t)ptr, length); 549 ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr); 550 551 val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST | 552 (length & AVE_STS_PKTLEN_TX_MASK); 553 ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val); 554 priv->tx_num++; 555 556 count = AVE_SEND_TIMEOUT_COUNT; 557 do { 558 val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); 559 } while ((val & AVE_STS_OWN) && --count); 560 if (!count) 561 return -ETIMEDOUT; 562 563 if (!(val & AVE_STS_OK)) 564 pr_warn("%s: bad send packet status:%08x\n", 565 priv->phydev->dev->name, le32_to_cpu(val)); 566 567 return 0; 568 } 569 570 static int ave_recv(struct udevice *dev, int flags, uchar **packetp) 571 { 572 struct ave_private *priv = dev_get_priv(dev); 573 uchar *ptr; 574 int length = 0; 575 u32 cmdsts; 576 577 while (1) { 578 cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX, 579 priv->rx_pos); 580 if (!(cmdsts & AVE_STS_OWN)) 581 /* hardware ownership, no received packets */ 582 return -EAGAIN; 583 584 ptr = net_rx_packets[priv->rx_pos] + priv->rx_off; 585 if (cmdsts & AVE_STS_OK) 586 break; 587 588 pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n", 589 priv->phydev->dev->name, priv->rx_pos, 590 le32_to_cpu(cmdsts), ptr); 591 } 592 593 length = cmdsts & AVE_STS_PKTLEN_RX_MASK; 594 595 /* invalidate after DMA is done */ 596 ave_cache_invalidate((uintptr_t)ptr, length); 597 *packetp = ptr; 598 599 return length; 600 } 601 602 static int ave_free_packet(struct udevice *dev, uchar *packet, int length) 603 { 604 struct ave_private *priv = dev_get_priv(dev); 605 606 ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos], 607 priv->rx_siz + priv->rx_off); 608 609 ave_desc_write_cmdsts(priv, AVE_DESCID_RX, 610 priv->rx_pos, priv->rx_siz); 611 612 if (++priv->rx_pos >= PKTBUFSRX) 613 priv->rx_pos = 0; 614 615 return 0; 616 } 617 618 static int ave_pro4_get_pinmode(struct ave_private *priv) 619 { 620 u32 reg, mask, val = 0; 621 622 if (priv->regmap_arg > 0) 623 return -EINVAL; 624 625 mask = SG_ETPINMODE_RMII(0); 626 627 switch (priv->phy_mode) { 628 case PHY_INTERFACE_MODE_RMII: 629 val = SG_ETPINMODE_RMII(0); 630 break; 631 case PHY_INTERFACE_MODE_MII: 632 case PHY_INTERFACE_MODE_RGMII: 633 break; 634 default: 635 return -EINVAL; 636 } 637 638 regmap_read(priv->regmap, SG_ETPINMODE, ®); 639 reg &= ~mask; 640 reg |= val; 641 regmap_write(priv->regmap, SG_ETPINMODE, reg); 642 643 return 0; 644 } 645 646 static int ave_ld11_get_pinmode(struct ave_private *priv) 647 { 648 u32 reg, mask, val = 0; 649 650 if (priv->regmap_arg > 0) 651 return -EINVAL; 652 653 mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 654 655 switch (priv->phy_mode) { 656 case PHY_INTERFACE_MODE_INTERNAL: 657 break; 658 case PHY_INTERFACE_MODE_RMII: 659 val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); 660 break; 661 default: 662 return -EINVAL; 663 } 664 665 regmap_read(priv->regmap, SG_ETPINMODE, ®); 666 reg &= ~mask; 667 reg |= val; 668 regmap_write(priv->regmap, SG_ETPINMODE, reg); 669 670 return 0; 671 } 672 673 static int ave_ld20_get_pinmode(struct ave_private *priv) 674 { 675 u32 reg, mask, val = 0; 676 677 if (priv->regmap_arg > 0) 678 return -EINVAL; 679 680 mask = SG_ETPINMODE_RMII(0); 681 682 switch (priv->phy_mode) { 683 case PHY_INTERFACE_MODE_RMII: 684 val = SG_ETPINMODE_RMII(0); 685 break; 686 case PHY_INTERFACE_MODE_RGMII: 687 break; 688 default: 689 return -EINVAL; 690 } 691 692 regmap_read(priv->regmap, SG_ETPINMODE, ®); 693 reg &= ~mask; 694 reg |= val; 695 regmap_write(priv->regmap, SG_ETPINMODE, reg); 696 697 return 0; 698 } 699 700 static int ave_pxs3_get_pinmode(struct ave_private *priv) 701 { 702 u32 reg, mask, val = 0; 703 704 if (priv->regmap_arg > 1) 705 return -EINVAL; 706 707 mask = SG_ETPINMODE_RMII(priv->regmap_arg); 708 709 switch (priv->phy_mode) { 710 case PHY_INTERFACE_MODE_RMII: 711 val = SG_ETPINMODE_RMII(priv->regmap_arg); 712 break; 713 case PHY_INTERFACE_MODE_RGMII: 714 break; 715 default: 716 return -EINVAL; 717 } 718 719 regmap_read(priv->regmap, SG_ETPINMODE, ®); 720 reg &= ~mask; 721 reg |= val; 722 regmap_write(priv->regmap, SG_ETPINMODE, reg); 723 724 return 0; 725 } 726 727 static int ave_ofdata_to_platdata(struct udevice *dev) 728 { 729 struct eth_pdata *pdata = dev_get_platdata(dev); 730 struct ave_private *priv = dev_get_priv(dev); 731 struct ofnode_phandle_args args; 732 const char *phy_mode; 733 const u32 *valp; 734 int ret, nc, nr; 735 const char *name; 736 737 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); 738 if (!priv->data) 739 return -EINVAL; 740 741 pdata->iobase = devfdt_get_addr(dev); 742 pdata->phy_interface = -1; 743 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 744 NULL); 745 if (phy_mode) 746 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 747 if (pdata->phy_interface == -1) { 748 dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); 749 return -EINVAL; 750 } 751 752 pdata->max_speed = 0; 753 valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", 754 NULL); 755 if (valp) 756 pdata->max_speed = fdt32_to_cpu(*valp); 757 758 for (nc = 0; nc < AVE_MAX_CLKS; nc++) { 759 name = priv->data->clock_names[nc]; 760 if (!name) 761 break; 762 ret = clk_get_by_name(dev, name, &priv->clk[nc]); 763 if (ret) { 764 dev_err(dev, "Failed to get clocks property: %d\n", 765 ret); 766 goto out_clk_free; 767 } 768 priv->nclks++; 769 } 770 771 for (nr = 0; nr < AVE_MAX_RSTS; nr++) { 772 name = priv->data->reset_names[nr]; 773 if (!name) 774 break; 775 ret = reset_get_by_name(dev, name, &priv->rst[nr]); 776 if (ret) { 777 dev_err(dev, "Failed to get resets property: %d\n", 778 ret); 779 goto out_reset_free; 780 } 781 priv->nrsts++; 782 } 783 784 ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode", 785 NULL, 1, 0, &args); 786 if (ret) { 787 dev_err(dev, "Failed to get syscon-phy-mode property: %d\n", 788 ret); 789 goto out_reset_free; 790 } 791 792 priv->regmap = syscon_node_to_regmap(args.node); 793 if (IS_ERR(priv->regmap)) { 794 ret = PTR_ERR(priv->regmap); 795 dev_err(dev, "can't get syscon: %d\n", ret); 796 goto out_reset_free; 797 } 798 799 if (args.args_count != 1) { 800 ret = -EINVAL; 801 dev_err(dev, "Invalid argument of syscon-phy-mode\n"); 802 goto out_reset_free; 803 } 804 805 priv->regmap_arg = args.args[0]; 806 807 return 0; 808 809 out_reset_free: 810 while (--nr >= 0) 811 reset_free(&priv->rst[nr]); 812 out_clk_free: 813 while (--nc >= 0) 814 clk_free(&priv->clk[nc]); 815 816 return ret; 817 } 818 819 static int ave_probe(struct udevice *dev) 820 { 821 struct eth_pdata *pdata = dev_get_platdata(dev); 822 struct ave_private *priv = dev_get_priv(dev); 823 int ret, nc, nr; 824 825 priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); 826 if (!priv->data) 827 return -EINVAL; 828 829 priv->iobase = pdata->iobase; 830 priv->phy_mode = pdata->phy_interface; 831 priv->max_speed = pdata->max_speed; 832 833 ret = priv->data->get_pinmode(priv); 834 if (ret) { 835 dev_err(dev, "Invalid phy-mode\n"); 836 return -EINVAL; 837 } 838 839 for (nc = 0; nc < priv->nclks; nc++) { 840 ret = clk_enable(&priv->clk[nc]); 841 if (ret) { 842 dev_err(dev, "Failed to enable clk: %d\n", ret); 843 goto out_clk_release; 844 } 845 } 846 847 for (nr = 0; nr < priv->nrsts; nr++) { 848 ret = reset_deassert(&priv->rst[nr]); 849 if (ret) { 850 dev_err(dev, "Failed to deassert reset: %d\n", ret); 851 goto out_reset_release; 852 } 853 } 854 855 ave_reset(priv); 856 857 ret = ave_mdiobus_init(priv, dev->name); 858 if (ret) { 859 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); 860 goto out_reset_release; 861 } 862 863 priv->bus = miiphy_get_dev_by_name(dev->name); 864 865 ret = ave_phy_init(priv, dev); 866 if (ret) { 867 dev_err(dev, "Failed to initialize phy: %d\n", ret); 868 goto out_mdiobus_release; 869 } 870 871 return 0; 872 873 out_mdiobus_release: 874 mdio_unregister(priv->bus); 875 mdio_free(priv->bus); 876 out_reset_release: 877 reset_release_all(priv->rst, nr); 878 out_clk_release: 879 clk_release_all(priv->clk, nc); 880 881 return ret; 882 } 883 884 static int ave_remove(struct udevice *dev) 885 { 886 struct ave_private *priv = dev_get_priv(dev); 887 888 free(priv->phydev); 889 mdio_unregister(priv->bus); 890 mdio_free(priv->bus); 891 reset_release_all(priv->rst, priv->nrsts); 892 clk_release_all(priv->clk, priv->nclks); 893 894 return 0; 895 } 896 897 static const struct eth_ops ave_ops = { 898 .start = ave_start, 899 .stop = ave_stop, 900 .send = ave_send, 901 .recv = ave_recv, 902 .free_pkt = ave_free_packet, 903 .write_hwaddr = ave_write_hwaddr, 904 }; 905 906 static const struct ave_soc_data ave_pro4_data = { 907 .is_desc_64bit = false, 908 .clock_names = { 909 "gio", "ether", "ether-gb", "ether-phy", 910 }, 911 .reset_names = { 912 "gio", "ether", 913 }, 914 .get_pinmode = ave_pro4_get_pinmode, 915 }; 916 917 static const struct ave_soc_data ave_pxs2_data = { 918 .is_desc_64bit = false, 919 .clock_names = { 920 "ether", 921 }, 922 .reset_names = { 923 "ether", 924 }, 925 .get_pinmode = ave_pro4_get_pinmode, 926 }; 927 928 static const struct ave_soc_data ave_ld11_data = { 929 .is_desc_64bit = false, 930 .clock_names = { 931 "ether", 932 }, 933 .reset_names = { 934 "ether", 935 }, 936 .get_pinmode = ave_ld11_get_pinmode, 937 }; 938 939 static const struct ave_soc_data ave_ld20_data = { 940 .is_desc_64bit = true, 941 .clock_names = { 942 "ether", 943 }, 944 .reset_names = { 945 "ether", 946 }, 947 .get_pinmode = ave_ld20_get_pinmode, 948 }; 949 950 static const struct ave_soc_data ave_pxs3_data = { 951 .is_desc_64bit = false, 952 .clock_names = { 953 "ether", 954 }, 955 .reset_names = { 956 "ether", 957 }, 958 .get_pinmode = ave_pxs3_get_pinmode, 959 }; 960 961 static const struct udevice_id ave_ids[] = { 962 { 963 .compatible = "socionext,uniphier-pro4-ave4", 964 .data = (ulong)&ave_pro4_data, 965 }, 966 { 967 .compatible = "socionext,uniphier-pxs2-ave4", 968 .data = (ulong)&ave_pxs2_data, 969 }, 970 { 971 .compatible = "socionext,uniphier-ld11-ave4", 972 .data = (ulong)&ave_ld11_data, 973 }, 974 { 975 .compatible = "socionext,uniphier-ld20-ave4", 976 .data = (ulong)&ave_ld20_data, 977 }, 978 { 979 .compatible = "socionext,uniphier-pxs3-ave4", 980 .data = (ulong)&ave_pxs3_data, 981 }, 982 { /* Sentinel */ } 983 }; 984 985 U_BOOT_DRIVER(ave) = { 986 .name = "ave", 987 .id = UCLASS_ETH, 988 .of_match = ave_ids, 989 .probe = ave_probe, 990 .remove = ave_remove, 991 .ofdata_to_platdata = ave_ofdata_to_platdata, 992 .ops = &ave_ops, 993 .priv_auto_alloc_size = sizeof(struct ave_private), 994 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 995 }; 996