1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * SMSC LAN9[12]1[567] Network driver 4 * 5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 */ 7 8 #ifndef _SMC911X_H_ 9 #define _SMC911X_H_ 10 11 #include <linux/types.h> 12 13 #define DRIVERNAME "smc911x" 14 15 #if defined (CONFIG_SMC911X_32_BIT) && \ 16 defined (CONFIG_SMC911X_16_BIT) 17 #error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \ 18 CONFIG_SMC911X_16_BIT shall be set" 19 #endif 20 21 #if defined (CONFIG_SMC911X_32_BIT) 22 static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset) 23 { 24 return *(volatile u32*)(dev->iobase + offset); 25 } 26 u32 smc911x_reg_read(struct eth_device *dev, u32 offset) 27 __attribute__((weak, alias("__smc911x_reg_read"))); 28 29 static inline void __smc911x_reg_write(struct eth_device *dev, 30 u32 offset, u32 val) 31 { 32 *(volatile u32*)(dev->iobase + offset) = val; 33 } 34 void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val) 35 __attribute__((weak, alias("__smc911x_reg_write"))); 36 #elif defined (CONFIG_SMC911X_16_BIT) 37 static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset) 38 { 39 volatile u16 *addr_16 = (u16 *)(dev->iobase + offset); 40 return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); 41 } 42 static inline void smc911x_reg_write(struct eth_device *dev, 43 u32 offset, u32 val) 44 { 45 *(volatile u16 *)(dev->iobase + offset) = (u16)val; 46 *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16); 47 } 48 #else 49 #error "SMC911X: undefined bus width" 50 #endif /* CONFIG_SMC911X_16_BIT */ 51 52 /* Below are the register offsets and bit definitions 53 * of the Lan911x memory space 54 */ 55 #define RX_DATA_FIFO 0x00 56 57 #define TX_DATA_FIFO 0x20 58 #define TX_CMD_A_INT_ON_COMP 0x80000000 59 #define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 60 #define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 61 #define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000 62 #define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000 63 #define TX_CMD_A_INT_DATA_OFFSET 0x001F0000 64 #define TX_CMD_A_INT_FIRST_SEG 0x00002000 65 #define TX_CMD_A_INT_LAST_SEG 0x00001000 66 #define TX_CMD_A_BUF_SIZE 0x000007FF 67 #define TX_CMD_B_PKT_TAG 0xFFFF0000 68 #define TX_CMD_B_ADD_CRC_DISABLE 0x00002000 69 #define TX_CMD_B_DISABLE_PADDING 0x00001000 70 #define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF 71 72 #define RX_STATUS_FIFO 0x40 73 #define RX_STS_PKT_LEN 0x3FFF0000 74 #define RX_STS_ES 0x00008000 75 #define RX_STS_BCST 0x00002000 76 #define RX_STS_LEN_ERR 0x00001000 77 #define RX_STS_RUNT_ERR 0x00000800 78 #define RX_STS_MCAST 0x00000400 79 #define RX_STS_TOO_LONG 0x00000080 80 #define RX_STS_COLL 0x00000040 81 #define RX_STS_ETH_TYPE 0x00000020 82 #define RX_STS_WDOG_TMT 0x00000010 83 #define RX_STS_MII_ERR 0x00000008 84 #define RX_STS_DRIBBLING 0x00000004 85 #define RX_STS_CRC_ERR 0x00000002 86 #define RX_STATUS_FIFO_PEEK 0x44 87 #define TX_STATUS_FIFO 0x48 88 #define TX_STS_TAG 0xFFFF0000 89 #define TX_STS_ES 0x00008000 90 #define TX_STS_LOC 0x00000800 91 #define TX_STS_NO_CARR 0x00000400 92 #define TX_STS_LATE_COLL 0x00000200 93 #define TX_STS_MANY_COLL 0x00000100 94 #define TX_STS_COLL_CNT 0x00000078 95 #define TX_STS_MANY_DEFER 0x00000004 96 #define TX_STS_UNDERRUN 0x00000002 97 #define TX_STS_DEFERRED 0x00000001 98 #define TX_STATUS_FIFO_PEEK 0x4C 99 #define ID_REV 0x50 100 #define ID_REV_CHIP_ID 0xFFFF0000 /* RO */ 101 #define ID_REV_REV_ID 0x0000FFFF /* RO */ 102 103 #define INT_CFG 0x54 104 #define INT_CFG_INT_DEAS 0xFF000000 /* R/W */ 105 #define INT_CFG_INT_DEAS_CLR 0x00004000 106 #define INT_CFG_INT_DEAS_STS 0x00002000 107 #define INT_CFG_IRQ_INT 0x00001000 /* RO */ 108 #define INT_CFG_IRQ_EN 0x00000100 /* R/W */ 109 /* R/W Not Affected by SW Reset */ 110 #define INT_CFG_IRQ_POL 0x00000010 111 /* R/W Not Affected by SW Reset */ 112 #define INT_CFG_IRQ_TYPE 0x00000001 113 114 #define INT_STS 0x58 115 #define INT_STS_SW_INT 0x80000000 /* R/WC */ 116 #define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */ 117 #define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */ 118 #define INT_STS_RXDFH_INT 0x00800000 /* R/WC */ 119 #define INT_STS_RXDF_INT 0x00400000 /* R/WC */ 120 #define INT_STS_TX_IOC 0x00200000 /* R/WC */ 121 #define INT_STS_RXD_INT 0x00100000 /* R/WC */ 122 #define INT_STS_GPT_INT 0x00080000 /* R/WC */ 123 #define INT_STS_PHY_INT 0x00040000 /* RO */ 124 #define INT_STS_PME_INT 0x00020000 /* R/WC */ 125 #define INT_STS_TXSO 0x00010000 /* R/WC */ 126 #define INT_STS_RWT 0x00008000 /* R/WC */ 127 #define INT_STS_RXE 0x00004000 /* R/WC */ 128 #define INT_STS_TXE 0x00002000 /* R/WC */ 129 /*#define INT_STS_ERX 0x00001000*/ /* R/WC */ 130 #define INT_STS_TDFU 0x00000800 /* R/WC */ 131 #define INT_STS_TDFO 0x00000400 /* R/WC */ 132 #define INT_STS_TDFA 0x00000200 /* R/WC */ 133 #define INT_STS_TSFF 0x00000100 /* R/WC */ 134 #define INT_STS_TSFL 0x00000080 /* R/WC */ 135 /*#define INT_STS_RXDF 0x00000040*/ /* R/WC */ 136 #define INT_STS_RDFO 0x00000040 /* R/WC */ 137 #define INT_STS_RDFL 0x00000020 /* R/WC */ 138 #define INT_STS_RSFF 0x00000010 /* R/WC */ 139 #define INT_STS_RSFL 0x00000008 /* R/WC */ 140 #define INT_STS_GPIO2_INT 0x00000004 /* R/WC */ 141 #define INT_STS_GPIO1_INT 0x00000002 /* R/WC */ 142 #define INT_STS_GPIO0_INT 0x00000001 /* R/WC */ 143 #define INT_EN 0x5C 144 #define INT_EN_SW_INT_EN 0x80000000 /* R/W */ 145 #define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */ 146 #define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */ 147 #define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */ 148 /*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */ 149 #define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */ 150 #define INT_EN_RXD_INT_EN 0x00100000 /* R/W */ 151 #define INT_EN_GPT_INT_EN 0x00080000 /* R/W */ 152 #define INT_EN_PHY_INT_EN 0x00040000 /* R/W */ 153 #define INT_EN_PME_INT_EN 0x00020000 /* R/W */ 154 #define INT_EN_TXSO_EN 0x00010000 /* R/W */ 155 #define INT_EN_RWT_EN 0x00008000 /* R/W */ 156 #define INT_EN_RXE_EN 0x00004000 /* R/W */ 157 #define INT_EN_TXE_EN 0x00002000 /* R/W */ 158 /*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */ 159 #define INT_EN_TDFU_EN 0x00000800 /* R/W */ 160 #define INT_EN_TDFO_EN 0x00000400 /* R/W */ 161 #define INT_EN_TDFA_EN 0x00000200 /* R/W */ 162 #define INT_EN_TSFF_EN 0x00000100 /* R/W */ 163 #define INT_EN_TSFL_EN 0x00000080 /* R/W */ 164 /*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */ 165 #define INT_EN_RDFO_EN 0x00000040 /* R/W */ 166 #define INT_EN_RDFL_EN 0x00000020 /* R/W */ 167 #define INT_EN_RSFF_EN 0x00000010 /* R/W */ 168 #define INT_EN_RSFL_EN 0x00000008 /* R/W */ 169 #define INT_EN_GPIO2_INT 0x00000004 /* R/W */ 170 #define INT_EN_GPIO1_INT 0x00000002 /* R/W */ 171 #define INT_EN_GPIO0_INT 0x00000001 /* R/W */ 172 173 #define BYTE_TEST 0x64 174 #define FIFO_INT 0x68 175 #define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */ 176 #define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */ 177 #define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */ 178 #define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */ 179 180 #define RX_CFG 0x6C 181 #define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */ 182 #define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */ 183 #define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */ 184 #define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */ 185 #define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */ 186 #define RX_CFG_RX_DUMP 0x00008000 /* R/W */ 187 #define RX_CFG_RXDOFF 0x00001F00 /* R/W */ 188 /*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */ 189 190 #define TX_CFG 0x70 191 /*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */ 192 /* R/W Self Clearing */ 193 /*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ 194 #define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */ 195 #define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */ 196 #define TX_CFG_TXSAO 0x00000004 /* R/W */ 197 #define TX_CFG_TX_ON 0x00000002 /* R/W */ 198 #define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */ 199 200 #define HW_CFG 0x74 201 #define HW_CFG_TTM 0x00200000 /* R/W */ 202 #define HW_CFG_SF 0x00100000 /* R/W */ 203 #define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */ 204 #define HW_CFG_TR 0x00003000 /* R/W */ 205 #define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */ 206 #define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ 207 #define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ 208 #define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ 209 #define HW_CFG_SMI_SEL 0x00000010 /* R/W */ 210 #define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */ 211 #define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */ 212 #define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */ 213 #define HW_CFG_SRST_TO 0x00000002 /* RO */ 214 #define HW_CFG_SRST 0x00000001 /* Self Clearing */ 215 216 #define RX_DP_CTRL 0x78 217 #define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */ 218 #define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */ 219 220 #define RX_FIFO_INF 0x7C 221 #define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */ 222 #define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */ 223 224 #define TX_FIFO_INF 0x80 225 #define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */ 226 #define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */ 227 228 #define PMT_CTRL 0x84 229 #define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */ 230 #define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */ 231 #define PMT_CTRL_WOL_EN 0x00000200 /* R/W */ 232 #define PMT_CTRL_ED_EN 0x00000100 /* R/W */ 233 /* R/W Not Affected by SW Reset */ 234 #define PMT_CTRL_PME_TYPE 0x00000040 235 #define PMT_CTRL_WUPS 0x00000030 /* R/WC */ 236 #define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */ 237 #define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */ 238 #define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */ 239 #define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */ 240 #define PMT_CTRL_PME_IND 0x00000008 /* R/W */ 241 #define PMT_CTRL_PME_POL 0x00000004 /* R/W */ 242 /* R/W Not Affected by SW Reset */ 243 #define PMT_CTRL_PME_EN 0x00000002 244 #define PMT_CTRL_READY 0x00000001 /* RO */ 245 246 #define GPIO_CFG 0x88 247 #define GPIO_CFG_LED3_EN 0x40000000 /* R/W */ 248 #define GPIO_CFG_LED2_EN 0x20000000 /* R/W */ 249 #define GPIO_CFG_LED1_EN 0x10000000 /* R/W */ 250 #define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */ 251 #define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */ 252 #define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */ 253 #define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */ 254 #define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */ 255 #define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */ 256 #define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */ 257 #define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */ 258 #define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */ 259 #define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */ 260 #define GPIO_CFG_GPIOD4 0x00000010 /* R/W */ 261 #define GPIO_CFG_GPIOD3 0x00000008 /* R/W */ 262 #define GPIO_CFG_GPIOD2 0x00000004 /* R/W */ 263 #define GPIO_CFG_GPIOD1 0x00000002 /* R/W */ 264 #define GPIO_CFG_GPIOD0 0x00000001 /* R/W */ 265 266 #define GPT_CFG 0x8C 267 #define GPT_CFG_TIMER_EN 0x20000000 /* R/W */ 268 #define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */ 269 270 #define GPT_CNT 0x90 271 #define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */ 272 273 #define ENDIAN 0x98 274 #define FREE_RUN 0x9C 275 #define RX_DROP 0xA0 276 #define MAC_CSR_CMD 0xA4 277 #define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */ 278 #define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */ 279 #define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */ 280 281 #define MAC_CSR_DATA 0xA8 282 #define AFC_CFG 0xAC 283 #define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */ 284 #define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */ 285 #define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */ 286 #define AFC_CFG_FCMULT 0x00000008 /* R/W */ 287 #define AFC_CFG_FCBRD 0x00000004 /* R/W */ 288 #define AFC_CFG_FCADD 0x00000002 /* R/W */ 289 #define AFC_CFG_FCANY 0x00000001 /* R/W */ 290 291 #define E2P_CMD 0xB0 292 #define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */ 293 #define E2P_CMD_EPC_CMD 0x70000000 /* R/W */ 294 #define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */ 295 #define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */ 296 #define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */ 297 #define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */ 298 #define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */ 299 #define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */ 300 #define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */ 301 #define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */ 302 #define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */ 303 #define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */ 304 #define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */ 305 306 #define E2P_DATA 0xB4 307 #define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */ 308 /* end of LAN register offsets and bit definitions */ 309 310 /* MAC Control and Status registers */ 311 #define MAC_CR 0x01 /* R/W */ 312 313 /* MAC_CR - MAC Control Register */ 314 #define MAC_CR_RXALL 0x80000000 315 /* TODO: delete this bit? It is not described in the data sheet. */ 316 #define MAC_CR_HBDIS 0x10000000 317 #define MAC_CR_RCVOWN 0x00800000 318 #define MAC_CR_LOOPBK 0x00200000 319 #define MAC_CR_FDPX 0x00100000 320 #define MAC_CR_MCPAS 0x00080000 321 #define MAC_CR_PRMS 0x00040000 322 #define MAC_CR_INVFILT 0x00020000 323 #define MAC_CR_PASSBAD 0x00010000 324 #define MAC_CR_HFILT 0x00008000 325 #define MAC_CR_HPFILT 0x00002000 326 #define MAC_CR_LCOLL 0x00001000 327 #define MAC_CR_BCAST 0x00000800 328 #define MAC_CR_DISRTY 0x00000400 329 #define MAC_CR_PADSTR 0x00000100 330 #define MAC_CR_BOLMT_MASK 0x000000C0 331 #define MAC_CR_DFCHK 0x00000020 332 #define MAC_CR_TXEN 0x00000008 333 #define MAC_CR_RXEN 0x00000004 334 335 #define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */ 336 #define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */ 337 #define HASHH 0x04 /* R/W */ 338 #define HASHL 0x05 /* R/W */ 339 340 #define MII_ACC 0x06 /* R/W */ 341 #define MII_ACC_PHY_ADDR 0x0000F800 342 #define MII_ACC_MIIRINDA 0x000007C0 343 #define MII_ACC_MII_WRITE 0x00000002 344 #define MII_ACC_MII_BUSY 0x00000001 345 346 #define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */ 347 348 #define FLOW 0x08 /* R/W */ 349 #define FLOW_FCPT 0xFFFF0000 350 #define FLOW_FCPASS 0x00000004 351 #define FLOW_FCEN 0x00000002 352 #define FLOW_FCBSY 0x00000001 353 354 #define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */ 355 #define VLAN1_VTI1 0x0000ffff 356 357 #define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */ 358 #define VLAN2_VTI2 0x0000ffff 359 360 #define WUFF 0x0B /* WO */ 361 362 #define WUCSR 0x0C /* R/W */ 363 #define WUCSR_GUE 0x00000200 364 #define WUCSR_WUFR 0x00000040 365 #define WUCSR_MPR 0x00000020 366 #define WUCSR_WAKE_EN 0x00000004 367 #define WUCSR_MPEN 0x00000002 368 369 /* Chip ID values */ 370 #define CHIP_89218 0x218a 371 #define CHIP_9115 0x115 372 #define CHIP_9116 0x116 373 #define CHIP_9117 0x117 374 #define CHIP_9118 0x118 375 #define CHIP_9211 0x9211 376 #define CHIP_9215 0x115a 377 #define CHIP_9216 0x116a 378 #define CHIP_9217 0x117a 379 #define CHIP_9218 0x118a 380 #define CHIP_9220 0x9220 381 #define CHIP_9221 0x9221 382 383 struct chip_id { 384 u16 id; 385 char *name; 386 }; 387 388 static const struct chip_id chip_ids[] = { 389 { CHIP_89218, "LAN89218" }, 390 { CHIP_9115, "LAN9115" }, 391 { CHIP_9116, "LAN9116" }, 392 { CHIP_9117, "LAN9117" }, 393 { CHIP_9118, "LAN9118" }, 394 { CHIP_9211, "LAN9211" }, 395 { CHIP_9215, "LAN9215" }, 396 { CHIP_9216, "LAN9216" }, 397 { CHIP_9217, "LAN9217" }, 398 { CHIP_9218, "LAN9218" }, 399 { CHIP_9220, "LAN9220" }, 400 { CHIP_9221, "LAN9221" }, 401 { 0, NULL }, 402 }; 403 404 static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg) 405 { 406 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) 407 ; 408 smc911x_reg_write(dev, MAC_CSR_CMD, 409 MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); 410 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) 411 ; 412 413 return smc911x_reg_read(dev, MAC_CSR_DATA); 414 } 415 416 static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data) 417 { 418 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) 419 ; 420 smc911x_reg_write(dev, MAC_CSR_DATA, data); 421 smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); 422 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) 423 ; 424 } 425 426 static int smc911x_detect_chip(struct eth_device *dev) 427 { 428 unsigned long val, i; 429 430 val = smc911x_reg_read(dev, BYTE_TEST); 431 if (val == 0xffffffff) { 432 /* Special case -- no chip present */ 433 return -1; 434 } else if (val != 0x87654321) { 435 printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); 436 return -1; 437 } 438 439 val = smc911x_reg_read(dev, ID_REV) >> 16; 440 for (i = 0; chip_ids[i].id != 0; i++) { 441 if (chip_ids[i].id == val) break; 442 } 443 if (!chip_ids[i].id) { 444 printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); 445 return -1; 446 } 447 448 dev->priv = (void *)&chip_ids[i]; 449 450 return 0; 451 } 452 453 static void smc911x_reset(struct eth_device *dev) 454 { 455 int timeout; 456 457 /* 458 * Take out of PM setting first 459 * Device is already wake up if PMT_CTRL_READY bit is set 460 */ 461 if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) { 462 /* Write to the bytetest will take out of powerdown */ 463 smc911x_reg_write(dev, BYTE_TEST, 0x0); 464 465 timeout = 10; 466 467 while (timeout-- && 468 !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY)) 469 udelay(10); 470 if (timeout < 0) { 471 printf(DRIVERNAME 472 ": timeout waiting for PM restore\n"); 473 return; 474 } 475 } 476 477 /* Disable interrupts */ 478 smc911x_reg_write(dev, INT_EN, 0); 479 480 smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST); 481 482 timeout = 1000; 483 while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) 484 udelay(10); 485 486 if (timeout < 0) { 487 printf(DRIVERNAME ": reset timeout\n"); 488 return; 489 } 490 491 /* Reset the FIFO level and flow control settings */ 492 smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN); 493 smc911x_reg_write(dev, AFC_CFG, 0x0050287F); 494 495 /* Set to LED outputs */ 496 smc911x_reg_write(dev, GPIO_CFG, 0x70070000); 497 } 498 499 #endif 500