1 /* 2 * SMSC LAN9[12]1[567] Network driver 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <command.h> 27 #include <net.h> 28 #include <miiphy.h> 29 30 #if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \ 31 defined (CONFIG_DRIVER_SMC911X_16_BIT) 32 #error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \ 33 CONFIG_DRIVER_SMC911X_16_BIT shall be set" 34 #endif 35 36 #if defined (CONFIG_DRIVER_SMC911X_32_BIT) 37 static inline u32 reg_read(u32 addr) 38 { 39 return *(volatile u32*)addr; 40 } 41 static inline void reg_write(u32 addr, u32 val) 42 { 43 *(volatile u32*)addr = val; 44 } 45 #elif defined (CONFIG_DRIVER_SMC911X_16_BIT) 46 static inline u32 reg_read(u32 addr) 47 { 48 volatile u16 *addr_16 = (u16 *)addr; 49 return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); 50 } 51 static inline void reg_write(u32 addr, u32 val) 52 { 53 *(volatile u16*)addr = (u16)val; 54 *(volatile u16*)(addr + 2) = (u16)(val >> 16); 55 } 56 #else 57 #error "SMC911X: undefined bus width" 58 #endif /* CONFIG_DRIVER_SMC911X_16_BIT */ 59 60 u32 pkt_data_pull(u32 addr) \ 61 __attribute__ ((weak, alias ("reg_read"))); 62 void pkt_data_push(u32 addr, u32 val) \ 63 __attribute__ ((weak, alias ("reg_write"))); 64 65 #define mdelay(n) udelay((n)*1000) 66 67 /* Below are the register offsets and bit definitions 68 * of the Lan911x memory space 69 */ 70 #define RX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x00) 71 72 #define TX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x20) 73 #define TX_CMD_A_INT_ON_COMP 0x80000000 74 #define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 75 #define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 76 #define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000 77 #define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000 78 #define TX_CMD_A_INT_DATA_OFFSET 0x001F0000 79 #define TX_CMD_A_INT_FIRST_SEG 0x00002000 80 #define TX_CMD_A_INT_LAST_SEG 0x00001000 81 #define TX_CMD_A_BUF_SIZE 0x000007FF 82 #define TX_CMD_B_PKT_TAG 0xFFFF0000 83 #define TX_CMD_B_ADD_CRC_DISABLE 0x00002000 84 #define TX_CMD_B_DISABLE_PADDING 0x00001000 85 #define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF 86 87 #define RX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x40) 88 #define RX_STS_PKT_LEN 0x3FFF0000 89 #define RX_STS_ES 0x00008000 90 #define RX_STS_BCST 0x00002000 91 #define RX_STS_LEN_ERR 0x00001000 92 #define RX_STS_RUNT_ERR 0x00000800 93 #define RX_STS_MCAST 0x00000400 94 #define RX_STS_TOO_LONG 0x00000080 95 #define RX_STS_COLL 0x00000040 96 #define RX_STS_ETH_TYPE 0x00000020 97 #define RX_STS_WDOG_TMT 0x00000010 98 #define RX_STS_MII_ERR 0x00000008 99 #define RX_STS_DRIBBLING 0x00000004 100 #define RX_STS_CRC_ERR 0x00000002 101 #define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44) 102 #define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48) 103 #define TX_STS_TAG 0xFFFF0000 104 #define TX_STS_ES 0x00008000 105 #define TX_STS_LOC 0x00000800 106 #define TX_STS_NO_CARR 0x00000400 107 #define TX_STS_LATE_COLL 0x00000200 108 #define TX_STS_MANY_COLL 0x00000100 109 #define TX_STS_COLL_CNT 0x00000078 110 #define TX_STS_MANY_DEFER 0x00000004 111 #define TX_STS_UNDERRUN 0x00000002 112 #define TX_STS_DEFERRED 0x00000001 113 #define TX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x4C) 114 #define ID_REV (CONFIG_DRIVER_SMC911X_BASE + 0x50) 115 #define ID_REV_CHIP_ID 0xFFFF0000 /* RO */ 116 #define ID_REV_REV_ID 0x0000FFFF /* RO */ 117 118 #define INT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x54) 119 #define INT_CFG_INT_DEAS 0xFF000000 /* R/W */ 120 #define INT_CFG_INT_DEAS_CLR 0x00004000 121 #define INT_CFG_INT_DEAS_STS 0x00002000 122 #define INT_CFG_IRQ_INT 0x00001000 /* RO */ 123 #define INT_CFG_IRQ_EN 0x00000100 /* R/W */ 124 #define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */ 125 #define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */ 126 127 #define INT_STS (CONFIG_DRIVER_SMC911X_BASE + 0x58) 128 #define INT_STS_SW_INT 0x80000000 /* R/WC */ 129 #define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */ 130 #define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */ 131 #define INT_STS_RXDFH_INT 0x00800000 /* R/WC */ 132 #define INT_STS_RXDF_INT 0x00400000 /* R/WC */ 133 #define INT_STS_TX_IOC 0x00200000 /* R/WC */ 134 #define INT_STS_RXD_INT 0x00100000 /* R/WC */ 135 #define INT_STS_GPT_INT 0x00080000 /* R/WC */ 136 #define INT_STS_PHY_INT 0x00040000 /* RO */ 137 #define INT_STS_PME_INT 0x00020000 /* R/WC */ 138 #define INT_STS_TXSO 0x00010000 /* R/WC */ 139 #define INT_STS_RWT 0x00008000 /* R/WC */ 140 #define INT_STS_RXE 0x00004000 /* R/WC */ 141 #define INT_STS_TXE 0x00002000 /* R/WC */ 142 /*#define INT_STS_ERX 0x00001000*/ /* R/WC */ 143 #define INT_STS_TDFU 0x00000800 /* R/WC */ 144 #define INT_STS_TDFO 0x00000400 /* R/WC */ 145 #define INT_STS_TDFA 0x00000200 /* R/WC */ 146 #define INT_STS_TSFF 0x00000100 /* R/WC */ 147 #define INT_STS_TSFL 0x00000080 /* R/WC */ 148 /*#define INT_STS_RXDF 0x00000040*/ /* R/WC */ 149 #define INT_STS_RDFO 0x00000040 /* R/WC */ 150 #define INT_STS_RDFL 0x00000020 /* R/WC */ 151 #define INT_STS_RSFF 0x00000010 /* R/WC */ 152 #define INT_STS_RSFL 0x00000008 /* R/WC */ 153 #define INT_STS_GPIO2_INT 0x00000004 /* R/WC */ 154 #define INT_STS_GPIO1_INT 0x00000002 /* R/WC */ 155 #define INT_STS_GPIO0_INT 0x00000001 /* R/WC */ 156 #define INT_EN (CONFIG_DRIVER_SMC911X_BASE + 0x5C) 157 #define INT_EN_SW_INT_EN 0x80000000 /* R/W */ 158 #define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */ 159 #define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */ 160 #define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */ 161 /*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */ 162 #define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */ 163 #define INT_EN_RXD_INT_EN 0x00100000 /* R/W */ 164 #define INT_EN_GPT_INT_EN 0x00080000 /* R/W */ 165 #define INT_EN_PHY_INT_EN 0x00040000 /* R/W */ 166 #define INT_EN_PME_INT_EN 0x00020000 /* R/W */ 167 #define INT_EN_TXSO_EN 0x00010000 /* R/W */ 168 #define INT_EN_RWT_EN 0x00008000 /* R/W */ 169 #define INT_EN_RXE_EN 0x00004000 /* R/W */ 170 #define INT_EN_TXE_EN 0x00002000 /* R/W */ 171 /*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */ 172 #define INT_EN_TDFU_EN 0x00000800 /* R/W */ 173 #define INT_EN_TDFO_EN 0x00000400 /* R/W */ 174 #define INT_EN_TDFA_EN 0x00000200 /* R/W */ 175 #define INT_EN_TSFF_EN 0x00000100 /* R/W */ 176 #define INT_EN_TSFL_EN 0x00000080 /* R/W */ 177 /*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */ 178 #define INT_EN_RDFO_EN 0x00000040 /* R/W */ 179 #define INT_EN_RDFL_EN 0x00000020 /* R/W */ 180 #define INT_EN_RSFF_EN 0x00000010 /* R/W */ 181 #define INT_EN_RSFL_EN 0x00000008 /* R/W */ 182 #define INT_EN_GPIO2_INT 0x00000004 /* R/W */ 183 #define INT_EN_GPIO1_INT 0x00000002 /* R/W */ 184 #define INT_EN_GPIO0_INT 0x00000001 /* R/W */ 185 186 #define BYTE_TEST (CONFIG_DRIVER_SMC911X_BASE + 0x64) 187 #define FIFO_INT (CONFIG_DRIVER_SMC911X_BASE + 0x68) 188 #define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */ 189 #define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */ 190 #define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */ 191 #define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */ 192 193 #define RX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x6C) 194 #define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */ 195 #define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */ 196 #define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */ 197 #define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */ 198 #define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */ 199 #define RX_CFG_RX_DUMP 0x00008000 /* R/W */ 200 #define RX_CFG_RXDOFF 0x00001F00 /* R/W */ 201 /*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */ 202 203 #define TX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x70) 204 /*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */ 205 /*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ /* R/W Self Clearing */ 206 #define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */ 207 #define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */ 208 #define TX_CFG_TXSAO 0x00000004 /* R/W */ 209 #define TX_CFG_TX_ON 0x00000002 /* R/W */ 210 #define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */ 211 212 #define HW_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x74) 213 #define HW_CFG_TTM 0x00200000 /* R/W */ 214 #define HW_CFG_SF 0x00100000 /* R/W */ 215 #define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */ 216 #define HW_CFG_TR 0x00003000 /* R/W */ 217 #define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */ 218 #define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ 219 #define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ 220 #define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ 221 #define HW_CFG_SMI_SEL 0x00000010 /* R/W */ 222 #define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */ 223 #define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */ 224 #define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */ 225 #define HW_CFG_SRST_TO 0x00000002 /* RO */ 226 #define HW_CFG_SRST 0x00000001 /* Self Clearing */ 227 228 #define RX_DP_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x78) 229 #define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */ 230 #define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */ 231 232 #define RX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x7C) 233 #define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */ 234 #define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */ 235 236 #define TX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x80) 237 #define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */ 238 #define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */ 239 240 #define PMT_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x84) 241 #define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */ 242 #define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */ 243 #define PMT_CTRL_WOL_EN 0x00000200 /* R/W */ 244 #define PMT_CTRL_ED_EN 0x00000100 /* R/W */ 245 #define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */ 246 #define PMT_CTRL_WUPS 0x00000030 /* R/WC */ 247 #define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */ 248 #define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */ 249 #define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */ 250 #define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */ 251 #define PMT_CTRL_PME_IND 0x00000008 /* R/W */ 252 #define PMT_CTRL_PME_POL 0x00000004 /* R/W */ 253 #define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */ 254 #define PMT_CTRL_READY 0x00000001 /* RO */ 255 256 #define GPIO_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x88) 257 #define GPIO_CFG_LED3_EN 0x40000000 /* R/W */ 258 #define GPIO_CFG_LED2_EN 0x20000000 /* R/W */ 259 #define GPIO_CFG_LED1_EN 0x10000000 /* R/W */ 260 #define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */ 261 #define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */ 262 #define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */ 263 #define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */ 264 #define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */ 265 #define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */ 266 #define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */ 267 #define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */ 268 #define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */ 269 #define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */ 270 #define GPIO_CFG_GPIOD4 0x00000010 /* R/W */ 271 #define GPIO_CFG_GPIOD3 0x00000008 /* R/W */ 272 #define GPIO_CFG_GPIOD2 0x00000004 /* R/W */ 273 #define GPIO_CFG_GPIOD1 0x00000002 /* R/W */ 274 #define GPIO_CFG_GPIOD0 0x00000001 /* R/W */ 275 276 #define GPT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x8C) 277 #define GPT_CFG_TIMER_EN 0x20000000 /* R/W */ 278 #define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */ 279 280 #define GPT_CNT (CONFIG_DRIVER_SMC911X_BASE + 0x90) 281 #define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */ 282 283 #define ENDIAN (CONFIG_DRIVER_SMC911X_BASE + 0x98) 284 #define FREE_RUN (CONFIG_DRIVER_SMC911X_BASE + 0x9C) 285 #define RX_DROP (CONFIG_DRIVER_SMC911X_BASE + 0xA0) 286 #define MAC_CSR_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xA4) 287 #define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */ 288 #define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */ 289 #define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */ 290 291 #define MAC_CSR_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xA8) 292 #define AFC_CFG (CONFIG_DRIVER_SMC911X_BASE + 0xAC) 293 #define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */ 294 #define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */ 295 #define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */ 296 #define AFC_CFG_FCMULT 0x00000008 /* R/W */ 297 #define AFC_CFG_FCBRD 0x00000004 /* R/W */ 298 #define AFC_CFG_FCADD 0x00000002 /* R/W */ 299 #define AFC_CFG_FCANY 0x00000001 /* R/W */ 300 301 #define E2P_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xB0) 302 #define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */ 303 #define E2P_CMD_EPC_CMD 0x70000000 /* R/W */ 304 #define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */ 305 #define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */ 306 #define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */ 307 #define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */ 308 #define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */ 309 #define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */ 310 #define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */ 311 #define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */ 312 #define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */ 313 #define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */ 314 #define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */ 315 316 #define E2P_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xB4) 317 #define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */ 318 /* end of LAN register offsets and bit definitions */ 319 320 /* MAC Control and Status registers */ 321 #define MAC_CR 0x01 /* R/W */ 322 323 /* MAC_CR - MAC Control Register */ 324 #define MAC_CR_RXALL 0x80000000 325 /* TODO: delete this bit? It is not described in the data sheet. */ 326 #define MAC_CR_HBDIS 0x10000000 327 #define MAC_CR_RCVOWN 0x00800000 328 #define MAC_CR_LOOPBK 0x00200000 329 #define MAC_CR_FDPX 0x00100000 330 #define MAC_CR_MCPAS 0x00080000 331 #define MAC_CR_PRMS 0x00040000 332 #define MAC_CR_INVFILT 0x00020000 333 #define MAC_CR_PASSBAD 0x00010000 334 #define MAC_CR_HFILT 0x00008000 335 #define MAC_CR_HPFILT 0x00002000 336 #define MAC_CR_LCOLL 0x00001000 337 #define MAC_CR_BCAST 0x00000800 338 #define MAC_CR_DISRTY 0x00000400 339 #define MAC_CR_PADSTR 0x00000100 340 #define MAC_CR_BOLMT_MASK 0x000000C0 341 #define MAC_CR_DFCHK 0x00000020 342 #define MAC_CR_TXEN 0x00000008 343 #define MAC_CR_RXEN 0x00000004 344 345 #define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */ 346 #define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */ 347 #define HASHH 0x04 /* R/W */ 348 #define HASHL 0x05 /* R/W */ 349 350 #define MII_ACC 0x06 /* R/W */ 351 #define MII_ACC_PHY_ADDR 0x0000F800 352 #define MII_ACC_MIIRINDA 0x000007C0 353 #define MII_ACC_MII_WRITE 0x00000002 354 #define MII_ACC_MII_BUSY 0x00000001 355 356 #define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */ 357 358 #define FLOW 0x08 /* R/W */ 359 #define FLOW_FCPT 0xFFFF0000 360 #define FLOW_FCPASS 0x00000004 361 #define FLOW_FCEN 0x00000002 362 #define FLOW_FCBSY 0x00000001 363 364 #define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */ 365 #define VLAN1_VTI1 0x0000ffff 366 367 #define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */ 368 #define VLAN2_VTI2 0x0000ffff 369 370 #define WUFF 0x0B /* WO */ 371 372 #define WUCSR 0x0C /* R/W */ 373 #define WUCSR_GUE 0x00000200 374 #define WUCSR_WUFR 0x00000040 375 #define WUCSR_MPR 0x00000020 376 #define WUCSR_WAKE_EN 0x00000004 377 #define WUCSR_MPEN 0x00000002 378 379 /* Chip ID values */ 380 #define CHIP_9115 0x115 381 #define CHIP_9116 0x116 382 #define CHIP_9117 0x117 383 #define CHIP_9118 0x118 384 #define CHIP_9215 0x115a 385 #define CHIP_9216 0x116a 386 #define CHIP_9217 0x117a 387 #define CHIP_9218 0x118a 388 389 struct chip_id { 390 u16 id; 391 char *name; 392 }; 393 394 static const struct chip_id chip_ids[] = { 395 { CHIP_9115, "LAN9115" }, 396 { CHIP_9116, "LAN9116" }, 397 { CHIP_9117, "LAN9117" }, 398 { CHIP_9118, "LAN9118" }, 399 { CHIP_9215, "LAN9215" }, 400 { CHIP_9216, "LAN9216" }, 401 { CHIP_9217, "LAN9217" }, 402 { CHIP_9218, "LAN9218" }, 403 { 0, NULL }, 404 }; 405 406 #define DRIVERNAME "smc911x" 407 408 u32 smc911x_get_mac_csr(u8 reg) 409 { 410 while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) 411 ; 412 reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); 413 while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) 414 ; 415 416 return reg_read(MAC_CSR_DATA); 417 } 418 419 void smc911x_set_mac_csr(u8 reg, u32 data) 420 { 421 while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) 422 ; 423 reg_write(MAC_CSR_DATA, data); 424 reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); 425 while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) 426 ; 427 } 428 429 static int smx911x_handle_mac_address(bd_t *bd) 430 { 431 unsigned long addrh, addrl; 432 unsigned char *m = bd->bi_enetaddr; 433 434 /* if the environment has a valid mac address then use it */ 435 if ((m[0] | m[1] | m[2] | m[3] | m[4] | m[5])) { 436 addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24; 437 addrh = m[4] | m[5] << 8; 438 smc911x_set_mac_csr(ADDRH, addrh); 439 smc911x_set_mac_csr(ADDRL, addrl); 440 } else { 441 /* if not, try to get one from the eeprom */ 442 addrh = smc911x_get_mac_csr(ADDRH); 443 addrl = smc911x_get_mac_csr(ADDRL); 444 445 m[0] = (addrl ) & 0xff; 446 m[1] = (addrl >> 8 ) & 0xff; 447 m[2] = (addrl >> 16 ) & 0xff; 448 m[3] = (addrl >> 24 ) & 0xff; 449 m[4] = (addrh ) & 0xff; 450 m[5] = (addrh >> 8 ) & 0xff; 451 452 /* we get 0xff when there is no eeprom connected */ 453 if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) { 454 printf(DRIVERNAME ": no valid mac address in environment " 455 "and no eeprom found\n"); 456 return -1; 457 } 458 } 459 460 printf(DRIVERNAME ": MAC %02x:%02x:%02x:%02x:%02x:%02x\n", 461 m[0], m[1], m[2], m[3], m[4], m[5]); 462 463 return 0; 464 } 465 466 static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val) 467 { 468 while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY) 469 ; 470 471 smc911x_set_mac_csr(MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY); 472 473 while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY) 474 ; 475 476 *val = smc911x_get_mac_csr(MII_DATA); 477 478 return 0; 479 } 480 481 static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val) 482 { 483 while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY) 484 ; 485 486 smc911x_set_mac_csr(MII_DATA, val); 487 smc911x_set_mac_csr(MII_ACC, 488 phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); 489 490 while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY) 491 ; 492 return 0; 493 } 494 495 static int smc911x_phy_reset(void) 496 { 497 u32 reg; 498 499 reg = reg_read(PMT_CTRL); 500 reg &= ~0xfffff030; 501 reg |= PMT_CTRL_PHY_RST; 502 reg_write(PMT_CTRL, reg); 503 504 mdelay(100); 505 506 return 0; 507 } 508 509 static void smc911x_phy_configure(void) 510 { 511 int timeout; 512 u16 status; 513 514 smc911x_phy_reset(); 515 516 smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET); 517 mdelay(1); 518 smc911x_miiphy_write(1, PHY_ANAR, 0x01e1); 519 smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); 520 521 timeout = 5000; 522 do { 523 mdelay(1); 524 if ((timeout--) == 0) 525 goto err_out; 526 527 if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0) 528 goto err_out; 529 } while (!(status & PHY_BMSR_LS)); 530 531 printf(DRIVERNAME ": phy initialized\n"); 532 533 return; 534 535 err_out: 536 printf(DRIVERNAME ": autonegotiation timed out\n"); 537 } 538 539 static void smc911x_reset(void) 540 { 541 int timeout; 542 543 /* Take out of PM setting first */ 544 if (reg_read(PMT_CTRL) & PMT_CTRL_READY) { 545 /* Write to the bytetest will take out of powerdown */ 546 reg_write(BYTE_TEST, 0x0); 547 548 timeout = 10; 549 550 while (timeout-- && !(reg_read(PMT_CTRL) & PMT_CTRL_READY)) 551 udelay(10); 552 if (!timeout) { 553 printf(DRIVERNAME 554 ": timeout waiting for PM restore\n"); 555 return; 556 } 557 } 558 559 /* Disable interrupts */ 560 reg_write(INT_EN, 0); 561 562 reg_write(HW_CFG, HW_CFG_SRST); 563 564 timeout = 1000; 565 while (timeout-- && reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) 566 udelay(10); 567 568 if (!timeout) { 569 printf(DRIVERNAME ": reset timeout\n"); 570 return; 571 } 572 573 /* Reset the FIFO level and flow control settings */ 574 smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN); 575 reg_write(AFC_CFG, 0x0050287F); 576 577 /* Set to LED outputs */ 578 reg_write(GPIO_CFG, 0x70070000); 579 } 580 581 static void smc911x_enable(void) 582 { 583 /* Enable TX */ 584 reg_write(HW_CFG, 8 << 16 | HW_CFG_SF); 585 586 reg_write(GPT_CFG, GPT_CFG_TIMER_EN | 10000); 587 588 reg_write(TX_CFG, TX_CFG_TX_ON); 589 590 /* no padding to start of packets */ 591 reg_write(RX_CFG, 0); 592 593 smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); 594 595 } 596 597 int eth_init(bd_t *bd) 598 { 599 unsigned long val, i; 600 601 printf(DRIVERNAME ": initializing\n"); 602 603 val = reg_read(BYTE_TEST); 604 if (val != 0x87654321) { 605 printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); 606 goto err_out; 607 } 608 609 val = reg_read(ID_REV) >> 16; 610 for (i = 0; chip_ids[i].id != 0; i++) { 611 if (chip_ids[i].id == val) break; 612 } 613 if (!chip_ids[i].id) { 614 printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); 615 goto err_out; 616 } 617 618 printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); 619 620 smc911x_reset(); 621 622 /* Configure the PHY, initialize the link state */ 623 smc911x_phy_configure(); 624 625 if (smx911x_handle_mac_address(bd)) 626 goto err_out; 627 628 /* Turn on Tx + Rx */ 629 smc911x_enable(); 630 631 return 0; 632 633 err_out: 634 return -1; 635 } 636 637 int eth_send(volatile void *packet, int length) 638 { 639 u32 *data = (u32*)packet; 640 u32 tmplen; 641 u32 status; 642 643 reg_write(TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length); 644 reg_write(TX_DATA_FIFO, length); 645 646 tmplen = (length + 3) / 4; 647 648 while (tmplen--) 649 pkt_data_push(TX_DATA_FIFO, *data++); 650 651 /* wait for transmission */ 652 while (!((reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16)); 653 654 /* get status. Ignore 'no carrier' error, it has no meaning for 655 * full duplex operation 656 */ 657 status = reg_read(TX_STATUS_FIFO) & (TX_STS_LOC | TX_STS_LATE_COLL | 658 TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN); 659 660 if (!status) 661 return 0; 662 663 printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n", 664 status & TX_STS_LOC ? "TX_STS_LOC " : "", 665 status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "", 666 status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "", 667 status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "", 668 status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : ""); 669 670 return -1; 671 } 672 673 void eth_halt(void) 674 { 675 smc911x_reset(); 676 } 677 678 int eth_rx(void) 679 { 680 u32 *data = (u32 *)NetRxPackets[0]; 681 u32 pktlen, tmplen; 682 u32 status; 683 684 if ((reg_read(RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) { 685 status = reg_read(RX_STATUS_FIFO); 686 pktlen = (status & RX_STS_PKT_LEN) >> 16; 687 688 reg_write(RX_CFG, 0); 689 690 tmplen = (pktlen + 2+ 3) / 4; 691 while (tmplen--) 692 *data++ = pkt_data_pull(RX_DATA_FIFO); 693 694 if (status & RX_STS_ES) 695 printf(DRIVERNAME 696 ": dropped bad packet. Status: 0x%08x\n", 697 status); 698 else 699 NetReceive(NetRxPackets[0], pktlen); 700 } 701 702 return 0; 703 } 704