xref: /openbmc/u-boot/drivers/net/smc91111.h (revision f77d4410)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*------------------------------------------------------------------------
3  . smc91111.h - macros for the LAN91C111 Ethernet Driver
4  .
5  . (C) Copyright 2002
6  . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7  . Rolf Offermanns <rof@sysgo.de>
8  . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
9  .       Developed by Simple Network Magic Corporation (SNMC)
10  . Copyright (C) 1996 by Erik Stahlman (ES)
11  .
12  . This file contains register information and access macros for
13  . the LAN91C111 single chip ethernet controller.  It is a modified
14  . version of the smc9194.h file.
15  .
16  . Information contained in this file was obtained from the LAN91C111
17  . manual from SMC.  To get a copy, if you really want one, you can find
18  . information under www.smsc.com.
19  .
20  . Authors
21  .	Erik Stahlman				( erik@vt.edu )
22  .	Daris A Nevil				( dnevil@snmc.com )
23  .
24  . History
25  . 03/16/01		Daris A Nevil	Modified for use with LAN91C111 device
26  .
27  ---------------------------------------------------------------------------*/
28 #ifndef _SMC91111_H_
29 #define _SMC91111_H_
30 
31 #include <asm/types.h>
32 #include <config.h>
33 
34 /*
35  * This function may be called by the board specific initialisation code
36  * in order to override the default mac address.
37  */
38 
39 void smc_set_mac_addr (const unsigned char *addr);
40 
41 
42 /* I want some simple types */
43 
44 typedef unsigned char			byte;
45 typedef unsigned short			word;
46 typedef unsigned long int		dword;
47 
48 struct smc91111_priv{
49 	u8 dev_num;
50 };
51 
52 /*
53  . DEBUGGING LEVELS
54  .
55  . 0 for normal operation
56  . 1 for slightly more details
57  . >2 for various levels of increasingly useless information
58  .    2 for interrupt tracking, status flags
59  .    3 for packet info
60  .    4 for complete packet dumps
61 */
62 /*#define SMC_DEBUG 0 */
63 
64 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
65 
66 #define	SMC_IO_EXTENT	16
67 
68 #ifdef CONFIG_CPU_PXA25X
69 
70 #ifdef CONFIG_XSENGINE
71 #define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+((r)<<1))))
72 #define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
73 #define SMC_inb(a,p)  ({ \
74 	unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
75 	unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
76 	if (__p & 2) __v >>= 8; \
77 	else __v &= 0xff; \
78 	__v; })
79 #else
80 #define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r))))
81 #define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+(r))))
82 #define SMC_inb(a,p)	({ \
83 	unsigned int __p = (unsigned int)((a)->iobase + (p)); \
84 	unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
85 	if (__p & 1) __v >>= 8; \
86 	else __v &= 0xff; \
87 	__v; })
88 #endif
89 
90 #ifdef CONFIG_XSENGINE
91 #define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r<<1))) = d)
92 #define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r<<1))) = d)
93 #else
94 #define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r))) = d)
95 #define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r))) = d)
96 #endif
97 
98 #define	SMC_outb(a,d,r)	({	word __d = (byte)(d);  \
99 				word __w = SMC_inw((a),(r)&~1);  \
100 				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
101 				__w |= ((r)&1) ? __d<<8 : __d;  \
102 				SMC_outw((a),__w,(r)&~1);  \
103 			})
104 
105 #define SMC_outsl(a,r,b,l)	({	int __i; \
106 					dword *__b2; \
107 					__b2 = (dword *) b; \
108 					for (__i = 0; __i < l; __i++) { \
109 					    SMC_outl((a), *(__b2 + __i), r); \
110 					} \
111 				})
112 
113 #define SMC_outsw(a,r,b,l)	({	int __i; \
114 					word *__b2; \
115 					__b2 = (word *) b; \
116 					for (__i = 0; __i < l; __i++) { \
117 					    SMC_outw((a), *(__b2 + __i), r); \
118 					} \
119 				})
120 
121 #define SMC_insl(a,r,b,l)	({	int __i ;  \
122 					dword *__b2;  \
123 					__b2 = (dword *) b;  \
124 					for (__i = 0; __i < l; __i++) {  \
125 					  *(__b2 + __i) = SMC_inl((a),(r));  \
126 					  SMC_inl((a),0);  \
127 					};  \
128 				})
129 
130 #define SMC_insw(a,r,b,l)		({	int __i ;  \
131 					word *__b2;  \
132 					__b2 = (word *) b;  \
133 					for (__i = 0; __i < l; __i++) {  \
134 					  *(__b2 + __i) = SMC_inw((a),(r));  \
135 					  SMC_inw((a),0);  \
136 					};  \
137 				})
138 
139 #define SMC_insb(a,r,b,l)	({	int __i ;  \
140 					byte *__b2;  \
141 					__b2 = (byte *) b;  \
142 					for (__i = 0; __i < l; __i++) {  \
143 					  *(__b2 + __i) = SMC_inb((a),(r));  \
144 					  SMC_inb((a),0);  \
145 					};  \
146 				})
147 
148 #elif defined(CONFIG_LEON)	/* if not CONFIG_CPU_PXA25X */
149 
150 #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); })
151 
152 #define SMC_LEON_SWAP32(_x_)			\
153     ({ dword _x = (_x_);			\
154        ((_x << 24) |				\
155        ((0x0000FF00UL & _x) <<  8) |		\
156        ((0x00FF0000UL & _x) >>  8) |		\
157        (_x  >> 24)); })
158 
159 #define	SMC_inl(a,r)	(SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0)))))
160 #define	SMC_inl_nosw(a,r)	((*(volatile dword *)((a)->iobase+((r)<<0))))
161 #define	SMC_inw(a,r)	(SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0)))))
162 #define	SMC_inw_nosw(a,r)	((*(volatile word *)((a)->iobase+((r)<<0))))
163 #define SMC_inb(a,p)	({ \
164 	word ___v = SMC_inw((a),(p) & ~1); \
165 	if ((p) & 1) ___v >>= 8; \
166 	else ___v &= 0xff; \
167 	___v; })
168 
169 #define	SMC_outl(a,d,r)	(*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d))
170 #define	SMC_outl_nosw(a,d,r)	(*(volatile dword *)((a)->iobase+((r)<<0))=(d))
171 #define	SMC_outw(a,d,r)	(*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d))
172 #define	SMC_outw_nosw(a,d,r)	(*(volatile word *)((a)->iobase+((r)<<0))=(d))
173 #define	SMC_outb(a,d,r)	do{	word __d = (byte)(d);  \
174 				word __w = SMC_inw((a),(r)&~1);  \
175 				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
176 				__w |= ((r)&1) ? __d<<8 : __d;  \
177 				SMC_outw((a),__w,(r)&~1);  \
178 			}while(0)
179 #define SMC_outsl(a,r,b,l)	do{	int __i; \
180 					dword *__b2; \
181 					__b2 = (dword *) b; \
182 					for (__i = 0; __i < l; __i++) { \
183 					    SMC_outl_nosw((a), *(__b2 + __i), r); \
184 					} \
185 				}while(0)
186 #define SMC_outsw(a,r,b,l)	do{	int __i; \
187 					word *__b2; \
188 					__b2 = (word *) b; \
189 					for (__i = 0; __i < l; __i++) { \
190 					    SMC_outw_nosw((a), *(__b2 + __i), r); \
191 					} \
192 				}while(0)
193 #define SMC_insl(a,r,b,l)	do{	int __i ;  \
194 					dword *__b2;  \
195 					__b2 = (dword *) b;  \
196 					for (__i = 0; __i < l; __i++) {  \
197 					  *(__b2 + __i) = SMC_inl_nosw((a),(r));  \
198 					};  \
199 				}while(0)
200 
201 #define SMC_insw(a,r,b,l)		do{	int __i ;  \
202 					word *__b2;  \
203 					__b2 = (word *) b;  \
204 					for (__i = 0; __i < l; __i++) {  \
205 					  *(__b2 + __i) = SMC_inw_nosw((a),(r));  \
206 					};  \
207 				}while(0)
208 
209 #define SMC_insb(a,r,b,l)		do{	int __i ;  \
210 					byte *__b2;  \
211 					__b2 = (byte *) b;  \
212 					for (__i = 0; __i < l; __i++) {  \
213 					  *(__b2 + __i) = SMC_inb((a),(r));  \
214 					};  \
215 				}while(0)
216 #elif defined(CONFIG_MS7206SE)
217 #define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); })
218 #define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r)))
219 #define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01))))
220 #define SMC_insw(a, r, b, l) \
221 	do { \
222 		int __i; \
223 		word *__b2 = (word *)(b);		  \
224 		for (__i = 0; __i < (l); __i++) { \
225 			*__b2++ = SWAB7206(SMC_inw(a, r));	\
226 		} \
227 	} while (0)
228 #define	SMC_outw(a, d, r)	(*((volatile word *)((a)->iobase+(r))) = d)
229 #define	SMC_outb(a, d, r)	({	word __d = (byte)(d);  \
230 				word __w = SMC_inw((a), ((r)&(~1)));	\
231 				if (((r) & 1)) \
232 					__w = (__w & 0x00ff) | (__d << 8); \
233 				else \
234 					__w = (__w & 0xff00) | (__d); \
235 				SMC_outw((a), __w, ((r)&(~1)));	      \
236 			})
237 #define SMC_outsw(a, r, b, l) \
238 	do { \
239 		int __i; \
240 		word *__b2 = (word *)(b);		  \
241 		for (__i = 0; __i < (l); __i++) { \
242 			SMC_outw(a, SWAB7206(*__b2), r);	  \
243 			__b2++; \
244 		} \
245 	} while (0)
246 #else			/* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */
247 
248 #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
249 /*
250  * We have only 16 Bit PCMCIA access on Socket 0
251  */
252 
253 #ifdef CONFIG_ADNPESC1
254 #define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
255 #elif CONFIG_ARM64
256 #define	SMC_inw(a, r)	(*((volatile word*)((a)->iobase+((dword)(r)))))
257 #else
258 #define SMC_inw(a, r)	(*((volatile word*)((a)->iobase+(r))))
259 #endif
260 #define  SMC_inb(a,r)	(((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
261 
262 #ifdef CONFIG_ADNPESC1
263 #define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+((r)<<1))) = d)
264 #elif CONFIG_ARM64
265 #define	SMC_outw(a, d, r)	\
266 			(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
267 #else
268 #define	SMC_outw(a, d, r)	\
269 			(*((volatile word*)((a)->iobase+(r))) = d)
270 #endif
271 #define	SMC_outb(a,d,r)	({	word __d = (byte)(d);  \
272 				word __w = SMC_inw((a),(r)&~1);  \
273 				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
274 				__w |= ((r)&1) ? __d<<8 : __d;  \
275 				SMC_outw((a),__w,(r)&~1);  \
276 			})
277 #if 0
278 #define	SMC_outsw(a,r,b,l)	outsw((a)->iobase+(r), (b), (l))
279 #else
280 #define SMC_outsw(a,r,b,l)	({	int __i; \
281 					word *__b2; \
282 					__b2 = (word *) b; \
283 					for (__i = 0; __i < l; __i++) { \
284 					    SMC_outw((a), *(__b2 + __i), r); \
285 					} \
286 				})
287 #endif
288 
289 #if 0
290 #define	SMC_insw(a,r,b,l)	insw((a)->iobase+(r), (b), (l))
291 #else
292 #define SMC_insw(a,r,b,l)	({	int __i ;  \
293 					word *__b2;  \
294 					__b2 = (word *) b;  \
295 					for (__i = 0; __i < l; __i++) {  \
296 					  *(__b2 + __i) = SMC_inw((a),(r));  \
297 					  SMC_inw((a),0);  \
298 					};  \
299 				})
300 #endif
301 
302 #endif  /* CONFIG_SMC_USE_IOFUNCS */
303 
304 #if defined(CONFIG_SMC_USE_32_BIT)
305 
306 #ifdef CONFIG_XSENGINE
307 #define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r<<1))))
308 #else
309 #define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r))))
310 #endif
311 
312 #define SMC_insl(a,r,b,l)	({	int __i ;  \
313 					dword *__b2;  \
314 					__b2 = (dword *) b;  \
315 					for (__i = 0; __i < l; __i++) {  \
316 					  *(__b2 + __i) = SMC_inl((a),(r));  \
317 					  SMC_inl((a),0);  \
318 					};  \
319 				})
320 
321 #ifdef CONFIG_XSENGINE
322 #define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r<<1))) = d)
323 #else
324 #define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r))) = d)
325 #endif
326 #define SMC_outsl(a,r,b,l)	({	int __i; \
327 					dword *__b2; \
328 					__b2 = (dword *) b; \
329 					for (__i = 0; __i < l; __i++) { \
330 					    SMC_outl((a), *(__b2 + __i), r); \
331 					} \
332 				})
333 
334 #endif /* CONFIG_SMC_USE_32_BIT */
335 
336 #endif
337 
338 /*---------------------------------------------------------------
339  .
340  . A description of the SMSC registers is probably in order here,
341  . although for details, the SMC datasheet is invaluable.
342  .
343  . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
344  . are accessed by writing a number into the BANK_SELECT register
345  . ( I also use a SMC_SELECT_BANK macro for this ).
346  .
347  . The banks are configured so that for most purposes, bank 2 is all
348  . that is needed for simple run time tasks.
349  -----------------------------------------------------------------------*/
350 
351 /*
352  . Bank Select Register:
353  .
354  .		yyyy yyyy 0000 00xx
355  .		xx		= bank number
356  .		yyyy yyyy	= 0x33, for identification purposes.
357 */
358 #define	BANK_SELECT		14
359 
360 /* Transmit Control Register */
361 /* BANK 0  */
362 #define	TCR_REG		0x0000	/* transmit control register */
363 #define TCR_ENABLE	0x0001	/* When 1 we can transmit */
364 #define TCR_LOOP	0x0002	/* Controls output pin LBK */
365 #define TCR_FORCOL	0x0004	/* When 1 will force a collision */
366 #define TCR_PAD_EN	0x0080	/* When 1 will pad tx frames < 64 bytes w/0 */
367 #define TCR_NOCRC	0x0100	/* When 1 will not append CRC to tx frames */
368 #define TCR_MON_CSN	0x0400	/* When 1 tx monitors carrier */
369 #define TCR_FDUPLX	0x0800  /* When 1 enables full duplex operation */
370 #define TCR_STP_SQET	0x1000	/* When 1 stops tx if Signal Quality Error */
371 #define	TCR_EPH_LOOP	0x2000	/* When 1 enables EPH block loopback */
372 #define	TCR_SWFDUP	0x8000	/* When 1 enables Switched Full Duplex mode */
373 
374 #define	TCR_CLEAR	0	/* do NOTHING */
375 /* the default settings for the TCR register : */
376 /* QUESTION: do I want to enable padding of short packets ? */
377 #define	TCR_DEFAULT	TCR_ENABLE
378 
379 
380 /* EPH Status Register */
381 /* BANK 0  */
382 #define EPH_STATUS_REG	0x0002
383 #define ES_TX_SUC	0x0001	/* Last TX was successful */
384 #define ES_SNGL_COL	0x0002	/* Single collision detected for last tx */
385 #define ES_MUL_COL	0x0004	/* Multiple collisions detected for last tx */
386 #define ES_LTX_MULT	0x0008	/* Last tx was a multicast */
387 #define ES_16COL	0x0010	/* 16 Collisions Reached */
388 #define ES_SQET		0x0020	/* Signal Quality Error Test */
389 #define ES_LTXBRD	0x0040	/* Last tx was a broadcast */
390 #define ES_TXDEFR	0x0080	/* Transmit Deferred */
391 #define ES_LATCOL	0x0200	/* Late collision detected on last tx */
392 #define ES_LOSTCARR	0x0400	/* Lost Carrier Sense */
393 #define ES_EXC_DEF	0x0800	/* Excessive Deferral */
394 #define ES_CTR_ROL	0x1000	/* Counter Roll Over indication */
395 #define ES_LINK_OK	0x4000	/* Driven by inverted value of nLNK pin */
396 #define ES_TXUNRN	0x8000	/* Tx Underrun */
397 
398 
399 /* Receive Control Register */
400 /* BANK 0  */
401 #define	RCR_REG		0x0004
402 #define	RCR_RX_ABORT	0x0001	/* Set if a rx frame was aborted */
403 #define	RCR_PRMS	0x0002	/* Enable promiscuous mode */
404 #define	RCR_ALMUL	0x0004	/* When set accepts all multicast frames */
405 #define RCR_RXEN	0x0100	/* IFF this is set, we can receive packets */
406 #define	RCR_STRIP_CRC	0x0200	/* When set strips CRC from rx packets */
407 #define	RCR_ABORT_ENB	0x0200	/* When set will abort rx on collision */
408 #define	RCR_FILT_CAR	0x0400	/* When set filters leading 12 bit s of carrier */
409 #define RCR_SOFTRST	0x8000	/* resets the chip */
410 
411 /* the normal settings for the RCR register : */
412 #define	RCR_DEFAULT	(RCR_STRIP_CRC | RCR_RXEN)
413 #define RCR_CLEAR	0x0	/* set it to a base state */
414 
415 /* Counter Register */
416 /* BANK 0  */
417 #define	COUNTER_REG	0x0006
418 
419 /* Memory Information Register */
420 /* BANK 0  */
421 #define	MIR_REG		0x0008
422 
423 /* Receive/Phy Control Register */
424 /* BANK 0  */
425 #define	RPC_REG		0x000A
426 #define	RPC_SPEED	0x2000	/* When 1 PHY is in 100Mbps mode. */
427 #define	RPC_DPLX	0x1000	/* When 1 PHY is in Full-Duplex Mode */
428 #define	RPC_ANEG	0x0800	/* When 1 PHY is in Auto-Negotiate Mode */
429 #define	RPC_LSXA_SHFT	5	/* Bits to shift LS2A,LS1A,LS0A to lsb */
430 #define	RPC_LSXB_SHFT	2	/* Bits to get LS2B,LS1B,LS0B to lsb */
431 #define RPC_LED_100_10	(0x00)	/* LED = 100Mbps OR's with 10Mbps link detect */
432 #define RPC_LED_RES	(0x01)	/* LED = Reserved */
433 #define RPC_LED_10	(0x02)	/* LED = 10Mbps link detect */
434 #define RPC_LED_FD	(0x03)	/* LED = Full Duplex Mode */
435 #define RPC_LED_TX_RX	(0x04)	/* LED = TX or RX packet occurred */
436 #define RPC_LED_100	(0x05)	/* LED = 100Mbps link dectect */
437 #define RPC_LED_TX	(0x06)	/* LED = TX packet occurred */
438 #define RPC_LED_RX	(0x07)	/* LED = RX packet occurred */
439 #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
440 /* buggy schematic: LEDa -> yellow, LEDb --> green */
441 #define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
442 			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
443 			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
444 #elif defined(CONFIG_ADNPESC1)
445 /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
446 #define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
447 			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
448 			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
449 #else
450 /* SMSC reference design: LEDa --> green, LEDb --> yellow */
451 #define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
452 			| (RPC_LED_100_10 << RPC_LSXA_SHFT)	\
453 			| (RPC_LED_TX_RX << RPC_LSXB_SHFT)	)
454 #endif
455 
456 /* Bank 0 0x000C is reserved */
457 
458 /* Bank Select Register */
459 /* All Banks */
460 #define BSR_REG	0x000E
461 
462 
463 /* Configuration Reg */
464 /* BANK 1 */
465 #define CONFIG_REG	0x0000
466 #define CONFIG_EXT_PHY	0x0200	/* 1=external MII, 0=internal Phy */
467 #define CONFIG_GPCNTRL	0x0400	/* Inverse value drives pin nCNTRL */
468 #define CONFIG_NO_WAIT	0x1000	/* When 1 no extra wait states on ISA bus */
469 #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
470 
471 /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
472 #define CONFIG_DEFAULT	(CONFIG_EPH_POWER_EN)
473 
474 
475 /* Base Address Register */
476 /* BANK 1 */
477 #define	BASE_REG	0x0002
478 
479 
480 /* Individual Address Registers */
481 /* BANK 1 */
482 #define	ADDR0_REG	0x0004
483 #define	ADDR1_REG	0x0006
484 #define	ADDR2_REG	0x0008
485 
486 
487 /* General Purpose Register */
488 /* BANK 1 */
489 #define	GP_REG		0x000A
490 
491 
492 /* Control Register */
493 /* BANK 1 */
494 #define	CTL_REG		0x000C
495 #define CTL_RCV_BAD	0x4000 /* When 1 bad CRC packets are received */
496 #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
497 #define	CTL_LE_ENABLE	0x0080 /* When 1 enables Link Error interrupt */
498 #define	CTL_CR_ENABLE	0x0040 /* When 1 enables Counter Rollover interrupt */
499 #define	CTL_TE_ENABLE	0x0020 /* When 1 enables Transmit Error interrupt */
500 #define	CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
501 #define	CTL_RELOAD	0x0002 /* When set reads EEPROM into registers */
502 #define	CTL_STORE	0x0001 /* When set stores registers into EEPROM */
503 #define CTL_DEFAULT     (0x1A10) /* Autorelease enabled*/
504 
505 /* MMU Command Register */
506 /* BANK 2 */
507 #define MMU_CMD_REG	0x0000
508 #define MC_BUSY		1	/* When 1 the last release has not completed */
509 #define MC_NOP		(0<<5)	/* No Op */
510 #define	MC_ALLOC	(1<<5)	/* OR with number of 256 byte packets */
511 #define	MC_RESET	(2<<5)	/* Reset MMU to initial state */
512 #define	MC_REMOVE	(3<<5)	/* Remove the current rx packet */
513 #define MC_RELEASE	(4<<5)	/* Remove and release the current rx packet */
514 #define MC_FREEPKT	(5<<5)	/* Release packet in PNR register */
515 #define MC_ENQUEUE	(6<<5)	/* Enqueue the packet for transmit */
516 #define MC_RSTTXFIFO	(7<<5)	/* Reset the TX FIFOs */
517 
518 
519 /* Packet Number Register */
520 /* BANK 2 */
521 #define	PN_REG		0x0002
522 
523 
524 /* Allocation Result Register */
525 /* BANK 2 */
526 #define	AR_REG		0x0003
527 #define AR_FAILED	0x80	/* Alocation Failed */
528 
529 
530 /* RX FIFO Ports Register */
531 /* BANK 2 */
532 #define RXFIFO_REG	0x0004	/* Must be read as a word */
533 #define RXFIFO_REMPTY	0x8000	/* RX FIFO Empty */
534 
535 
536 /* TX FIFO Ports Register */
537 /* BANK 2 */
538 #define TXFIFO_REG	RXFIFO_REG	/* Must be read as a word */
539 #define TXFIFO_TEMPTY	0x80	/* TX FIFO Empty */
540 
541 
542 /* Pointer Register */
543 /* BANK 2 */
544 #define PTR_REG		0x0006
545 #define	PTR_RCV		0x8000 /* 1=Receive area, 0=Transmit area */
546 #define	PTR_AUTOINC	0x4000 /* Auto increment the pointer on each access */
547 #define PTR_READ	0x2000 /* When 1 the operation is a read */
548 #define PTR_NOTEMPTY	0x0800 /* When 1 _do not_ write fifo DATA REG */
549 
550 
551 /* Data Register */
552 /* BANK 2 */
553 #define	SMC91111_DATA_REG	0x0008
554 
555 
556 /* Interrupt Status/Acknowledge Register */
557 /* BANK 2 */
558 #define	SMC91111_INT_REG	0x000C
559 
560 
561 /* Interrupt Mask Register */
562 /* BANK 2 */
563 #define IM_REG		0x000D
564 #define	IM_MDINT	0x80 /* PHY MI Register 18 Interrupt */
565 #define	IM_ERCV_INT	0x40 /* Early Receive Interrupt */
566 #define	IM_EPH_INT	0x20 /* Set by Etheret Protocol Handler section */
567 #define	IM_RX_OVRN_INT	0x10 /* Set by Receiver Overruns */
568 #define	IM_ALLOC_INT	0x08 /* Set when allocation request is completed */
569 #define	IM_TX_EMPTY_INT	0x04 /* Set if the TX FIFO goes empty */
570 #define	IM_TX_INT	0x02 /* Transmit Interrrupt */
571 #define IM_RCV_INT	0x01 /* Receive Interrupt */
572 
573 
574 /* Multicast Table Registers */
575 /* BANK 3 */
576 #define	MCAST_REG1	0x0000
577 #define	MCAST_REG2	0x0002
578 #define	MCAST_REG3	0x0004
579 #define	MCAST_REG4	0x0006
580 
581 
582 /* Management Interface Register (MII) */
583 /* BANK 3 */
584 #define	MII_REG		0x0008
585 #define MII_MSK_CRS100	0x4000 /* Disables CRS100 detection during tx half dup */
586 #define MII_MDOE	0x0008 /* MII Output Enable */
587 #define MII_MCLK	0x0004 /* MII Clock, pin MDCLK */
588 #define MII_MDI		0x0002 /* MII Input, pin MDI */
589 #define MII_MDO		0x0001 /* MII Output, pin MDO */
590 
591 
592 /* Revision Register */
593 /* BANK 3 */
594 #define	REV_REG		0x000A /* ( hi: chip id   low: rev # ) */
595 
596 
597 /* Early RCV Register */
598 /* BANK 3 */
599 /* this is NOT on SMC9192 */
600 #define	ERCV_REG	0x000C
601 #define ERCV_RCV_DISCRD	0x0080 /* When 1 discards a packet being received */
602 #define ERCV_THRESHOLD	0x001F /* ERCV Threshold Mask */
603 
604 /* External Register */
605 /* BANK 7 */
606 #define	EXT_REG		0x0000
607 
608 
609 #define CHIP_9192	3
610 #define CHIP_9194	4
611 #define CHIP_9195	5
612 #define CHIP_9196	6
613 #define CHIP_91100	7
614 #define CHIP_91100FD	8
615 #define CHIP_91111FD	9
616 
617 #if 0
618 static const char * chip_ids[ 15 ] =  {
619 	NULL, NULL, NULL,
620 	/* 3 */ "SMC91C90/91C92",
621 	/* 4 */ "SMC91C94",
622 	/* 5 */ "SMC91C95",
623 	/* 6 */ "SMC91C96",
624 	/* 7 */ "SMC91C100",
625 	/* 8 */ "SMC91C100FD",
626 	/* 9 */ "SMC91C111",
627 	NULL, NULL,
628 	NULL, NULL, NULL};
629 #endif
630 
631 /*
632  . Transmit status bits
633 */
634 #define TS_SUCCESS 0x0001
635 #define TS_LOSTCAR 0x0400
636 #define TS_LATCOL  0x0200
637 #define TS_16COL   0x0010
638 
639 /*
640  . Receive status bits
641 */
642 #define RS_ALGNERR	0x8000
643 #define RS_BRODCAST	0x4000
644 #define RS_BADCRC	0x2000
645 #define RS_ODDFRAME	0x1000	/* bug: the LAN91C111 never sets this on receive */
646 #define RS_TOOLONG	0x0800
647 #define RS_TOOSHORT	0x0400
648 #define RS_MULTICAST	0x0001
649 #define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
650 
651 
652 /* PHY Types */
653 enum {
654 	PHY_LAN83C183 = 1,	/* LAN91C111 Internal PHY */
655 	PHY_LAN83C180
656 };
657 
658 
659 /* PHY Register Addresses (LAN91C111 Internal PHY) */
660 
661 /* PHY Control Register */
662 #define PHY_CNTL_REG		0x00
663 #define PHY_CNTL_RST		0x8000	/* 1=PHY Reset */
664 #define PHY_CNTL_LPBK		0x4000	/* 1=PHY Loopback */
665 #define PHY_CNTL_SPEED		0x2000	/* 1=100Mbps, 0=10Mpbs */
666 #define PHY_CNTL_ANEG_EN	0x1000 /* 1=Enable Auto negotiation */
667 #define PHY_CNTL_PDN		0x0800	/* 1=PHY Power Down mode */
668 #define PHY_CNTL_MII_DIS	0x0400	/* 1=MII 4 bit interface disabled */
669 #define PHY_CNTL_ANEG_RST	0x0200 /* 1=Reset Auto negotiate */
670 #define PHY_CNTL_DPLX		0x0100	/* 1=Full Duplex, 0=Half Duplex */
671 #define PHY_CNTL_COLTST		0x0080	/* 1= MII Colision Test */
672 
673 /* PHY Status Register */
674 #define PHY_STAT_REG		0x01
675 #define PHY_STAT_CAP_T4		0x8000	/* 1=100Base-T4 capable */
676 #define PHY_STAT_CAP_TXF	0x4000	/* 1=100Base-X full duplex capable */
677 #define PHY_STAT_CAP_TXH	0x2000	/* 1=100Base-X half duplex capable */
678 #define PHY_STAT_CAP_TF		0x1000	/* 1=10Mbps full duplex capable */
679 #define PHY_STAT_CAP_TH		0x0800	/* 1=10Mbps half duplex capable */
680 #define PHY_STAT_CAP_SUPR	0x0040	/* 1=recv mgmt frames with not preamble */
681 #define PHY_STAT_ANEG_ACK	0x0020	/* 1=ANEG has completed */
682 #define PHY_STAT_REM_FLT	0x0010	/* 1=Remote Fault detected */
683 #define PHY_STAT_CAP_ANEG	0x0008	/* 1=Auto negotiate capable */
684 #define PHY_STAT_LINK		0x0004	/* 1=valid link */
685 #define PHY_STAT_JAB		0x0002	/* 1=10Mbps jabber condition */
686 #define PHY_STAT_EXREG		0x0001	/* 1=extended registers implemented */
687 
688 /* PHY Identifier Registers */
689 #define PHY_ID1_REG		0x02	/* PHY Identifier 1 */
690 #define PHY_ID2_REG		0x03	/* PHY Identifier 2 */
691 
692 /* PHY Auto-Negotiation Advertisement Register */
693 #define PHY_AD_REG		0x04
694 #define PHY_AD_NP		0x8000	/* 1=PHY requests exchange of Next Page */
695 #define PHY_AD_ACK		0x4000	/* 1=got link code word from remote */
696 #define PHY_AD_RF		0x2000	/* 1=advertise remote fault */
697 #define PHY_AD_T4		0x0200	/* 1=PHY is capable of 100Base-T4 */
698 #define PHY_AD_TX_FDX		0x0100	/* 1=PHY is capable of 100Base-TX FDPLX */
699 #define PHY_AD_TX_HDX		0x0080	/* 1=PHY is capable of 100Base-TX HDPLX */
700 #define PHY_AD_10_FDX		0x0040	/* 1=PHY is capable of 10Base-T FDPLX */
701 #define PHY_AD_10_HDX		0x0020	/* 1=PHY is capable of 10Base-T HDPLX */
702 #define PHY_AD_CSMA		0x0001	/* 1=PHY is capable of 802.3 CMSA */
703 
704 /* PHY Auto-negotiation Remote End Capability Register */
705 #define PHY_RMT_REG		0x05
706 /* Uses same bit definitions as PHY_AD_REG */
707 
708 /* PHY Configuration Register 1 */
709 #define PHY_CFG1_REG		0x10
710 #define PHY_CFG1_LNKDIS		0x8000	/* 1=Rx Link Detect Function disabled */
711 #define PHY_CFG1_XMTDIS		0x4000	/* 1=TP Transmitter Disabled */
712 #define PHY_CFG1_XMTPDN		0x2000	/* 1=TP Transmitter Powered Down */
713 #define PHY_CFG1_BYPSCR		0x0400	/* 1=Bypass scrambler/descrambler */
714 #define PHY_CFG1_UNSCDS		0x0200	/* 1=Unscramble Idle Reception Disable */
715 #define PHY_CFG1_EQLZR		0x0100	/* 1=Rx Equalizer Disabled */
716 #define PHY_CFG1_CABLE		0x0080	/* 1=STP(150ohm), 0=UTP(100ohm) */
717 #define PHY_CFG1_RLVL0		0x0040	/* 1=Rx Squelch level reduced by 4.5db */
718 #define PHY_CFG1_TLVL_SHIFT	2	/* Transmit Output Level Adjust */
719 #define PHY_CFG1_TLVL_MASK	0x003C
720 #define PHY_CFG1_TRF_MASK	0x0003	/* Transmitter Rise/Fall time */
721 
722 
723 /* PHY Configuration Register 2 */
724 #define PHY_CFG2_REG		0x11
725 #define PHY_CFG2_APOLDIS	0x0020	/* 1=Auto Polarity Correction disabled */
726 #define PHY_CFG2_JABDIS		0x0010	/* 1=Jabber disabled */
727 #define PHY_CFG2_MREG		0x0008	/* 1=Multiple register access (MII mgt) */
728 #define PHY_CFG2_INTMDIO	0x0004	/* 1=Interrupt signaled with MDIO pulseo */
729 
730 /* PHY Status Output (and Interrupt status) Register */
731 #define PHY_INT_REG		0x12	/* Status Output (Interrupt Status) */
732 #define PHY_INT_INT		0x8000	/* 1=bits have changed since last read */
733 #define	PHY_INT_LNKFAIL		0x4000	/* 1=Link Not detected */
734 #define PHY_INT_LOSSSYNC	0x2000	/* 1=Descrambler has lost sync */
735 #define PHY_INT_CWRD		0x1000	/* 1=Invalid 4B5B code detected on rx */
736 #define PHY_INT_SSD		0x0800	/* 1=No Start Of Stream detected on rx */
737 #define PHY_INT_ESD		0x0400	/* 1=No End Of Stream detected on rx */
738 #define PHY_INT_RPOL		0x0200	/* 1=Reverse Polarity detected */
739 #define PHY_INT_JAB		0x0100	/* 1=Jabber detected */
740 #define PHY_INT_SPDDET		0x0080	/* 1=100Base-TX mode, 0=10Base-T mode */
741 #define PHY_INT_DPLXDET		0x0040	/* 1=Device in Full Duplex */
742 
743 /* PHY Interrupt/Status Mask Register */
744 #define PHY_MASK_REG		0x13	/* Interrupt Mask */
745 /* Uses the same bit definitions as PHY_INT_REG */
746 
747 
748 /*-------------------------------------------------------------------------
749  .  I define some macros to make it easier to do somewhat common
750  . or slightly complicated, repeated tasks.
751  --------------------------------------------------------------------------*/
752 
753 /* select a register bank, 0 to 3  */
754 
755 #define SMC_SELECT_BANK(a,x)  { SMC_outw((a), (x), BANK_SELECT ); }
756 
757 /* this enables an interrupt in the interrupt mask register */
758 #define SMC_ENABLE_INT(a,x) {\
759 		unsigned char mask;\
760 		SMC_SELECT_BANK((a),2);\
761 		mask = SMC_inb((a), IM_REG );\
762 		mask |= (x);\
763 		SMC_outb( (a), mask, IM_REG ); \
764 }
765 
766 /* this disables an interrupt from the interrupt mask register */
767 
768 #define SMC_DISABLE_INT(a,x) {\
769 		unsigned char mask;\
770 		SMC_SELECT_BANK(2);\
771 		mask = SMC_inb( (a), IM_REG );\
772 		mask &= ~(x);\
773 		SMC_outb( (a), mask, IM_REG ); \
774 }
775 
776 /*----------------------------------------------------------------------
777  . Define the interrupts that I want to receive from the card
778  .
779  . I want:
780  .  IM_EPH_INT, for nasty errors
781  .  IM_RCV_INT, for happy received packets
782  .  IM_RX_OVRN_INT, because I have to kick the receiver
783  .  IM_MDINT, for PHY Register 18 Status Changes
784  --------------------------------------------------------------------------*/
785 #define SMC_INTERRUPT_MASK   (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
786 	IM_MDINT)
787 
788 #endif  /* _SMC_91111_H_ */
789