1 /*------------------------------------------------------------------------ 2 . smc91111.h - macros for the LAN91C111 Ethernet Driver 3 . 4 . (C) Copyright 2002 5 . Sysgo Real-Time Solutions, GmbH <www.elinos.com> 6 . Rolf Offermanns <rof@sysgo.de> 7 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 8 . Developed by Simple Network Magic Corporation (SNMC) 9 . Copyright (C) 1996 by Erik Stahlman (ES) 10 . 11 * SPDX-License-Identifier: GPL-2.0+ 12 . 13 . This file contains register information and access macros for 14 . the LAN91C111 single chip ethernet controller. It is a modified 15 . version of the smc9194.h file. 16 . 17 . Information contained in this file was obtained from the LAN91C111 18 . manual from SMC. To get a copy, if you really want one, you can find 19 . information under www.smsc.com. 20 . 21 . Authors 22 . Erik Stahlman ( erik@vt.edu ) 23 . Daris A Nevil ( dnevil@snmc.com ) 24 . 25 . History 26 . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device 27 . 28 ---------------------------------------------------------------------------*/ 29 #ifndef _SMC91111_H_ 30 #define _SMC91111_H_ 31 32 #include <asm/types.h> 33 #include <config.h> 34 35 /* 36 * This function may be called by the board specific initialisation code 37 * in order to override the default mac address. 38 */ 39 40 void smc_set_mac_addr (const unsigned char *addr); 41 42 43 /* I want some simple types */ 44 45 typedef unsigned char byte; 46 typedef unsigned short word; 47 typedef unsigned long int dword; 48 49 struct smc91111_priv{ 50 u8 dev_num; 51 }; 52 53 /* 54 . DEBUGGING LEVELS 55 . 56 . 0 for normal operation 57 . 1 for slightly more details 58 . >2 for various levels of increasingly useless information 59 . 2 for interrupt tracking, status flags 60 . 3 for packet info 61 . 4 for complete packet dumps 62 */ 63 /*#define SMC_DEBUG 0 */ 64 65 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 66 67 #define SMC_IO_EXTENT 16 68 69 #ifdef CONFIG_CPU_PXA25X 70 71 #ifdef CONFIG_XSENGINE 72 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) 73 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) 74 #define SMC_inb(a,p) ({ \ 75 unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \ 76 unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ 77 if (__p & 2) __v >>= 8; \ 78 else __v &= 0xff; \ 79 __v; }) 80 #else 81 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) 82 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) 83 #define SMC_inb(a,p) ({ \ 84 unsigned int __p = (unsigned int)((a)->iobase + (p)); \ 85 unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ 86 if (__p & 1) __v >>= 8; \ 87 else __v &= 0xff; \ 88 __v; }) 89 #endif 90 91 #ifdef CONFIG_XSENGINE 92 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) 93 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) 94 #else 95 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) 96 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) 97 #endif 98 99 #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ 100 word __w = SMC_inw((a),(r)&~1); \ 101 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 102 __w |= ((r)&1) ? __d<<8 : __d; \ 103 SMC_outw((a),__w,(r)&~1); \ 104 }) 105 106 #define SMC_outsl(a,r,b,l) ({ int __i; \ 107 dword *__b2; \ 108 __b2 = (dword *) b; \ 109 for (__i = 0; __i < l; __i++) { \ 110 SMC_outl((a), *(__b2 + __i), r); \ 111 } \ 112 }) 113 114 #define SMC_outsw(a,r,b,l) ({ int __i; \ 115 word *__b2; \ 116 __b2 = (word *) b; \ 117 for (__i = 0; __i < l; __i++) { \ 118 SMC_outw((a), *(__b2 + __i), r); \ 119 } \ 120 }) 121 122 #define SMC_insl(a,r,b,l) ({ int __i ; \ 123 dword *__b2; \ 124 __b2 = (dword *) b; \ 125 for (__i = 0; __i < l; __i++) { \ 126 *(__b2 + __i) = SMC_inl((a),(r)); \ 127 SMC_inl((a),0); \ 128 }; \ 129 }) 130 131 #define SMC_insw(a,r,b,l) ({ int __i ; \ 132 word *__b2; \ 133 __b2 = (word *) b; \ 134 for (__i = 0; __i < l; __i++) { \ 135 *(__b2 + __i) = SMC_inw((a),(r)); \ 136 SMC_inw((a),0); \ 137 }; \ 138 }) 139 140 #define SMC_insb(a,r,b,l) ({ int __i ; \ 141 byte *__b2; \ 142 __b2 = (byte *) b; \ 143 for (__i = 0; __i < l; __i++) { \ 144 *(__b2 + __i) = SMC_inb((a),(r)); \ 145 SMC_inb((a),0); \ 146 }; \ 147 }) 148 149 #elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */ 150 151 #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) 152 153 #define SMC_LEON_SWAP32(_x_) \ 154 ({ dword _x = (_x_); \ 155 ((_x << 24) | \ 156 ((0x0000FF00UL & _x) << 8) | \ 157 ((0x00FF0000UL & _x) >> 8) | \ 158 (_x >> 24)); }) 159 160 #define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0))))) 161 #define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0)))) 162 #define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0))))) 163 #define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0)))) 164 #define SMC_inb(a,p) ({ \ 165 word ___v = SMC_inw((a),(p) & ~1); \ 166 if ((p) & 1) ___v >>= 8; \ 167 else ___v &= 0xff; \ 168 ___v; }) 169 170 #define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d)) 171 #define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d)) 172 #define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d)) 173 #define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d)) 174 #define SMC_outb(a,d,r) do{ word __d = (byte)(d); \ 175 word __w = SMC_inw((a),(r)&~1); \ 176 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 177 __w |= ((r)&1) ? __d<<8 : __d; \ 178 SMC_outw((a),__w,(r)&~1); \ 179 }while(0) 180 #define SMC_outsl(a,r,b,l) do{ int __i; \ 181 dword *__b2; \ 182 __b2 = (dword *) b; \ 183 for (__i = 0; __i < l; __i++) { \ 184 SMC_outl_nosw((a), *(__b2 + __i), r); \ 185 } \ 186 }while(0) 187 #define SMC_outsw(a,r,b,l) do{ int __i; \ 188 word *__b2; \ 189 __b2 = (word *) b; \ 190 for (__i = 0; __i < l; __i++) { \ 191 SMC_outw_nosw((a), *(__b2 + __i), r); \ 192 } \ 193 }while(0) 194 #define SMC_insl(a,r,b,l) do{ int __i ; \ 195 dword *__b2; \ 196 __b2 = (dword *) b; \ 197 for (__i = 0; __i < l; __i++) { \ 198 *(__b2 + __i) = SMC_inl_nosw((a),(r)); \ 199 }; \ 200 }while(0) 201 202 #define SMC_insw(a,r,b,l) do{ int __i ; \ 203 word *__b2; \ 204 __b2 = (word *) b; \ 205 for (__i = 0; __i < l; __i++) { \ 206 *(__b2 + __i) = SMC_inw_nosw((a),(r)); \ 207 }; \ 208 }while(0) 209 210 #define SMC_insb(a,r,b,l) do{ int __i ; \ 211 byte *__b2; \ 212 __b2 = (byte *) b; \ 213 for (__i = 0; __i < l; __i++) { \ 214 *(__b2 + __i) = SMC_inb((a),(r)); \ 215 }; \ 216 }while(0) 217 #elif defined(CONFIG_MS7206SE) 218 #define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); }) 219 #define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r))) 220 #define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01)))) 221 #define SMC_insw(a, r, b, l) \ 222 do { \ 223 int __i; \ 224 word *__b2 = (word *)(b); \ 225 for (__i = 0; __i < (l); __i++) { \ 226 *__b2++ = SWAB7206(SMC_inw(a, r)); \ 227 } \ 228 } while (0) 229 #define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d) 230 #define SMC_outb(a, d, r) ({ word __d = (byte)(d); \ 231 word __w = SMC_inw((a), ((r)&(~1))); \ 232 if (((r) & 1)) \ 233 __w = (__w & 0x00ff) | (__d << 8); \ 234 else \ 235 __w = (__w & 0xff00) | (__d); \ 236 SMC_outw((a), __w, ((r)&(~1))); \ 237 }) 238 #define SMC_outsw(a, r, b, l) \ 239 do { \ 240 int __i; \ 241 word *__b2 = (word *)(b); \ 242 for (__i = 0; __i < (l); __i++) { \ 243 SMC_outw(a, SWAB7206(*__b2), r); \ 244 __b2++; \ 245 } \ 246 } while (0) 247 #else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */ 248 249 #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ 250 /* 251 * We have only 16 Bit PCMCIA access on Socket 0 252 */ 253 254 #ifdef CONFIG_ADNPESC1 255 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) 256 #elif CONFIG_BLACKFIN 257 #define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) 258 #elif CONFIG_ARM64 259 #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) 260 #else 261 #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) 262 #endif 263 #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) 264 265 #ifdef CONFIG_ADNPESC1 266 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) 267 #elif CONFIG_BLACKFIN 268 #define SMC_outw(a, d, r) \ 269 ({ (*((volatile word*)((a)->iobase+((r)))) = d); \ 270 SSYNC(); \ 271 }) 272 #elif CONFIG_ARM64 273 #define SMC_outw(a, d, r) \ 274 (*((volatile word*)((a)->iobase+((dword)(r)))) = d) 275 #else 276 #define SMC_outw(a, d, r) \ 277 (*((volatile word*)((a)->iobase+(r))) = d) 278 #endif 279 #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ 280 word __w = SMC_inw((a),(r)&~1); \ 281 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 282 __w |= ((r)&1) ? __d<<8 : __d; \ 283 SMC_outw((a),__w,(r)&~1); \ 284 }) 285 #if 0 286 #define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l)) 287 #else 288 #define SMC_outsw(a,r,b,l) ({ int __i; \ 289 word *__b2; \ 290 __b2 = (word *) b; \ 291 for (__i = 0; __i < l; __i++) { \ 292 SMC_outw((a), *(__b2 + __i), r); \ 293 } \ 294 }) 295 #endif 296 297 #if 0 298 #define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l)) 299 #else 300 #define SMC_insw(a,r,b,l) ({ int __i ; \ 301 word *__b2; \ 302 __b2 = (word *) b; \ 303 for (__i = 0; __i < l; __i++) { \ 304 *(__b2 + __i) = SMC_inw((a),(r)); \ 305 SMC_inw((a),0); \ 306 }; \ 307 }) 308 #endif 309 310 #endif /* CONFIG_SMC_USE_IOFUNCS */ 311 312 #if defined(CONFIG_SMC_USE_32_BIT) 313 314 #ifdef CONFIG_XSENGINE 315 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) 316 #else 317 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) 318 #endif 319 320 #define SMC_insl(a,r,b,l) ({ int __i ; \ 321 dword *__b2; \ 322 __b2 = (dword *) b; \ 323 for (__i = 0; __i < l; __i++) { \ 324 *(__b2 + __i) = SMC_inl((a),(r)); \ 325 SMC_inl((a),0); \ 326 }; \ 327 }) 328 329 #ifdef CONFIG_XSENGINE 330 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) 331 #else 332 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) 333 #endif 334 #define SMC_outsl(a,r,b,l) ({ int __i; \ 335 dword *__b2; \ 336 __b2 = (dword *) b; \ 337 for (__i = 0; __i < l; __i++) { \ 338 SMC_outl((a), *(__b2 + __i), r); \ 339 } \ 340 }) 341 342 #endif /* CONFIG_SMC_USE_32_BIT */ 343 344 #endif 345 346 /*--------------------------------------------------------------- 347 . 348 . A description of the SMSC registers is probably in order here, 349 . although for details, the SMC datasheet is invaluable. 350 . 351 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which 352 . are accessed by writing a number into the BANK_SELECT register 353 . ( I also use a SMC_SELECT_BANK macro for this ). 354 . 355 . The banks are configured so that for most purposes, bank 2 is all 356 . that is needed for simple run time tasks. 357 -----------------------------------------------------------------------*/ 358 359 /* 360 . Bank Select Register: 361 . 362 . yyyy yyyy 0000 00xx 363 . xx = bank number 364 . yyyy yyyy = 0x33, for identification purposes. 365 */ 366 #define BANK_SELECT 14 367 368 /* Transmit Control Register */ 369 /* BANK 0 */ 370 #define TCR_REG 0x0000 /* transmit control register */ 371 #define TCR_ENABLE 0x0001 /* When 1 we can transmit */ 372 #define TCR_LOOP 0x0002 /* Controls output pin LBK */ 373 #define TCR_FORCOL 0x0004 /* When 1 will force a collision */ 374 #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ 375 #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ 376 #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ 377 #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ 378 #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ 379 #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ 380 #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ 381 382 #define TCR_CLEAR 0 /* do NOTHING */ 383 /* the default settings for the TCR register : */ 384 /* QUESTION: do I want to enable padding of short packets ? */ 385 #define TCR_DEFAULT TCR_ENABLE 386 387 388 /* EPH Status Register */ 389 /* BANK 0 */ 390 #define EPH_STATUS_REG 0x0002 391 #define ES_TX_SUC 0x0001 /* Last TX was successful */ 392 #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ 393 #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ 394 #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ 395 #define ES_16COL 0x0010 /* 16 Collisions Reached */ 396 #define ES_SQET 0x0020 /* Signal Quality Error Test */ 397 #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ 398 #define ES_TXDEFR 0x0080 /* Transmit Deferred */ 399 #define ES_LATCOL 0x0200 /* Late collision detected on last tx */ 400 #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ 401 #define ES_EXC_DEF 0x0800 /* Excessive Deferral */ 402 #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ 403 #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ 404 #define ES_TXUNRN 0x8000 /* Tx Underrun */ 405 406 407 /* Receive Control Register */ 408 /* BANK 0 */ 409 #define RCR_REG 0x0004 410 #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ 411 #define RCR_PRMS 0x0002 /* Enable promiscuous mode */ 412 #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ 413 #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ 414 #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ 415 #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ 416 #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ 417 #define RCR_SOFTRST 0x8000 /* resets the chip */ 418 419 /* the normal settings for the RCR register : */ 420 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 421 #define RCR_CLEAR 0x0 /* set it to a base state */ 422 423 /* Counter Register */ 424 /* BANK 0 */ 425 #define COUNTER_REG 0x0006 426 427 /* Memory Information Register */ 428 /* BANK 0 */ 429 #define MIR_REG 0x0008 430 431 /* Receive/Phy Control Register */ 432 /* BANK 0 */ 433 #define RPC_REG 0x000A 434 #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ 435 #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ 436 #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ 437 #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ 438 #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ 439 #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ 440 #define RPC_LED_RES (0x01) /* LED = Reserved */ 441 #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ 442 #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ 443 #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ 444 #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ 445 #define RPC_LED_TX (0x06) /* LED = TX packet occurred */ 446 #define RPC_LED_RX (0x07) /* LED = RX packet occurred */ 447 #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) 448 /* buggy schematic: LEDa -> yellow, LEDb --> green */ 449 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 450 | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 451 | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 452 #elif defined(CONFIG_ADNPESC1) 453 /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ 454 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 455 | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 456 | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 457 #else 458 /* SMSC reference design: LEDa --> green, LEDb --> yellow */ 459 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 460 | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ 461 | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) 462 #endif 463 464 /* Bank 0 0x000C is reserved */ 465 466 /* Bank Select Register */ 467 /* All Banks */ 468 #define BSR_REG 0x000E 469 470 471 /* Configuration Reg */ 472 /* BANK 1 */ 473 #define CONFIG_REG 0x0000 474 #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ 475 #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ 476 #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ 477 #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ 478 479 /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ 480 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 481 482 483 /* Base Address Register */ 484 /* BANK 1 */ 485 #define BASE_REG 0x0002 486 487 488 /* Individual Address Registers */ 489 /* BANK 1 */ 490 #define ADDR0_REG 0x0004 491 #define ADDR1_REG 0x0006 492 #define ADDR2_REG 0x0008 493 494 495 /* General Purpose Register */ 496 /* BANK 1 */ 497 #define GP_REG 0x000A 498 499 500 /* Control Register */ 501 /* BANK 1 */ 502 #define CTL_REG 0x000C 503 #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ 504 #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ 505 #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ 506 #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ 507 #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ 508 #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ 509 #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ 510 #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ 511 #define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ 512 513 /* MMU Command Register */ 514 /* BANK 2 */ 515 #define MMU_CMD_REG 0x0000 516 #define MC_BUSY 1 /* When 1 the last release has not completed */ 517 #define MC_NOP (0<<5) /* No Op */ 518 #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ 519 #define MC_RESET (2<<5) /* Reset MMU to initial state */ 520 #define MC_REMOVE (3<<5) /* Remove the current rx packet */ 521 #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ 522 #define MC_FREEPKT (5<<5) /* Release packet in PNR register */ 523 #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ 524 #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ 525 526 527 /* Packet Number Register */ 528 /* BANK 2 */ 529 #define PN_REG 0x0002 530 531 532 /* Allocation Result Register */ 533 /* BANK 2 */ 534 #define AR_REG 0x0003 535 #define AR_FAILED 0x80 /* Alocation Failed */ 536 537 538 /* RX FIFO Ports Register */ 539 /* BANK 2 */ 540 #define RXFIFO_REG 0x0004 /* Must be read as a word */ 541 #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ 542 543 544 /* TX FIFO Ports Register */ 545 /* BANK 2 */ 546 #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ 547 #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ 548 549 550 /* Pointer Register */ 551 /* BANK 2 */ 552 #define PTR_REG 0x0006 553 #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ 554 #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ 555 #define PTR_READ 0x2000 /* When 1 the operation is a read */ 556 #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ 557 558 559 /* Data Register */ 560 /* BANK 2 */ 561 #define SMC91111_DATA_REG 0x0008 562 563 564 /* Interrupt Status/Acknowledge Register */ 565 /* BANK 2 */ 566 #define SMC91111_INT_REG 0x000C 567 568 569 /* Interrupt Mask Register */ 570 /* BANK 2 */ 571 #define IM_REG 0x000D 572 #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ 573 #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ 574 #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ 575 #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ 576 #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ 577 #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ 578 #define IM_TX_INT 0x02 /* Transmit Interrrupt */ 579 #define IM_RCV_INT 0x01 /* Receive Interrupt */ 580 581 582 /* Multicast Table Registers */ 583 /* BANK 3 */ 584 #define MCAST_REG1 0x0000 585 #define MCAST_REG2 0x0002 586 #define MCAST_REG3 0x0004 587 #define MCAST_REG4 0x0006 588 589 590 /* Management Interface Register (MII) */ 591 /* BANK 3 */ 592 #define MII_REG 0x0008 593 #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ 594 #define MII_MDOE 0x0008 /* MII Output Enable */ 595 #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ 596 #define MII_MDI 0x0002 /* MII Input, pin MDI */ 597 #define MII_MDO 0x0001 /* MII Output, pin MDO */ 598 599 600 /* Revision Register */ 601 /* BANK 3 */ 602 #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ 603 604 605 /* Early RCV Register */ 606 /* BANK 3 */ 607 /* this is NOT on SMC9192 */ 608 #define ERCV_REG 0x000C 609 #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ 610 #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ 611 612 /* External Register */ 613 /* BANK 7 */ 614 #define EXT_REG 0x0000 615 616 617 #define CHIP_9192 3 618 #define CHIP_9194 4 619 #define CHIP_9195 5 620 #define CHIP_9196 6 621 #define CHIP_91100 7 622 #define CHIP_91100FD 8 623 #define CHIP_91111FD 9 624 625 #if 0 626 static const char * chip_ids[ 15 ] = { 627 NULL, NULL, NULL, 628 /* 3 */ "SMC91C90/91C92", 629 /* 4 */ "SMC91C94", 630 /* 5 */ "SMC91C95", 631 /* 6 */ "SMC91C96", 632 /* 7 */ "SMC91C100", 633 /* 8 */ "SMC91C100FD", 634 /* 9 */ "SMC91C111", 635 NULL, NULL, 636 NULL, NULL, NULL}; 637 #endif 638 639 /* 640 . Transmit status bits 641 */ 642 #define TS_SUCCESS 0x0001 643 #define TS_LOSTCAR 0x0400 644 #define TS_LATCOL 0x0200 645 #define TS_16COL 0x0010 646 647 /* 648 . Receive status bits 649 */ 650 #define RS_ALGNERR 0x8000 651 #define RS_BRODCAST 0x4000 652 #define RS_BADCRC 0x2000 653 #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ 654 #define RS_TOOLONG 0x0800 655 #define RS_TOOSHORT 0x0400 656 #define RS_MULTICAST 0x0001 657 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 658 659 660 /* PHY Types */ 661 enum { 662 PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ 663 PHY_LAN83C180 664 }; 665 666 667 /* PHY Register Addresses (LAN91C111 Internal PHY) */ 668 669 /* PHY Control Register */ 670 #define PHY_CNTL_REG 0x00 671 #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ 672 #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ 673 #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ 674 #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ 675 #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ 676 #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ 677 #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ 678 #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ 679 #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ 680 681 /* PHY Status Register */ 682 #define PHY_STAT_REG 0x01 683 #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ 684 #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ 685 #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ 686 #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ 687 #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ 688 #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ 689 #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ 690 #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ 691 #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ 692 #define PHY_STAT_LINK 0x0004 /* 1=valid link */ 693 #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ 694 #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ 695 696 /* PHY Identifier Registers */ 697 #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ 698 #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ 699 700 /* PHY Auto-Negotiation Advertisement Register */ 701 #define PHY_AD_REG 0x04 702 #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ 703 #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ 704 #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ 705 #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ 706 #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ 707 #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ 708 #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ 709 #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ 710 #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ 711 712 /* PHY Auto-negotiation Remote End Capability Register */ 713 #define PHY_RMT_REG 0x05 714 /* Uses same bit definitions as PHY_AD_REG */ 715 716 /* PHY Configuration Register 1 */ 717 #define PHY_CFG1_REG 0x10 718 #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ 719 #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ 720 #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ 721 #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ 722 #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ 723 #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ 724 #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ 725 #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ 726 #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ 727 #define PHY_CFG1_TLVL_MASK 0x003C 728 #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ 729 730 731 /* PHY Configuration Register 2 */ 732 #define PHY_CFG2_REG 0x11 733 #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ 734 #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ 735 #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ 736 #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ 737 738 /* PHY Status Output (and Interrupt status) Register */ 739 #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ 740 #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ 741 #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ 742 #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ 743 #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ 744 #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ 745 #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ 746 #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ 747 #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ 748 #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ 749 #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ 750 751 /* PHY Interrupt/Status Mask Register */ 752 #define PHY_MASK_REG 0x13 /* Interrupt Mask */ 753 /* Uses the same bit definitions as PHY_INT_REG */ 754 755 756 /*------------------------------------------------------------------------- 757 . I define some macros to make it easier to do somewhat common 758 . or slightly complicated, repeated tasks. 759 --------------------------------------------------------------------------*/ 760 761 /* select a register bank, 0 to 3 */ 762 763 #define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); } 764 765 /* this enables an interrupt in the interrupt mask register */ 766 #define SMC_ENABLE_INT(a,x) {\ 767 unsigned char mask;\ 768 SMC_SELECT_BANK((a),2);\ 769 mask = SMC_inb((a), IM_REG );\ 770 mask |= (x);\ 771 SMC_outb( (a), mask, IM_REG ); \ 772 } 773 774 /* this disables an interrupt from the interrupt mask register */ 775 776 #define SMC_DISABLE_INT(a,x) {\ 777 unsigned char mask;\ 778 SMC_SELECT_BANK(2);\ 779 mask = SMC_inb( (a), IM_REG );\ 780 mask &= ~(x);\ 781 SMC_outb( (a), mask, IM_REG ); \ 782 } 783 784 /*---------------------------------------------------------------------- 785 . Define the interrupts that I want to receive from the card 786 . 787 . I want: 788 . IM_EPH_INT, for nasty errors 789 . IM_RCV_INT, for happy received packets 790 . IM_RX_OVRN_INT, because I have to kick the receiver 791 . IM_MDINT, for PHY Register 18 Status Changes 792 --------------------------------------------------------------------------*/ 793 #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ 794 IM_MDINT) 795 796 #endif /* _SMC_91111_H_ */ 797