1 /*------------------------------------------------------------------------ 2 . smc91111.h - macros for the LAN91C111 Ethernet Driver 3 . 4 . (C) Copyright 2002 5 . Sysgo Real-Time Solutions, GmbH <www.elinos.com> 6 . Rolf Offermanns <rof@sysgo.de> 7 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 8 . Developed by Simple Network Magic Corporation (SNMC) 9 . Copyright (C) 1996 by Erik Stahlman (ES) 10 . 11 . This program is free software; you can redistribute it and/or modify 12 . it under the terms of the GNU General Public License as published by 13 . the Free Software Foundation; either version 2 of the License, or 14 . (at your option) any later version. 15 . 16 . This program is distributed in the hope that it will be useful, 17 . but WITHOUT ANY WARRANTY; without even the implied warranty of 18 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 . GNU General Public License for more details. 20 . 21 . You should have received a copy of the GNU General Public License 22 . along with this program; if not, write to the Free Software 23 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 . 25 . This file contains register information and access macros for 26 . the LAN91C111 single chip ethernet controller. It is a modified 27 . version of the smc9194.h file. 28 . 29 . Information contained in this file was obtained from the LAN91C111 30 . manual from SMC. To get a copy, if you really want one, you can find 31 . information under www.smsc.com. 32 . 33 . Authors 34 . Erik Stahlman ( erik@vt.edu ) 35 . Daris A Nevil ( dnevil@snmc.com ) 36 . 37 . History 38 . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device 39 . 40 ---------------------------------------------------------------------------*/ 41 #ifndef _SMC91111_H_ 42 #define _SMC91111_H_ 43 44 #include <asm/types.h> 45 #include <config.h> 46 47 /* 48 * This function may be called by the board specific initialisation code 49 * in order to override the default mac address. 50 */ 51 52 void smc_set_mac_addr (const unsigned char *addr); 53 54 55 /* I want some simple types */ 56 57 typedef unsigned char byte; 58 typedef unsigned short word; 59 typedef unsigned long int dword; 60 61 /* 62 . DEBUGGING LEVELS 63 . 64 . 0 for normal operation 65 . 1 for slightly more details 66 . >2 for various levels of increasingly useless information 67 . 2 for interrupt tracking, status flags 68 . 3 for packet info 69 . 4 for complete packet dumps 70 */ 71 /*#define SMC_DEBUG 0 */ 72 73 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 74 75 #define SMC_IO_EXTENT 16 76 77 #ifdef CONFIG_PXA250 78 79 #ifdef CONFIG_XSENGINE 80 #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) 81 #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1)))) 82 #define SMC_inb(p) ({ \ 83 unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \ 84 unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ 85 if (__p & 2) __v >>= 8; \ 86 else __v &= 0xff; \ 87 __v; }) 88 #elif defined(CONFIG_XAENIAX) 89 #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) 90 #define SMC_inw(z) ({ \ 91 unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \ 92 unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ 93 if (__p & 3) __v >>= 16; \ 94 else __v &= 0xffff; \ 95 __v; }) 96 #define SMC_inb(p) ({ \ 97 unsigned int ___v = SMC_inw((p) & ~1); \ 98 if (p & 1) ___v >>= 8; \ 99 else ___v &= 0xff; \ 100 ___v; }) 101 #else 102 #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) 103 #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) 104 #define SMC_inb(p) ({ \ 105 unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \ 106 unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ 107 if (__p & 1) __v >>= 8; \ 108 else __v &= 0xff; \ 109 __v; }) 110 #endif 111 112 #ifdef CONFIG_XSENGINE 113 #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) 114 #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d) 115 #elif defined (CONFIG_XAENIAX) 116 #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) 117 #define SMC_outw(d,p) ({ \ 118 dword __dwo = SMC_inl((p) & ~3); \ 119 dword __dwn = (word)(d); \ 120 __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ 121 __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ 122 SMC_outl(__dwo, (p) & ~3); \ 123 }) 124 #else 125 #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) 126 #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) 127 #endif 128 129 #define SMC_outb(d,r) ({ word __d = (byte)(d); \ 130 word __w = SMC_inw((r)&~1); \ 131 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 132 __w |= ((r)&1) ? __d<<8 : __d; \ 133 SMC_outw(__w,(r)&~1); \ 134 }) 135 136 #define SMC_outsl(r,b,l) ({ int __i; \ 137 dword *__b2; \ 138 __b2 = (dword *) b; \ 139 for (__i = 0; __i < l; __i++) { \ 140 SMC_outl( *(__b2 + __i), r); \ 141 } \ 142 }) 143 144 #define SMC_outsw(r,b,l) ({ int __i; \ 145 word *__b2; \ 146 __b2 = (word *) b; \ 147 for (__i = 0; __i < l; __i++) { \ 148 SMC_outw( *(__b2 + __i), r); \ 149 } \ 150 }) 151 152 #define SMC_insl(r,b,l) ({ int __i ; \ 153 dword *__b2; \ 154 __b2 = (dword *) b; \ 155 for (__i = 0; __i < l; __i++) { \ 156 *(__b2 + __i) = SMC_inl(r); \ 157 SMC_inl(0); \ 158 }; \ 159 }) 160 161 #define SMC_insw(r,b,l) ({ int __i ; \ 162 word *__b2; \ 163 __b2 = (word *) b; \ 164 for (__i = 0; __i < l; __i++) { \ 165 *(__b2 + __i) = SMC_inw(r); \ 166 SMC_inw(0); \ 167 }; \ 168 }) 169 170 #define SMC_insb(r,b,l) ({ int __i ; \ 171 byte *__b2; \ 172 __b2 = (byte *) b; \ 173 for (__i = 0; __i < l; __i++) { \ 174 *(__b2 + __i) = SMC_inb(r); \ 175 SMC_inb(0); \ 176 }; \ 177 }) 178 179 #else /* if not CONFIG_PXA250 */ 180 181 #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ 182 /* 183 * We have only 16 Bit PCMCIA access on Socket 0 184 */ 185 186 #ifdef CONFIG_ADNPESC1 187 #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) 188 #elif CONFIG_BLACKFIN 189 #define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;}) 190 #else 191 #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) 192 #endif 193 #define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) 194 195 #ifdef CONFIG_ADNPESC1 196 #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) 197 #elif CONFIG_BLACKFIN 198 #define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");} 199 #else 200 #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) 201 #endif 202 #define SMC_outb(d,r) ({ word __d = (byte)(d); \ 203 word __w = SMC_inw((r)&~1); \ 204 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 205 __w |= ((r)&1) ? __d<<8 : __d; \ 206 SMC_outw(__w,(r)&~1); \ 207 }) 208 #if 0 209 #define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) 210 #else 211 #define SMC_outsw(r,b,l) ({ int __i; \ 212 word *__b2; \ 213 __b2 = (word *) b; \ 214 for (__i = 0; __i < l; __i++) { \ 215 SMC_outw( *(__b2 + __i), r); \ 216 } \ 217 }) 218 #endif 219 220 #if 0 221 #define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) 222 #else 223 #define SMC_insw(r,b,l) ({ int __i ; \ 224 word *__b2; \ 225 __b2 = (word *) b; \ 226 for (__i = 0; __i < l; __i++) { \ 227 *(__b2 + __i) = SMC_inw(r); \ 228 SMC_inw(0); \ 229 }; \ 230 }) 231 #endif 232 233 #endif /* CONFIG_SMC_USE_IOFUNCS */ 234 235 #if defined(CONFIG_SMC_USE_32_BIT) 236 237 #ifdef CONFIG_XSENGINE 238 #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) 239 #else 240 #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) 241 #endif 242 243 #define SMC_insl(r,b,l) ({ int __i ; \ 244 dword *__b2; \ 245 __b2 = (dword *) b; \ 246 for (__i = 0; __i < l; __i++) { \ 247 *(__b2 + __i) = SMC_inl(r); \ 248 SMC_inl(0); \ 249 }; \ 250 }) 251 252 #ifdef CONFIG_XSENGINE 253 #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) 254 #else 255 #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) 256 #endif 257 #define SMC_outsl(r,b,l) ({ int __i; \ 258 dword *__b2; \ 259 __b2 = (dword *) b; \ 260 for (__i = 0; __i < l; __i++) { \ 261 SMC_outl( *(__b2 + __i), r); \ 262 } \ 263 }) 264 265 #endif /* CONFIG_SMC_USE_32_BIT */ 266 267 #endif 268 269 /*--------------------------------------------------------------- 270 . 271 . A description of the SMSC registers is probably in order here, 272 . although for details, the SMC datasheet is invaluable. 273 . 274 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which 275 . are accessed by writing a number into the BANK_SELECT register 276 . ( I also use a SMC_SELECT_BANK macro for this ). 277 . 278 . The banks are configured so that for most purposes, bank 2 is all 279 . that is needed for simple run time tasks. 280 -----------------------------------------------------------------------*/ 281 282 /* 283 . Bank Select Register: 284 . 285 . yyyy yyyy 0000 00xx 286 . xx = bank number 287 . yyyy yyyy = 0x33, for identification purposes. 288 */ 289 #define BANK_SELECT 14 290 291 /* Transmit Control Register */ 292 /* BANK 0 */ 293 #define TCR_REG 0x0000 /* transmit control register */ 294 #define TCR_ENABLE 0x0001 /* When 1 we can transmit */ 295 #define TCR_LOOP 0x0002 /* Controls output pin LBK */ 296 #define TCR_FORCOL 0x0004 /* When 1 will force a collision */ 297 #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ 298 #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ 299 #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ 300 #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ 301 #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ 302 #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ 303 #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ 304 305 #define TCR_CLEAR 0 /* do NOTHING */ 306 /* the default settings for the TCR register : */ 307 /* QUESTION: do I want to enable padding of short packets ? */ 308 #define TCR_DEFAULT TCR_ENABLE 309 310 311 /* EPH Status Register */ 312 /* BANK 0 */ 313 #define EPH_STATUS_REG 0x0002 314 #define ES_TX_SUC 0x0001 /* Last TX was successful */ 315 #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ 316 #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ 317 #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ 318 #define ES_16COL 0x0010 /* 16 Collisions Reached */ 319 #define ES_SQET 0x0020 /* Signal Quality Error Test */ 320 #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ 321 #define ES_TXDEFR 0x0080 /* Transmit Deferred */ 322 #define ES_LATCOL 0x0200 /* Late collision detected on last tx */ 323 #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ 324 #define ES_EXC_DEF 0x0800 /* Excessive Deferral */ 325 #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ 326 #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ 327 #define ES_TXUNRN 0x8000 /* Tx Underrun */ 328 329 330 /* Receive Control Register */ 331 /* BANK 0 */ 332 #define RCR_REG 0x0004 333 #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ 334 #define RCR_PRMS 0x0002 /* Enable promiscuous mode */ 335 #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ 336 #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ 337 #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ 338 #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ 339 #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ 340 #define RCR_SOFTRST 0x8000 /* resets the chip */ 341 342 /* the normal settings for the RCR register : */ 343 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 344 #define RCR_CLEAR 0x0 /* set it to a base state */ 345 346 /* Counter Register */ 347 /* BANK 0 */ 348 #define COUNTER_REG 0x0006 349 350 /* Memory Information Register */ 351 /* BANK 0 */ 352 #define MIR_REG 0x0008 353 354 /* Receive/Phy Control Register */ 355 /* BANK 0 */ 356 #define RPC_REG 0x000A 357 #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ 358 #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ 359 #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ 360 #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ 361 #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ 362 #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ 363 #define RPC_LED_RES (0x01) /* LED = Reserved */ 364 #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ 365 #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ 366 #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ 367 #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ 368 #define RPC_LED_TX (0x06) /* LED = TX packet occurred */ 369 #define RPC_LED_RX (0x07) /* LED = RX packet occurred */ 370 #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) 371 /* buggy schematic: LEDa -> yellow, LEDb --> green */ 372 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 373 | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 374 | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 375 #elif defined(CONFIG_ADNPESC1) 376 /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ 377 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 378 | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 379 | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 380 #else 381 /* SMSC reference design: LEDa --> green, LEDb --> yellow */ 382 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 383 | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ 384 | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) 385 #endif 386 387 /* Bank 0 0x000C is reserved */ 388 389 /* Bank Select Register */ 390 /* All Banks */ 391 #define BSR_REG 0x000E 392 393 394 /* Configuration Reg */ 395 /* BANK 1 */ 396 #define CONFIG_REG 0x0000 397 #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ 398 #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ 399 #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ 400 #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ 401 402 /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ 403 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 404 405 406 /* Base Address Register */ 407 /* BANK 1 */ 408 #define BASE_REG 0x0002 409 410 411 /* Individual Address Registers */ 412 /* BANK 1 */ 413 #define ADDR0_REG 0x0004 414 #define ADDR1_REG 0x0006 415 #define ADDR2_REG 0x0008 416 417 418 /* General Purpose Register */ 419 /* BANK 1 */ 420 #define GP_REG 0x000A 421 422 423 /* Control Register */ 424 /* BANK 1 */ 425 #define CTL_REG 0x000C 426 #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ 427 #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ 428 #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ 429 #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ 430 #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ 431 #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ 432 #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ 433 #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ 434 #define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ 435 436 /* MMU Command Register */ 437 /* BANK 2 */ 438 #define MMU_CMD_REG 0x0000 439 #define MC_BUSY 1 /* When 1 the last release has not completed */ 440 #define MC_NOP (0<<5) /* No Op */ 441 #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ 442 #define MC_RESET (2<<5) /* Reset MMU to initial state */ 443 #define MC_REMOVE (3<<5) /* Remove the current rx packet */ 444 #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ 445 #define MC_FREEPKT (5<<5) /* Release packet in PNR register */ 446 #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ 447 #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ 448 449 450 /* Packet Number Register */ 451 /* BANK 2 */ 452 #define PN_REG 0x0002 453 454 455 /* Allocation Result Register */ 456 /* BANK 2 */ 457 #define AR_REG 0x0003 458 #define AR_FAILED 0x80 /* Alocation Failed */ 459 460 461 /* RX FIFO Ports Register */ 462 /* BANK 2 */ 463 #define RXFIFO_REG 0x0004 /* Must be read as a word */ 464 #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ 465 466 467 /* TX FIFO Ports Register */ 468 /* BANK 2 */ 469 #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ 470 #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ 471 472 473 /* Pointer Register */ 474 /* BANK 2 */ 475 #define PTR_REG 0x0006 476 #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ 477 #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ 478 #define PTR_READ 0x2000 /* When 1 the operation is a read */ 479 #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ 480 481 482 /* Data Register */ 483 /* BANK 2 */ 484 #define SMC91111_DATA_REG 0x0008 485 486 487 /* Interrupt Status/Acknowledge Register */ 488 /* BANK 2 */ 489 #define SMC91111_INT_REG 0x000C 490 491 492 /* Interrupt Mask Register */ 493 /* BANK 2 */ 494 #define IM_REG 0x000D 495 #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ 496 #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ 497 #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ 498 #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ 499 #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ 500 #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ 501 #define IM_TX_INT 0x02 /* Transmit Interrrupt */ 502 #define IM_RCV_INT 0x01 /* Receive Interrupt */ 503 504 505 /* Multicast Table Registers */ 506 /* BANK 3 */ 507 #define MCAST_REG1 0x0000 508 #define MCAST_REG2 0x0002 509 #define MCAST_REG3 0x0004 510 #define MCAST_REG4 0x0006 511 512 513 /* Management Interface Register (MII) */ 514 /* BANK 3 */ 515 #define MII_REG 0x0008 516 #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ 517 #define MII_MDOE 0x0008 /* MII Output Enable */ 518 #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ 519 #define MII_MDI 0x0002 /* MII Input, pin MDI */ 520 #define MII_MDO 0x0001 /* MII Output, pin MDO */ 521 522 523 /* Revision Register */ 524 /* BANK 3 */ 525 #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ 526 527 528 /* Early RCV Register */ 529 /* BANK 3 */ 530 /* this is NOT on SMC9192 */ 531 #define ERCV_REG 0x000C 532 #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ 533 #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ 534 535 /* External Register */ 536 /* BANK 7 */ 537 #define EXT_REG 0x0000 538 539 540 #define CHIP_9192 3 541 #define CHIP_9194 4 542 #define CHIP_9195 5 543 #define CHIP_9196 6 544 #define CHIP_91100 7 545 #define CHIP_91100FD 8 546 #define CHIP_91111FD 9 547 548 #if 0 549 static const char * chip_ids[ 15 ] = { 550 NULL, NULL, NULL, 551 /* 3 */ "SMC91C90/91C92", 552 /* 4 */ "SMC91C94", 553 /* 5 */ "SMC91C95", 554 /* 6 */ "SMC91C96", 555 /* 7 */ "SMC91C100", 556 /* 8 */ "SMC91C100FD", 557 /* 9 */ "SMC91C111", 558 NULL, NULL, 559 NULL, NULL, NULL}; 560 #endif 561 562 /* 563 . Transmit status bits 564 */ 565 #define TS_SUCCESS 0x0001 566 #define TS_LOSTCAR 0x0400 567 #define TS_LATCOL 0x0200 568 #define TS_16COL 0x0010 569 570 /* 571 . Receive status bits 572 */ 573 #define RS_ALGNERR 0x8000 574 #define RS_BRODCAST 0x4000 575 #define RS_BADCRC 0x2000 576 #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ 577 #define RS_TOOLONG 0x0800 578 #define RS_TOOSHORT 0x0400 579 #define RS_MULTICAST 0x0001 580 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 581 582 583 /* PHY Types */ 584 enum { 585 PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ 586 PHY_LAN83C180 587 }; 588 589 590 /* PHY Register Addresses (LAN91C111 Internal PHY) */ 591 592 /* PHY Control Register */ 593 #define PHY_CNTL_REG 0x00 594 #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ 595 #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ 596 #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ 597 #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ 598 #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ 599 #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ 600 #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ 601 #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ 602 #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ 603 604 /* PHY Status Register */ 605 #define PHY_STAT_REG 0x01 606 #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ 607 #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ 608 #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ 609 #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ 610 #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ 611 #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ 612 #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ 613 #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ 614 #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ 615 #define PHY_STAT_LINK 0x0004 /* 1=valid link */ 616 #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ 617 #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ 618 619 /* PHY Identifier Registers */ 620 #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ 621 #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ 622 623 /* PHY Auto-Negotiation Advertisement Register */ 624 #define PHY_AD_REG 0x04 625 #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ 626 #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ 627 #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ 628 #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ 629 #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ 630 #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ 631 #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ 632 #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ 633 #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ 634 635 /* PHY Auto-negotiation Remote End Capability Register */ 636 #define PHY_RMT_REG 0x05 637 /* Uses same bit definitions as PHY_AD_REG */ 638 639 /* PHY Configuration Register 1 */ 640 #define PHY_CFG1_REG 0x10 641 #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ 642 #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ 643 #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ 644 #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ 645 #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ 646 #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ 647 #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ 648 #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ 649 #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ 650 #define PHY_CFG1_TLVL_MASK 0x003C 651 #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ 652 653 654 /* PHY Configuration Register 2 */ 655 #define PHY_CFG2_REG 0x11 656 #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ 657 #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ 658 #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ 659 #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ 660 661 /* PHY Status Output (and Interrupt status) Register */ 662 #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ 663 #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ 664 #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ 665 #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ 666 #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ 667 #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ 668 #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ 669 #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ 670 #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ 671 #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ 672 #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ 673 674 /* PHY Interrupt/Status Mask Register */ 675 #define PHY_MASK_REG 0x13 /* Interrupt Mask */ 676 /* Uses the same bit definitions as PHY_INT_REG */ 677 678 679 /*------------------------------------------------------------------------- 680 . I define some macros to make it easier to do somewhat common 681 . or slightly complicated, repeated tasks. 682 --------------------------------------------------------------------------*/ 683 684 /* select a register bank, 0 to 3 */ 685 686 #define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); } 687 688 /* this enables an interrupt in the interrupt mask register */ 689 #define SMC_ENABLE_INT(x) {\ 690 unsigned char mask;\ 691 SMC_SELECT_BANK(2);\ 692 mask = SMC_inb( IM_REG );\ 693 mask |= (x);\ 694 SMC_outb( mask, IM_REG ); \ 695 } 696 697 /* this disables an interrupt from the interrupt mask register */ 698 699 #define SMC_DISABLE_INT(x) {\ 700 unsigned char mask;\ 701 SMC_SELECT_BANK(2);\ 702 mask = SMC_inb( IM_REG );\ 703 mask &= ~(x);\ 704 SMC_outb( mask, IM_REG ); \ 705 } 706 707 /*---------------------------------------------------------------------- 708 . Define the interrupts that I want to receive from the card 709 . 710 . I want: 711 . IM_EPH_INT, for nasty errors 712 . IM_RCV_INT, for happy received packets 713 . IM_RX_OVRN_INT, because I have to kick the receiver 714 . IM_MDINT, for PHY Register 18 Status Changes 715 --------------------------------------------------------------------------*/ 716 #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ 717 IM_MDINT) 718 719 #endif /* _SMC_91111_H_ */ 720