xref: /openbmc/u-boot/drivers/net/smc91111.h (revision 5794619e)
1 /*------------------------------------------------------------------------
2  . smc91111.h - macros for the LAN91C111 Ethernet Driver
3  .
4  . (C) Copyright 2002
5  . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6  . Rolf Offermanns <rof@sysgo.de>
7  . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
8  .       Developed by Simple Network Magic Corporation (SNMC)
9  . Copyright (C) 1996 by Erik Stahlman (ES)
10  .
11  . This program is free software; you can redistribute it and/or modify
12  . it under the terms of the GNU General Public License as published by
13  . the Free Software Foundation; either version 2 of the License, or
14  . (at your option) any later version.
15  .
16  . This program is distributed in the hope that it will be useful,
17  . but WITHOUT ANY WARRANTY; without even the implied warranty of
18  . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  . GNU General Public License for more details.
20  .
21  . You should have received a copy of the GNU General Public License
22  . along with this program; if not, write to the Free Software
23  . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
24  .
25  . This file contains register information and access macros for
26  . the LAN91C111 single chip ethernet controller.  It is a modified
27  . version of the smc9194.h file.
28  .
29  . Information contained in this file was obtained from the LAN91C111
30  . manual from SMC.  To get a copy, if you really want one, you can find
31  . information under www.smsc.com.
32  .
33  . Authors
34  .	Erik Stahlman				( erik@vt.edu )
35  .	Daris A Nevil				( dnevil@snmc.com )
36  .
37  . History
38  . 03/16/01		Daris A Nevil	Modified for use with LAN91C111 device
39  .
40  ---------------------------------------------------------------------------*/
41 #ifndef _SMC91111_H_
42 #define _SMC91111_H_
43 
44 #include <asm/types.h>
45 #include <config.h>
46 
47 /*
48  * This function may be called by the board specific initialisation code
49  * in order to override the default mac address.
50  */
51 
52 void smc_set_mac_addr (const unsigned char *addr);
53 
54 
55 /* I want some simple types */
56 
57 typedef unsigned char			byte;
58 typedef unsigned short			word;
59 typedef unsigned long int		dword;
60 
61 struct smc91111_priv{
62 	u8 dev_num;
63 };
64 
65 /*
66  . DEBUGGING LEVELS
67  .
68  . 0 for normal operation
69  . 1 for slightly more details
70  . >2 for various levels of increasingly useless information
71  .    2 for interrupt tracking, status flags
72  .    3 for packet info
73  .    4 for complete packet dumps
74 */
75 /*#define SMC_DEBUG 0 */
76 
77 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
78 
79 #define	SMC_IO_EXTENT	16
80 
81 #ifdef CONFIG_PXA250
82 
83 #ifdef CONFIG_XSENGINE
84 #define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+((r)<<1))))
85 #define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
86 #define SMC_inb(a,p)  ({ \
87 	unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
88 	unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
89 	if (__p & 2) __v >>= 8; \
90 	else __v &= 0xff; \
91 	__v; })
92 #elif defined(CONFIG_XAENIAX)
93 #define SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r))))
94 #define SMC_inw(a,z)	({ \
95 	unsigned int __p = (unsigned int)((a)->iobase + (z)); \
96 	unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \
97 	if (__p & 3) __v >>= 16; \
98 	else __v &= 0xffff; \
99 	__v; })
100 #define SMC_inb(a,p)	({ \
101 	unsigned int ___v = SMC_inw((a),(p) & ~1); \
102 	if ((p) & 1) ___v >>= 8; \
103 	else ___v &= 0xff; \
104 	___v; })
105 #else
106 #define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r))))
107 #define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+(r))))
108 #define SMC_inb(a,p)	({ \
109 	unsigned int __p = (unsigned int)((a)->iobase + (p)); \
110 	unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
111 	if (__p & 1) __v >>= 8; \
112 	else __v &= 0xff; \
113 	__v; })
114 #endif
115 
116 #ifdef CONFIG_XSENGINE
117 #define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r<<1))) = d)
118 #define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r<<1))) = d)
119 #elif defined (CONFIG_XAENIAX)
120 #define SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r))) = d)
121 #define SMC_outw(a,d,p)	({ \
122 	dword __dwo = SMC_inl((a),(p) & ~3); \
123 	dword __dwn = (word)(d); \
124 	__dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \
125 	__dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \
126 	SMC_outl((a), __dwo, (p) & ~3); \
127 })
128 #else
129 #define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r))) = d)
130 #define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r))) = d)
131 #endif
132 
133 #define	SMC_outb(a,d,r)	({	word __d = (byte)(d);  \
134 				word __w = SMC_inw((a),(r)&~1);  \
135 				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
136 				__w |= ((r)&1) ? __d<<8 : __d;  \
137 				SMC_outw((a),__w,(r)&~1);  \
138 			})
139 
140 #define SMC_outsl(a,r,b,l)	({	int __i; \
141 					dword *__b2; \
142 					__b2 = (dword *) b; \
143 					for (__i = 0; __i < l; __i++) { \
144 					    SMC_outl((a), *(__b2 + __i), r); \
145 					} \
146 				})
147 
148 #define SMC_outsw(a,r,b,l)	({	int __i; \
149 					word *__b2; \
150 					__b2 = (word *) b; \
151 					for (__i = 0; __i < l; __i++) { \
152 					    SMC_outw((a), *(__b2 + __i), r); \
153 					} \
154 				})
155 
156 #define SMC_insl(a,r,b,l)	({	int __i ;  \
157 					dword *__b2;  \
158 					__b2 = (dword *) b;  \
159 					for (__i = 0; __i < l; __i++) {  \
160 					  *(__b2 + __i) = SMC_inl((a),(r));  \
161 					  SMC_inl((a),0);  \
162 					};  \
163 				})
164 
165 #define SMC_insw(a,r,b,l)		({	int __i ;  \
166 					word *__b2;  \
167 					__b2 = (word *) b;  \
168 					for (__i = 0; __i < l; __i++) {  \
169 					  *(__b2 + __i) = SMC_inw((a),(r));  \
170 					  SMC_inw((a),0);  \
171 					};  \
172 				})
173 
174 #define SMC_insb(a,r,b,l)	({	int __i ;  \
175 					byte *__b2;  \
176 					__b2 = (byte *) b;  \
177 					for (__i = 0; __i < l; __i++) {  \
178 					  *(__b2 + __i) = SMC_inb((a),(r));  \
179 					  SMC_inb((a),0);  \
180 					};  \
181 				})
182 
183 #elif defined(CONFIG_LEON)	/* if not CONFIG_PXA250 */
184 
185 #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); })
186 
187 #define SMC_LEON_SWAP32(_x_)			\
188     ({ dword _x = (_x_);			\
189        ((_x << 24) |				\
190        ((0x0000FF00UL & _x) <<  8) |		\
191        ((0x00FF0000UL & _x) >>  8) |		\
192        (_x  >> 24)); })
193 
194 #define	SMC_inl(a,r)	(SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0)))))
195 #define	SMC_inl_nosw(a,r)	((*(volatile dword *)((a)->iobase+((r)<<0))))
196 #define	SMC_inw(a,r)	(SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0)))))
197 #define	SMC_inw_nosw(a,r)	((*(volatile word *)((a)->iobase+((r)<<0))))
198 #define SMC_inb(a,p)	({ \
199 	word ___v = SMC_inw((a),(p) & ~1); \
200 	if ((p) & 1) ___v >>= 8; \
201 	else ___v &= 0xff; \
202 	___v; })
203 
204 #define	SMC_outl(a,d,r)	(*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d))
205 #define	SMC_outl_nosw(a,d,r)	(*(volatile dword *)((a)->iobase+((r)<<0))=(d))
206 #define	SMC_outw(a,d,r)	(*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d))
207 #define	SMC_outw_nosw(a,d,r)	(*(volatile word *)((a)->iobase+((r)<<0))=(d))
208 #define	SMC_outb(a,d,r)	do{	word __d = (byte)(d);  \
209 				word __w = SMC_inw((a),(r)&~1);  \
210 				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
211 				__w |= ((r)&1) ? __d<<8 : __d;  \
212 				SMC_outw((a),__w,(r)&~1);  \
213 			}while(0)
214 #define SMC_outsl(a,r,b,l)	do{	int __i; \
215 					dword *__b2; \
216 					__b2 = (dword *) b; \
217 					for (__i = 0; __i < l; __i++) { \
218 					    SMC_outl_nosw((a), *(__b2 + __i), r); \
219 					} \
220 				}while(0)
221 #define SMC_outsw(a,r,b,l)	do{	int __i; \
222 					word *__b2; \
223 					__b2 = (word *) b; \
224 					for (__i = 0; __i < l; __i++) { \
225 					    SMC_outw_nosw((a), *(__b2 + __i), r); \
226 					} \
227 				}while(0)
228 #define SMC_insl(a,r,b,l)	do{	int __i ;  \
229 					dword *__b2;  \
230 					__b2 = (dword *) b;  \
231 					for (__i = 0; __i < l; __i++) {  \
232 					  *(__b2 + __i) = SMC_inl_nosw((a),(r));  \
233 					};  \
234 				}while(0)
235 
236 #define SMC_insw(a,r,b,l)		do{	int __i ;  \
237 					word *__b2;  \
238 					__b2 = (word *) b;  \
239 					for (__i = 0; __i < l; __i++) {  \
240 					  *(__b2 + __i) = SMC_inw_nosw((a),(r));  \
241 					};  \
242 				}while(0)
243 
244 #define SMC_insb(a,r,b,l)		do{	int __i ;  \
245 					byte *__b2;  \
246 					__b2 = (byte *) b;  \
247 					for (__i = 0; __i < l; __i++) {  \
248 					  *(__b2 + __i) = SMC_inb((a),(r));  \
249 					};  \
250 				}while(0)
251 
252 #else				/* if not CONFIG_PXA250 and not CONFIG_LEON */
253 
254 #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
255 /*
256  * We have only 16 Bit PCMCIA access on Socket 0
257  */
258 
259 #ifdef CONFIG_ADNPESC1
260 #define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
261 #elif CONFIG_BLACKFIN
262 #define	SMC_inw(a,r)	({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
263 #else
264 #define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+(r))))
265 #endif
266 #define  SMC_inb(a,r)	(((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
267 
268 #ifdef CONFIG_ADNPESC1
269 #define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+((r)<<1))) = d)
270 #elif CONFIG_BLACKFIN
271 #define	SMC_outw(a,d,r)	{(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();}
272 #else
273 #define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r))) = d)
274 #endif
275 #define	SMC_outb(a,d,r)	({	word __d = (byte)(d);  \
276 				word __w = SMC_inw((a),(r)&~1);  \
277 				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
278 				__w |= ((r)&1) ? __d<<8 : __d;  \
279 				SMC_outw((a),__w,(r)&~1);  \
280 			})
281 #if 0
282 #define	SMC_outsw(a,r,b,l)	outsw((a)->iobase+(r), (b), (l))
283 #else
284 #define SMC_outsw(a,r,b,l)	({	int __i; \
285 					word *__b2; \
286 					__b2 = (word *) b; \
287 					for (__i = 0; __i < l; __i++) { \
288 					    SMC_outw((a), *(__b2 + __i), r); \
289 					} \
290 				})
291 #endif
292 
293 #if 0
294 #define	SMC_insw(a,r,b,l)	insw((a)->iobase+(r), (b), (l))
295 #else
296 #define SMC_insw(a,r,b,l)	({	int __i ;  \
297 					word *__b2;  \
298 					__b2 = (word *) b;  \
299 					for (__i = 0; __i < l; __i++) {  \
300 					  *(__b2 + __i) = SMC_inw((a),(r));  \
301 					  SMC_inw((a),0);  \
302 					};  \
303 				})
304 #endif
305 
306 #endif  /* CONFIG_SMC_USE_IOFUNCS */
307 
308 #if defined(CONFIG_SMC_USE_32_BIT)
309 
310 #ifdef CONFIG_XSENGINE
311 #define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r<<1))))
312 #else
313 #define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r))))
314 #endif
315 
316 #define SMC_insl(a,r,b,l)	({	int __i ;  \
317 					dword *__b2;  \
318 					__b2 = (dword *) b;  \
319 					for (__i = 0; __i < l; __i++) {  \
320 					  *(__b2 + __i) = SMC_inl((a),(r));  \
321 					  SMC_inl((a),0);  \
322 					};  \
323 				})
324 
325 #ifdef CONFIG_XSENGINE
326 #define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r<<1))) = d)
327 #else
328 #define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r))) = d)
329 #endif
330 #define SMC_outsl(a,r,b,l)	({	int __i; \
331 					dword *__b2; \
332 					__b2 = (dword *) b; \
333 					for (__i = 0; __i < l; __i++) { \
334 					    SMC_outl((a), *(__b2 + __i), r); \
335 					} \
336 				})
337 
338 #endif /* CONFIG_SMC_USE_32_BIT */
339 
340 #endif
341 
342 /*---------------------------------------------------------------
343  .
344  . A description of the SMSC registers is probably in order here,
345  . although for details, the SMC datasheet is invaluable.
346  .
347  . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
348  . are accessed by writing a number into the BANK_SELECT register
349  . ( I also use a SMC_SELECT_BANK macro for this ).
350  .
351  . The banks are configured so that for most purposes, bank 2 is all
352  . that is needed for simple run time tasks.
353  -----------------------------------------------------------------------*/
354 
355 /*
356  . Bank Select Register:
357  .
358  .		yyyy yyyy 0000 00xx
359  .		xx		= bank number
360  .		yyyy yyyy	= 0x33, for identification purposes.
361 */
362 #define	BANK_SELECT		14
363 
364 /* Transmit Control Register */
365 /* BANK 0  */
366 #define	TCR_REG		0x0000	/* transmit control register */
367 #define TCR_ENABLE	0x0001	/* When 1 we can transmit */
368 #define TCR_LOOP	0x0002	/* Controls output pin LBK */
369 #define TCR_FORCOL	0x0004	/* When 1 will force a collision */
370 #define TCR_PAD_EN	0x0080	/* When 1 will pad tx frames < 64 bytes w/0 */
371 #define TCR_NOCRC	0x0100	/* When 1 will not append CRC to tx frames */
372 #define TCR_MON_CSN	0x0400	/* When 1 tx monitors carrier */
373 #define TCR_FDUPLX	0x0800  /* When 1 enables full duplex operation */
374 #define TCR_STP_SQET	0x1000	/* When 1 stops tx if Signal Quality Error */
375 #define	TCR_EPH_LOOP	0x2000	/* When 1 enables EPH block loopback */
376 #define	TCR_SWFDUP	0x8000	/* When 1 enables Switched Full Duplex mode */
377 
378 #define	TCR_CLEAR	0	/* do NOTHING */
379 /* the default settings for the TCR register : */
380 /* QUESTION: do I want to enable padding of short packets ? */
381 #define	TCR_DEFAULT	TCR_ENABLE
382 
383 
384 /* EPH Status Register */
385 /* BANK 0  */
386 #define EPH_STATUS_REG	0x0002
387 #define ES_TX_SUC	0x0001	/* Last TX was successful */
388 #define ES_SNGL_COL	0x0002	/* Single collision detected for last tx */
389 #define ES_MUL_COL	0x0004	/* Multiple collisions detected for last tx */
390 #define ES_LTX_MULT	0x0008	/* Last tx was a multicast */
391 #define ES_16COL	0x0010	/* 16 Collisions Reached */
392 #define ES_SQET		0x0020	/* Signal Quality Error Test */
393 #define ES_LTXBRD	0x0040	/* Last tx was a broadcast */
394 #define ES_TXDEFR	0x0080	/* Transmit Deferred */
395 #define ES_LATCOL	0x0200	/* Late collision detected on last tx */
396 #define ES_LOSTCARR	0x0400	/* Lost Carrier Sense */
397 #define ES_EXC_DEF	0x0800	/* Excessive Deferral */
398 #define ES_CTR_ROL	0x1000	/* Counter Roll Over indication */
399 #define ES_LINK_OK	0x4000	/* Driven by inverted value of nLNK pin */
400 #define ES_TXUNRN	0x8000	/* Tx Underrun */
401 
402 
403 /* Receive Control Register */
404 /* BANK 0  */
405 #define	RCR_REG		0x0004
406 #define	RCR_RX_ABORT	0x0001	/* Set if a rx frame was aborted */
407 #define	RCR_PRMS	0x0002	/* Enable promiscuous mode */
408 #define	RCR_ALMUL	0x0004	/* When set accepts all multicast frames */
409 #define RCR_RXEN	0x0100	/* IFF this is set, we can receive packets */
410 #define	RCR_STRIP_CRC	0x0200	/* When set strips CRC from rx packets */
411 #define	RCR_ABORT_ENB	0x0200	/* When set will abort rx on collision */
412 #define	RCR_FILT_CAR	0x0400	/* When set filters leading 12 bit s of carrier */
413 #define RCR_SOFTRST	0x8000	/* resets the chip */
414 
415 /* the normal settings for the RCR register : */
416 #define	RCR_DEFAULT	(RCR_STRIP_CRC | RCR_RXEN)
417 #define RCR_CLEAR	0x0	/* set it to a base state */
418 
419 /* Counter Register */
420 /* BANK 0  */
421 #define	COUNTER_REG	0x0006
422 
423 /* Memory Information Register */
424 /* BANK 0  */
425 #define	MIR_REG		0x0008
426 
427 /* Receive/Phy Control Register */
428 /* BANK 0  */
429 #define	RPC_REG		0x000A
430 #define	RPC_SPEED	0x2000	/* When 1 PHY is in 100Mbps mode. */
431 #define	RPC_DPLX	0x1000	/* When 1 PHY is in Full-Duplex Mode */
432 #define	RPC_ANEG	0x0800	/* When 1 PHY is in Auto-Negotiate Mode */
433 #define	RPC_LSXA_SHFT	5	/* Bits to shift LS2A,LS1A,LS0A to lsb */
434 #define	RPC_LSXB_SHFT	2	/* Bits to get LS2B,LS1B,LS0B to lsb */
435 #define RPC_LED_100_10	(0x00)	/* LED = 100Mbps OR's with 10Mbps link detect */
436 #define RPC_LED_RES	(0x01)	/* LED = Reserved */
437 #define RPC_LED_10	(0x02)	/* LED = 10Mbps link detect */
438 #define RPC_LED_FD	(0x03)	/* LED = Full Duplex Mode */
439 #define RPC_LED_TX_RX	(0x04)	/* LED = TX or RX packet occurred */
440 #define RPC_LED_100	(0x05)	/* LED = 100Mbps link dectect */
441 #define RPC_LED_TX	(0x06)	/* LED = TX packet occurred */
442 #define RPC_LED_RX	(0x07)	/* LED = RX packet occurred */
443 #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
444 /* buggy schematic: LEDa -> yellow, LEDb --> green */
445 #define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
446 			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
447 			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
448 #elif defined(CONFIG_ADNPESC1)
449 /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
450 #define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
451 			| (RPC_LED_TX_RX << RPC_LSXA_SHFT)	\
452 			| (RPC_LED_100_10 << RPC_LSXB_SHFT)	)
453 #else
454 /* SMSC reference design: LEDa --> green, LEDb --> yellow */
455 #define RPC_DEFAULT	( RPC_SPEED | RPC_DPLX | RPC_ANEG	\
456 			| (RPC_LED_100_10 << RPC_LSXA_SHFT)	\
457 			| (RPC_LED_TX_RX << RPC_LSXB_SHFT)	)
458 #endif
459 
460 /* Bank 0 0x000C is reserved */
461 
462 /* Bank Select Register */
463 /* All Banks */
464 #define BSR_REG	0x000E
465 
466 
467 /* Configuration Reg */
468 /* BANK 1 */
469 #define CONFIG_REG	0x0000
470 #define CONFIG_EXT_PHY	0x0200	/* 1=external MII, 0=internal Phy */
471 #define CONFIG_GPCNTRL	0x0400	/* Inverse value drives pin nCNTRL */
472 #define CONFIG_NO_WAIT	0x1000	/* When 1 no extra wait states on ISA bus */
473 #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
474 
475 /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
476 #define CONFIG_DEFAULT	(CONFIG_EPH_POWER_EN)
477 
478 
479 /* Base Address Register */
480 /* BANK 1 */
481 #define	BASE_REG	0x0002
482 
483 
484 /* Individual Address Registers */
485 /* BANK 1 */
486 #define	ADDR0_REG	0x0004
487 #define	ADDR1_REG	0x0006
488 #define	ADDR2_REG	0x0008
489 
490 
491 /* General Purpose Register */
492 /* BANK 1 */
493 #define	GP_REG		0x000A
494 
495 
496 /* Control Register */
497 /* BANK 1 */
498 #define	CTL_REG		0x000C
499 #define CTL_RCV_BAD	0x4000 /* When 1 bad CRC packets are received */
500 #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
501 #define	CTL_LE_ENABLE	0x0080 /* When 1 enables Link Error interrupt */
502 #define	CTL_CR_ENABLE	0x0040 /* When 1 enables Counter Rollover interrupt */
503 #define	CTL_TE_ENABLE	0x0020 /* When 1 enables Transmit Error interrupt */
504 #define	CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
505 #define	CTL_RELOAD	0x0002 /* When set reads EEPROM into registers */
506 #define	CTL_STORE	0x0001 /* When set stores registers into EEPROM */
507 #define CTL_DEFAULT     (0x1A10) /* Autorelease enabled*/
508 
509 /* MMU Command Register */
510 /* BANK 2 */
511 #define MMU_CMD_REG	0x0000
512 #define MC_BUSY		1	/* When 1 the last release has not completed */
513 #define MC_NOP		(0<<5)	/* No Op */
514 #define	MC_ALLOC	(1<<5)	/* OR with number of 256 byte packets */
515 #define	MC_RESET	(2<<5)	/* Reset MMU to initial state */
516 #define	MC_REMOVE	(3<<5)	/* Remove the current rx packet */
517 #define MC_RELEASE	(4<<5)	/* Remove and release the current rx packet */
518 #define MC_FREEPKT	(5<<5)	/* Release packet in PNR register */
519 #define MC_ENQUEUE	(6<<5)	/* Enqueue the packet for transmit */
520 #define MC_RSTTXFIFO	(7<<5)	/* Reset the TX FIFOs */
521 
522 
523 /* Packet Number Register */
524 /* BANK 2 */
525 #define	PN_REG		0x0002
526 
527 
528 /* Allocation Result Register */
529 /* BANK 2 */
530 #define	AR_REG		0x0003
531 #define AR_FAILED	0x80	/* Alocation Failed */
532 
533 
534 /* RX FIFO Ports Register */
535 /* BANK 2 */
536 #define RXFIFO_REG	0x0004	/* Must be read as a word */
537 #define RXFIFO_REMPTY	0x8000	/* RX FIFO Empty */
538 
539 
540 /* TX FIFO Ports Register */
541 /* BANK 2 */
542 #define TXFIFO_REG	RXFIFO_REG	/* Must be read as a word */
543 #define TXFIFO_TEMPTY	0x80	/* TX FIFO Empty */
544 
545 
546 /* Pointer Register */
547 /* BANK 2 */
548 #define PTR_REG		0x0006
549 #define	PTR_RCV		0x8000 /* 1=Receive area, 0=Transmit area */
550 #define	PTR_AUTOINC	0x4000 /* Auto increment the pointer on each access */
551 #define PTR_READ	0x2000 /* When 1 the operation is a read */
552 #define PTR_NOTEMPTY	0x0800 /* When 1 _do not_ write fifo DATA REG */
553 
554 
555 /* Data Register */
556 /* BANK 2 */
557 #define	SMC91111_DATA_REG	0x0008
558 
559 
560 /* Interrupt Status/Acknowledge Register */
561 /* BANK 2 */
562 #define	SMC91111_INT_REG	0x000C
563 
564 
565 /* Interrupt Mask Register */
566 /* BANK 2 */
567 #define IM_REG		0x000D
568 #define	IM_MDINT	0x80 /* PHY MI Register 18 Interrupt */
569 #define	IM_ERCV_INT	0x40 /* Early Receive Interrupt */
570 #define	IM_EPH_INT	0x20 /* Set by Etheret Protocol Handler section */
571 #define	IM_RX_OVRN_INT	0x10 /* Set by Receiver Overruns */
572 #define	IM_ALLOC_INT	0x08 /* Set when allocation request is completed */
573 #define	IM_TX_EMPTY_INT	0x04 /* Set if the TX FIFO goes empty */
574 #define	IM_TX_INT	0x02 /* Transmit Interrrupt */
575 #define IM_RCV_INT	0x01 /* Receive Interrupt */
576 
577 
578 /* Multicast Table Registers */
579 /* BANK 3 */
580 #define	MCAST_REG1	0x0000
581 #define	MCAST_REG2	0x0002
582 #define	MCAST_REG3	0x0004
583 #define	MCAST_REG4	0x0006
584 
585 
586 /* Management Interface Register (MII) */
587 /* BANK 3 */
588 #define	MII_REG		0x0008
589 #define MII_MSK_CRS100	0x4000 /* Disables CRS100 detection during tx half dup */
590 #define MII_MDOE	0x0008 /* MII Output Enable */
591 #define MII_MCLK	0x0004 /* MII Clock, pin MDCLK */
592 #define MII_MDI		0x0002 /* MII Input, pin MDI */
593 #define MII_MDO		0x0001 /* MII Output, pin MDO */
594 
595 
596 /* Revision Register */
597 /* BANK 3 */
598 #define	REV_REG		0x000A /* ( hi: chip id   low: rev # ) */
599 
600 
601 /* Early RCV Register */
602 /* BANK 3 */
603 /* this is NOT on SMC9192 */
604 #define	ERCV_REG	0x000C
605 #define ERCV_RCV_DISCRD	0x0080 /* When 1 discards a packet being received */
606 #define ERCV_THRESHOLD	0x001F /* ERCV Threshold Mask */
607 
608 /* External Register */
609 /* BANK 7 */
610 #define	EXT_REG		0x0000
611 
612 
613 #define CHIP_9192	3
614 #define CHIP_9194	4
615 #define CHIP_9195	5
616 #define CHIP_9196	6
617 #define CHIP_91100	7
618 #define CHIP_91100FD	8
619 #define CHIP_91111FD	9
620 
621 #if 0
622 static const char * chip_ids[ 15 ] =  {
623 	NULL, NULL, NULL,
624 	/* 3 */ "SMC91C90/91C92",
625 	/* 4 */ "SMC91C94",
626 	/* 5 */ "SMC91C95",
627 	/* 6 */ "SMC91C96",
628 	/* 7 */ "SMC91C100",
629 	/* 8 */ "SMC91C100FD",
630 	/* 9 */ "SMC91C111",
631 	NULL, NULL,
632 	NULL, NULL, NULL};
633 #endif
634 
635 /*
636  . Transmit status bits
637 */
638 #define TS_SUCCESS 0x0001
639 #define TS_LOSTCAR 0x0400
640 #define TS_LATCOL  0x0200
641 #define TS_16COL   0x0010
642 
643 /*
644  . Receive status bits
645 */
646 #define RS_ALGNERR	0x8000
647 #define RS_BRODCAST	0x4000
648 #define RS_BADCRC	0x2000
649 #define RS_ODDFRAME	0x1000	/* bug: the LAN91C111 never sets this on receive */
650 #define RS_TOOLONG	0x0800
651 #define RS_TOOSHORT	0x0400
652 #define RS_MULTICAST	0x0001
653 #define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
654 
655 
656 /* PHY Types */
657 enum {
658 	PHY_LAN83C183 = 1,	/* LAN91C111 Internal PHY */
659 	PHY_LAN83C180
660 };
661 
662 
663 /* PHY Register Addresses (LAN91C111 Internal PHY) */
664 
665 /* PHY Control Register */
666 #define PHY_CNTL_REG		0x00
667 #define PHY_CNTL_RST		0x8000	/* 1=PHY Reset */
668 #define PHY_CNTL_LPBK		0x4000	/* 1=PHY Loopback */
669 #define PHY_CNTL_SPEED		0x2000	/* 1=100Mbps, 0=10Mpbs */
670 #define PHY_CNTL_ANEG_EN	0x1000 /* 1=Enable Auto negotiation */
671 #define PHY_CNTL_PDN		0x0800	/* 1=PHY Power Down mode */
672 #define PHY_CNTL_MII_DIS	0x0400	/* 1=MII 4 bit interface disabled */
673 #define PHY_CNTL_ANEG_RST	0x0200 /* 1=Reset Auto negotiate */
674 #define PHY_CNTL_DPLX		0x0100	/* 1=Full Duplex, 0=Half Duplex */
675 #define PHY_CNTL_COLTST		0x0080	/* 1= MII Colision Test */
676 
677 /* PHY Status Register */
678 #define PHY_STAT_REG		0x01
679 #define PHY_STAT_CAP_T4		0x8000	/* 1=100Base-T4 capable */
680 #define PHY_STAT_CAP_TXF	0x4000	/* 1=100Base-X full duplex capable */
681 #define PHY_STAT_CAP_TXH	0x2000	/* 1=100Base-X half duplex capable */
682 #define PHY_STAT_CAP_TF		0x1000	/* 1=10Mbps full duplex capable */
683 #define PHY_STAT_CAP_TH		0x0800	/* 1=10Mbps half duplex capable */
684 #define PHY_STAT_CAP_SUPR	0x0040	/* 1=recv mgmt frames with not preamble */
685 #define PHY_STAT_ANEG_ACK	0x0020	/* 1=ANEG has completed */
686 #define PHY_STAT_REM_FLT	0x0010	/* 1=Remote Fault detected */
687 #define PHY_STAT_CAP_ANEG	0x0008	/* 1=Auto negotiate capable */
688 #define PHY_STAT_LINK		0x0004	/* 1=valid link */
689 #define PHY_STAT_JAB		0x0002	/* 1=10Mbps jabber condition */
690 #define PHY_STAT_EXREG		0x0001	/* 1=extended registers implemented */
691 
692 /* PHY Identifier Registers */
693 #define PHY_ID1_REG		0x02	/* PHY Identifier 1 */
694 #define PHY_ID2_REG		0x03	/* PHY Identifier 2 */
695 
696 /* PHY Auto-Negotiation Advertisement Register */
697 #define PHY_AD_REG		0x04
698 #define PHY_AD_NP		0x8000	/* 1=PHY requests exchange of Next Page */
699 #define PHY_AD_ACK		0x4000	/* 1=got link code word from remote */
700 #define PHY_AD_RF		0x2000	/* 1=advertise remote fault */
701 #define PHY_AD_T4		0x0200	/* 1=PHY is capable of 100Base-T4 */
702 #define PHY_AD_TX_FDX		0x0100	/* 1=PHY is capable of 100Base-TX FDPLX */
703 #define PHY_AD_TX_HDX		0x0080	/* 1=PHY is capable of 100Base-TX HDPLX */
704 #define PHY_AD_10_FDX		0x0040	/* 1=PHY is capable of 10Base-T FDPLX */
705 #define PHY_AD_10_HDX		0x0020	/* 1=PHY is capable of 10Base-T HDPLX */
706 #define PHY_AD_CSMA		0x0001	/* 1=PHY is capable of 802.3 CMSA */
707 
708 /* PHY Auto-negotiation Remote End Capability Register */
709 #define PHY_RMT_REG		0x05
710 /* Uses same bit definitions as PHY_AD_REG */
711 
712 /* PHY Configuration Register 1 */
713 #define PHY_CFG1_REG		0x10
714 #define PHY_CFG1_LNKDIS		0x8000	/* 1=Rx Link Detect Function disabled */
715 #define PHY_CFG1_XMTDIS		0x4000	/* 1=TP Transmitter Disabled */
716 #define PHY_CFG1_XMTPDN		0x2000	/* 1=TP Transmitter Powered Down */
717 #define PHY_CFG1_BYPSCR		0x0400	/* 1=Bypass scrambler/descrambler */
718 #define PHY_CFG1_UNSCDS		0x0200	/* 1=Unscramble Idle Reception Disable */
719 #define PHY_CFG1_EQLZR		0x0100	/* 1=Rx Equalizer Disabled */
720 #define PHY_CFG1_CABLE		0x0080	/* 1=STP(150ohm), 0=UTP(100ohm) */
721 #define PHY_CFG1_RLVL0		0x0040	/* 1=Rx Squelch level reduced by 4.5db */
722 #define PHY_CFG1_TLVL_SHIFT	2	/* Transmit Output Level Adjust */
723 #define PHY_CFG1_TLVL_MASK	0x003C
724 #define PHY_CFG1_TRF_MASK	0x0003	/* Transmitter Rise/Fall time */
725 
726 
727 /* PHY Configuration Register 2 */
728 #define PHY_CFG2_REG		0x11
729 #define PHY_CFG2_APOLDIS	0x0020	/* 1=Auto Polarity Correction disabled */
730 #define PHY_CFG2_JABDIS		0x0010	/* 1=Jabber disabled */
731 #define PHY_CFG2_MREG		0x0008	/* 1=Multiple register access (MII mgt) */
732 #define PHY_CFG2_INTMDIO	0x0004	/* 1=Interrupt signaled with MDIO pulseo */
733 
734 /* PHY Status Output (and Interrupt status) Register */
735 #define PHY_INT_REG		0x12	/* Status Output (Interrupt Status) */
736 #define PHY_INT_INT		0x8000	/* 1=bits have changed since last read */
737 #define	PHY_INT_LNKFAIL		0x4000	/* 1=Link Not detected */
738 #define PHY_INT_LOSSSYNC	0x2000	/* 1=Descrambler has lost sync */
739 #define PHY_INT_CWRD		0x1000	/* 1=Invalid 4B5B code detected on rx */
740 #define PHY_INT_SSD		0x0800	/* 1=No Start Of Stream detected on rx */
741 #define PHY_INT_ESD		0x0400	/* 1=No End Of Stream detected on rx */
742 #define PHY_INT_RPOL		0x0200	/* 1=Reverse Polarity detected */
743 #define PHY_INT_JAB		0x0100	/* 1=Jabber detected */
744 #define PHY_INT_SPDDET		0x0080	/* 1=100Base-TX mode, 0=10Base-T mode */
745 #define PHY_INT_DPLXDET		0x0040	/* 1=Device in Full Duplex */
746 
747 /* PHY Interrupt/Status Mask Register */
748 #define PHY_MASK_REG		0x13	/* Interrupt Mask */
749 /* Uses the same bit definitions as PHY_INT_REG */
750 
751 
752 /*-------------------------------------------------------------------------
753  .  I define some macros to make it easier to do somewhat common
754  . or slightly complicated, repeated tasks.
755  --------------------------------------------------------------------------*/
756 
757 /* select a register bank, 0 to 3  */
758 
759 #define SMC_SELECT_BANK(a,x)  { SMC_outw((a), (x), BANK_SELECT ); }
760 
761 /* this enables an interrupt in the interrupt mask register */
762 #define SMC_ENABLE_INT(a,x) {\
763 		unsigned char mask;\
764 		SMC_SELECT_BANK((a),2);\
765 		mask = SMC_inb((a), IM_REG );\
766 		mask |= (x);\
767 		SMC_outb( (a), mask, IM_REG ); \
768 }
769 
770 /* this disables an interrupt from the interrupt mask register */
771 
772 #define SMC_DISABLE_INT(a,x) {\
773 		unsigned char mask;\
774 		SMC_SELECT_BANK(2);\
775 		mask = SMC_inb( (a), IM_REG );\
776 		mask &= ~(x);\
777 		SMC_outb( (a), mask, IM_REG ); \
778 }
779 
780 /*----------------------------------------------------------------------
781  . Define the interrupts that I want to receive from the card
782  .
783  . I want:
784  .  IM_EPH_INT, for nasty errors
785  .  IM_RCV_INT, for happy received packets
786  .  IM_RX_OVRN_INT, because I have to kick the receiver
787  .  IM_MDINT, for PHY Register 18 Status Changes
788  --------------------------------------------------------------------------*/
789 #define SMC_INTERRUPT_MASK   (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
790 	IM_MDINT)
791 
792 #endif  /* _SMC_91111_H_ */
793