1 /*------------------------------------------------------------------------ 2 . smc91111.h - macros for the LAN91C111 Ethernet Driver 3 . 4 . (C) Copyright 2002 5 . Sysgo Real-Time Solutions, GmbH <www.elinos.com> 6 . Rolf Offermanns <rof@sysgo.de> 7 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 8 . Developed by Simple Network Magic Corporation (SNMC) 9 . Copyright (C) 1996 by Erik Stahlman (ES) 10 . 11 * SPDX-License-Identifier: GPL-2.0+ 12 . 13 . This file contains register information and access macros for 14 . the LAN91C111 single chip ethernet controller. It is a modified 15 . version of the smc9194.h file. 16 . 17 . Information contained in this file was obtained from the LAN91C111 18 . manual from SMC. To get a copy, if you really want one, you can find 19 . information under www.smsc.com. 20 . 21 . Authors 22 . Erik Stahlman ( erik@vt.edu ) 23 . Daris A Nevil ( dnevil@snmc.com ) 24 . 25 . History 26 . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device 27 . 28 ---------------------------------------------------------------------------*/ 29 #ifndef _SMC91111_H_ 30 #define _SMC91111_H_ 31 32 #include <asm/types.h> 33 #include <config.h> 34 35 /* 36 * This function may be called by the board specific initialisation code 37 * in order to override the default mac address. 38 */ 39 40 void smc_set_mac_addr (const unsigned char *addr); 41 42 43 /* I want some simple types */ 44 45 typedef unsigned char byte; 46 typedef unsigned short word; 47 typedef unsigned long int dword; 48 49 struct smc91111_priv{ 50 u8 dev_num; 51 }; 52 53 /* 54 . DEBUGGING LEVELS 55 . 56 . 0 for normal operation 57 . 1 for slightly more details 58 . >2 for various levels of increasingly useless information 59 . 2 for interrupt tracking, status flags 60 . 3 for packet info 61 . 4 for complete packet dumps 62 */ 63 /*#define SMC_DEBUG 0 */ 64 65 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 66 67 #define SMC_IO_EXTENT 16 68 69 #ifdef CONFIG_CPU_PXA25X 70 71 #ifdef CONFIG_XSENGINE 72 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) 73 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) 74 #define SMC_inb(a,p) ({ \ 75 unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \ 76 unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ 77 if (__p & 2) __v >>= 8; \ 78 else __v &= 0xff; \ 79 __v; }) 80 #elif defined(CONFIG_XAENIAX) 81 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) 82 #define SMC_inw(a,z) ({ \ 83 unsigned int __p = (unsigned int)((a)->iobase + (z)); \ 84 unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ 85 if (__p & 3) __v >>= 16; \ 86 else __v &= 0xffff; \ 87 __v; }) 88 #define SMC_inb(a,p) ({ \ 89 unsigned int ___v = SMC_inw((a),(p) & ~1); \ 90 if ((p) & 1) ___v >>= 8; \ 91 else ___v &= 0xff; \ 92 ___v; }) 93 #else 94 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) 95 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) 96 #define SMC_inb(a,p) ({ \ 97 unsigned int __p = (unsigned int)((a)->iobase + (p)); \ 98 unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ 99 if (__p & 1) __v >>= 8; \ 100 else __v &= 0xff; \ 101 __v; }) 102 #endif 103 104 #ifdef CONFIG_XSENGINE 105 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) 106 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) 107 #elif defined (CONFIG_XAENIAX) 108 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) 109 #define SMC_outw(a,d,p) ({ \ 110 dword __dwo = SMC_inl((a),(p) & ~3); \ 111 dword __dwn = (word)(d); \ 112 __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ 113 __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ 114 SMC_outl((a), __dwo, (p) & ~3); \ 115 }) 116 #else 117 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) 118 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) 119 #endif 120 121 #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ 122 word __w = SMC_inw((a),(r)&~1); \ 123 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 124 __w |= ((r)&1) ? __d<<8 : __d; \ 125 SMC_outw((a),__w,(r)&~1); \ 126 }) 127 128 #define SMC_outsl(a,r,b,l) ({ int __i; \ 129 dword *__b2; \ 130 __b2 = (dword *) b; \ 131 for (__i = 0; __i < l; __i++) { \ 132 SMC_outl((a), *(__b2 + __i), r); \ 133 } \ 134 }) 135 136 #define SMC_outsw(a,r,b,l) ({ int __i; \ 137 word *__b2; \ 138 __b2 = (word *) b; \ 139 for (__i = 0; __i < l; __i++) { \ 140 SMC_outw((a), *(__b2 + __i), r); \ 141 } \ 142 }) 143 144 #define SMC_insl(a,r,b,l) ({ int __i ; \ 145 dword *__b2; \ 146 __b2 = (dword *) b; \ 147 for (__i = 0; __i < l; __i++) { \ 148 *(__b2 + __i) = SMC_inl((a),(r)); \ 149 SMC_inl((a),0); \ 150 }; \ 151 }) 152 153 #define SMC_insw(a,r,b,l) ({ int __i ; \ 154 word *__b2; \ 155 __b2 = (word *) b; \ 156 for (__i = 0; __i < l; __i++) { \ 157 *(__b2 + __i) = SMC_inw((a),(r)); \ 158 SMC_inw((a),0); \ 159 }; \ 160 }) 161 162 #define SMC_insb(a,r,b,l) ({ int __i ; \ 163 byte *__b2; \ 164 __b2 = (byte *) b; \ 165 for (__i = 0; __i < l; __i++) { \ 166 *(__b2 + __i) = SMC_inb((a),(r)); \ 167 SMC_inb((a),0); \ 168 }; \ 169 }) 170 171 #elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */ 172 173 #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) 174 175 #define SMC_LEON_SWAP32(_x_) \ 176 ({ dword _x = (_x_); \ 177 ((_x << 24) | \ 178 ((0x0000FF00UL & _x) << 8) | \ 179 ((0x00FF0000UL & _x) >> 8) | \ 180 (_x >> 24)); }) 181 182 #define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0))))) 183 #define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0)))) 184 #define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0))))) 185 #define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0)))) 186 #define SMC_inb(a,p) ({ \ 187 word ___v = SMC_inw((a),(p) & ~1); \ 188 if ((p) & 1) ___v >>= 8; \ 189 else ___v &= 0xff; \ 190 ___v; }) 191 192 #define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d)) 193 #define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d)) 194 #define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d)) 195 #define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d)) 196 #define SMC_outb(a,d,r) do{ word __d = (byte)(d); \ 197 word __w = SMC_inw((a),(r)&~1); \ 198 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 199 __w |= ((r)&1) ? __d<<8 : __d; \ 200 SMC_outw((a),__w,(r)&~1); \ 201 }while(0) 202 #define SMC_outsl(a,r,b,l) do{ int __i; \ 203 dword *__b2; \ 204 __b2 = (dword *) b; \ 205 for (__i = 0; __i < l; __i++) { \ 206 SMC_outl_nosw((a), *(__b2 + __i), r); \ 207 } \ 208 }while(0) 209 #define SMC_outsw(a,r,b,l) do{ int __i; \ 210 word *__b2; \ 211 __b2 = (word *) b; \ 212 for (__i = 0; __i < l; __i++) { \ 213 SMC_outw_nosw((a), *(__b2 + __i), r); \ 214 } \ 215 }while(0) 216 #define SMC_insl(a,r,b,l) do{ int __i ; \ 217 dword *__b2; \ 218 __b2 = (dword *) b; \ 219 for (__i = 0; __i < l; __i++) { \ 220 *(__b2 + __i) = SMC_inl_nosw((a),(r)); \ 221 }; \ 222 }while(0) 223 224 #define SMC_insw(a,r,b,l) do{ int __i ; \ 225 word *__b2; \ 226 __b2 = (word *) b; \ 227 for (__i = 0; __i < l; __i++) { \ 228 *(__b2 + __i) = SMC_inw_nosw((a),(r)); \ 229 }; \ 230 }while(0) 231 232 #define SMC_insb(a,r,b,l) do{ int __i ; \ 233 byte *__b2; \ 234 __b2 = (byte *) b; \ 235 for (__i = 0; __i < l; __i++) { \ 236 *(__b2 + __i) = SMC_inb((a),(r)); \ 237 }; \ 238 }while(0) 239 #elif defined(CONFIG_MS7206SE) 240 #define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); }) 241 #define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r))) 242 #define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01)))) 243 #define SMC_insw(a, r, b, l) \ 244 do { \ 245 int __i; \ 246 word *__b2 = (word *)(b); \ 247 for (__i = 0; __i < (l); __i++) { \ 248 *__b2++ = SWAB7206(SMC_inw(a, r)); \ 249 } \ 250 } while (0) 251 #define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d) 252 #define SMC_outb(a, d, r) ({ word __d = (byte)(d); \ 253 word __w = SMC_inw((a), ((r)&(~1))); \ 254 if (((r) & 1)) \ 255 __w = (__w & 0x00ff) | (__d << 8); \ 256 else \ 257 __w = (__w & 0xff00) | (__d); \ 258 SMC_outw((a), __w, ((r)&(~1))); \ 259 }) 260 #define SMC_outsw(a, r, b, l) \ 261 do { \ 262 int __i; \ 263 word *__b2 = (word *)(b); \ 264 for (__i = 0; __i < (l); __i++) { \ 265 SMC_outw(a, SWAB7206(*__b2), r); \ 266 __b2++; \ 267 } \ 268 } while (0) 269 #else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */ 270 271 #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ 272 /* 273 * We have only 16 Bit PCMCIA access on Socket 0 274 */ 275 276 #ifdef CONFIG_ADNPESC1 277 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) 278 #elif CONFIG_BLACKFIN 279 #define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) 280 #elif CONFIG_ARM64 281 #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) 282 #else 283 #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) 284 #endif 285 #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) 286 287 #ifdef CONFIG_ADNPESC1 288 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) 289 #elif CONFIG_BLACKFIN 290 #define SMC_outw(a, d, r) \ 291 ({ (*((volatile word*)((a)->iobase+((r)))) = d); \ 292 SSYNC(); \ 293 }) 294 #elif CONFIG_ARM64 295 #define SMC_outw(a, d, r) \ 296 (*((volatile word*)((a)->iobase+((dword)(r)))) = d) 297 #else 298 #define SMC_outw(a, d, r) \ 299 (*((volatile word*)((a)->iobase+(r))) = d) 300 #endif 301 #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ 302 word __w = SMC_inw((a),(r)&~1); \ 303 __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 304 __w |= ((r)&1) ? __d<<8 : __d; \ 305 SMC_outw((a),__w,(r)&~1); \ 306 }) 307 #if 0 308 #define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l)) 309 #else 310 #define SMC_outsw(a,r,b,l) ({ int __i; \ 311 word *__b2; \ 312 __b2 = (word *) b; \ 313 for (__i = 0; __i < l; __i++) { \ 314 SMC_outw((a), *(__b2 + __i), r); \ 315 } \ 316 }) 317 #endif 318 319 #if 0 320 #define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l)) 321 #else 322 #define SMC_insw(a,r,b,l) ({ int __i ; \ 323 word *__b2; \ 324 __b2 = (word *) b; \ 325 for (__i = 0; __i < l; __i++) { \ 326 *(__b2 + __i) = SMC_inw((a),(r)); \ 327 SMC_inw((a),0); \ 328 }; \ 329 }) 330 #endif 331 332 #endif /* CONFIG_SMC_USE_IOFUNCS */ 333 334 #if defined(CONFIG_SMC_USE_32_BIT) 335 336 #ifdef CONFIG_XSENGINE 337 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) 338 #else 339 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) 340 #endif 341 342 #define SMC_insl(a,r,b,l) ({ int __i ; \ 343 dword *__b2; \ 344 __b2 = (dword *) b; \ 345 for (__i = 0; __i < l; __i++) { \ 346 *(__b2 + __i) = SMC_inl((a),(r)); \ 347 SMC_inl((a),0); \ 348 }; \ 349 }) 350 351 #ifdef CONFIG_XSENGINE 352 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) 353 #else 354 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) 355 #endif 356 #define SMC_outsl(a,r,b,l) ({ int __i; \ 357 dword *__b2; \ 358 __b2 = (dword *) b; \ 359 for (__i = 0; __i < l; __i++) { \ 360 SMC_outl((a), *(__b2 + __i), r); \ 361 } \ 362 }) 363 364 #endif /* CONFIG_SMC_USE_32_BIT */ 365 366 #endif 367 368 /*--------------------------------------------------------------- 369 . 370 . A description of the SMSC registers is probably in order here, 371 . although for details, the SMC datasheet is invaluable. 372 . 373 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which 374 . are accessed by writing a number into the BANK_SELECT register 375 . ( I also use a SMC_SELECT_BANK macro for this ). 376 . 377 . The banks are configured so that for most purposes, bank 2 is all 378 . that is needed for simple run time tasks. 379 -----------------------------------------------------------------------*/ 380 381 /* 382 . Bank Select Register: 383 . 384 . yyyy yyyy 0000 00xx 385 . xx = bank number 386 . yyyy yyyy = 0x33, for identification purposes. 387 */ 388 #define BANK_SELECT 14 389 390 /* Transmit Control Register */ 391 /* BANK 0 */ 392 #define TCR_REG 0x0000 /* transmit control register */ 393 #define TCR_ENABLE 0x0001 /* When 1 we can transmit */ 394 #define TCR_LOOP 0x0002 /* Controls output pin LBK */ 395 #define TCR_FORCOL 0x0004 /* When 1 will force a collision */ 396 #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ 397 #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ 398 #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ 399 #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ 400 #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ 401 #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ 402 #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ 403 404 #define TCR_CLEAR 0 /* do NOTHING */ 405 /* the default settings for the TCR register : */ 406 /* QUESTION: do I want to enable padding of short packets ? */ 407 #define TCR_DEFAULT TCR_ENABLE 408 409 410 /* EPH Status Register */ 411 /* BANK 0 */ 412 #define EPH_STATUS_REG 0x0002 413 #define ES_TX_SUC 0x0001 /* Last TX was successful */ 414 #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ 415 #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ 416 #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ 417 #define ES_16COL 0x0010 /* 16 Collisions Reached */ 418 #define ES_SQET 0x0020 /* Signal Quality Error Test */ 419 #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ 420 #define ES_TXDEFR 0x0080 /* Transmit Deferred */ 421 #define ES_LATCOL 0x0200 /* Late collision detected on last tx */ 422 #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ 423 #define ES_EXC_DEF 0x0800 /* Excessive Deferral */ 424 #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ 425 #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ 426 #define ES_TXUNRN 0x8000 /* Tx Underrun */ 427 428 429 /* Receive Control Register */ 430 /* BANK 0 */ 431 #define RCR_REG 0x0004 432 #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ 433 #define RCR_PRMS 0x0002 /* Enable promiscuous mode */ 434 #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ 435 #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ 436 #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ 437 #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ 438 #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ 439 #define RCR_SOFTRST 0x8000 /* resets the chip */ 440 441 /* the normal settings for the RCR register : */ 442 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 443 #define RCR_CLEAR 0x0 /* set it to a base state */ 444 445 /* Counter Register */ 446 /* BANK 0 */ 447 #define COUNTER_REG 0x0006 448 449 /* Memory Information Register */ 450 /* BANK 0 */ 451 #define MIR_REG 0x0008 452 453 /* Receive/Phy Control Register */ 454 /* BANK 0 */ 455 #define RPC_REG 0x000A 456 #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ 457 #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ 458 #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ 459 #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ 460 #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ 461 #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ 462 #define RPC_LED_RES (0x01) /* LED = Reserved */ 463 #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ 464 #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ 465 #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ 466 #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ 467 #define RPC_LED_TX (0x06) /* LED = TX packet occurred */ 468 #define RPC_LED_RX (0x07) /* LED = RX packet occurred */ 469 #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) 470 /* buggy schematic: LEDa -> yellow, LEDb --> green */ 471 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 472 | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 473 | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 474 #elif defined(CONFIG_ADNPESC1) 475 /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ 476 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 477 | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 478 | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 479 #else 480 /* SMSC reference design: LEDa --> green, LEDb --> yellow */ 481 #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 482 | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ 483 | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) 484 #endif 485 486 /* Bank 0 0x000C is reserved */ 487 488 /* Bank Select Register */ 489 /* All Banks */ 490 #define BSR_REG 0x000E 491 492 493 /* Configuration Reg */ 494 /* BANK 1 */ 495 #define CONFIG_REG 0x0000 496 #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ 497 #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ 498 #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ 499 #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ 500 501 /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ 502 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 503 504 505 /* Base Address Register */ 506 /* BANK 1 */ 507 #define BASE_REG 0x0002 508 509 510 /* Individual Address Registers */ 511 /* BANK 1 */ 512 #define ADDR0_REG 0x0004 513 #define ADDR1_REG 0x0006 514 #define ADDR2_REG 0x0008 515 516 517 /* General Purpose Register */ 518 /* BANK 1 */ 519 #define GP_REG 0x000A 520 521 522 /* Control Register */ 523 /* BANK 1 */ 524 #define CTL_REG 0x000C 525 #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ 526 #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ 527 #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ 528 #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ 529 #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ 530 #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ 531 #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ 532 #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ 533 #define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ 534 535 /* MMU Command Register */ 536 /* BANK 2 */ 537 #define MMU_CMD_REG 0x0000 538 #define MC_BUSY 1 /* When 1 the last release has not completed */ 539 #define MC_NOP (0<<5) /* No Op */ 540 #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ 541 #define MC_RESET (2<<5) /* Reset MMU to initial state */ 542 #define MC_REMOVE (3<<5) /* Remove the current rx packet */ 543 #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ 544 #define MC_FREEPKT (5<<5) /* Release packet in PNR register */ 545 #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ 546 #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ 547 548 549 /* Packet Number Register */ 550 /* BANK 2 */ 551 #define PN_REG 0x0002 552 553 554 /* Allocation Result Register */ 555 /* BANK 2 */ 556 #define AR_REG 0x0003 557 #define AR_FAILED 0x80 /* Alocation Failed */ 558 559 560 /* RX FIFO Ports Register */ 561 /* BANK 2 */ 562 #define RXFIFO_REG 0x0004 /* Must be read as a word */ 563 #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ 564 565 566 /* TX FIFO Ports Register */ 567 /* BANK 2 */ 568 #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ 569 #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ 570 571 572 /* Pointer Register */ 573 /* BANK 2 */ 574 #define PTR_REG 0x0006 575 #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ 576 #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ 577 #define PTR_READ 0x2000 /* When 1 the operation is a read */ 578 #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ 579 580 581 /* Data Register */ 582 /* BANK 2 */ 583 #define SMC91111_DATA_REG 0x0008 584 585 586 /* Interrupt Status/Acknowledge Register */ 587 /* BANK 2 */ 588 #define SMC91111_INT_REG 0x000C 589 590 591 /* Interrupt Mask Register */ 592 /* BANK 2 */ 593 #define IM_REG 0x000D 594 #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ 595 #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ 596 #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ 597 #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ 598 #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ 599 #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ 600 #define IM_TX_INT 0x02 /* Transmit Interrrupt */ 601 #define IM_RCV_INT 0x01 /* Receive Interrupt */ 602 603 604 /* Multicast Table Registers */ 605 /* BANK 3 */ 606 #define MCAST_REG1 0x0000 607 #define MCAST_REG2 0x0002 608 #define MCAST_REG3 0x0004 609 #define MCAST_REG4 0x0006 610 611 612 /* Management Interface Register (MII) */ 613 /* BANK 3 */ 614 #define MII_REG 0x0008 615 #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ 616 #define MII_MDOE 0x0008 /* MII Output Enable */ 617 #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ 618 #define MII_MDI 0x0002 /* MII Input, pin MDI */ 619 #define MII_MDO 0x0001 /* MII Output, pin MDO */ 620 621 622 /* Revision Register */ 623 /* BANK 3 */ 624 #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ 625 626 627 /* Early RCV Register */ 628 /* BANK 3 */ 629 /* this is NOT on SMC9192 */ 630 #define ERCV_REG 0x000C 631 #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ 632 #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ 633 634 /* External Register */ 635 /* BANK 7 */ 636 #define EXT_REG 0x0000 637 638 639 #define CHIP_9192 3 640 #define CHIP_9194 4 641 #define CHIP_9195 5 642 #define CHIP_9196 6 643 #define CHIP_91100 7 644 #define CHIP_91100FD 8 645 #define CHIP_91111FD 9 646 647 #if 0 648 static const char * chip_ids[ 15 ] = { 649 NULL, NULL, NULL, 650 /* 3 */ "SMC91C90/91C92", 651 /* 4 */ "SMC91C94", 652 /* 5 */ "SMC91C95", 653 /* 6 */ "SMC91C96", 654 /* 7 */ "SMC91C100", 655 /* 8 */ "SMC91C100FD", 656 /* 9 */ "SMC91C111", 657 NULL, NULL, 658 NULL, NULL, NULL}; 659 #endif 660 661 /* 662 . Transmit status bits 663 */ 664 #define TS_SUCCESS 0x0001 665 #define TS_LOSTCAR 0x0400 666 #define TS_LATCOL 0x0200 667 #define TS_16COL 0x0010 668 669 /* 670 . Receive status bits 671 */ 672 #define RS_ALGNERR 0x8000 673 #define RS_BRODCAST 0x4000 674 #define RS_BADCRC 0x2000 675 #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ 676 #define RS_TOOLONG 0x0800 677 #define RS_TOOSHORT 0x0400 678 #define RS_MULTICAST 0x0001 679 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 680 681 682 /* PHY Types */ 683 enum { 684 PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ 685 PHY_LAN83C180 686 }; 687 688 689 /* PHY Register Addresses (LAN91C111 Internal PHY) */ 690 691 /* PHY Control Register */ 692 #define PHY_CNTL_REG 0x00 693 #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ 694 #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ 695 #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ 696 #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ 697 #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ 698 #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ 699 #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ 700 #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ 701 #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ 702 703 /* PHY Status Register */ 704 #define PHY_STAT_REG 0x01 705 #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ 706 #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ 707 #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ 708 #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ 709 #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ 710 #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ 711 #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ 712 #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ 713 #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ 714 #define PHY_STAT_LINK 0x0004 /* 1=valid link */ 715 #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ 716 #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ 717 718 /* PHY Identifier Registers */ 719 #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ 720 #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ 721 722 /* PHY Auto-Negotiation Advertisement Register */ 723 #define PHY_AD_REG 0x04 724 #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ 725 #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ 726 #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ 727 #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ 728 #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ 729 #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ 730 #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ 731 #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ 732 #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ 733 734 /* PHY Auto-negotiation Remote End Capability Register */ 735 #define PHY_RMT_REG 0x05 736 /* Uses same bit definitions as PHY_AD_REG */ 737 738 /* PHY Configuration Register 1 */ 739 #define PHY_CFG1_REG 0x10 740 #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ 741 #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ 742 #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ 743 #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ 744 #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ 745 #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ 746 #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ 747 #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ 748 #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ 749 #define PHY_CFG1_TLVL_MASK 0x003C 750 #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ 751 752 753 /* PHY Configuration Register 2 */ 754 #define PHY_CFG2_REG 0x11 755 #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ 756 #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ 757 #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ 758 #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ 759 760 /* PHY Status Output (and Interrupt status) Register */ 761 #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ 762 #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ 763 #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ 764 #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ 765 #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ 766 #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ 767 #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ 768 #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ 769 #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ 770 #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ 771 #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ 772 773 /* PHY Interrupt/Status Mask Register */ 774 #define PHY_MASK_REG 0x13 /* Interrupt Mask */ 775 /* Uses the same bit definitions as PHY_INT_REG */ 776 777 778 /*------------------------------------------------------------------------- 779 . I define some macros to make it easier to do somewhat common 780 . or slightly complicated, repeated tasks. 781 --------------------------------------------------------------------------*/ 782 783 /* select a register bank, 0 to 3 */ 784 785 #define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); } 786 787 /* this enables an interrupt in the interrupt mask register */ 788 #define SMC_ENABLE_INT(a,x) {\ 789 unsigned char mask;\ 790 SMC_SELECT_BANK((a),2);\ 791 mask = SMC_inb((a), IM_REG );\ 792 mask |= (x);\ 793 SMC_outb( (a), mask, IM_REG ); \ 794 } 795 796 /* this disables an interrupt from the interrupt mask register */ 797 798 #define SMC_DISABLE_INT(a,x) {\ 799 unsigned char mask;\ 800 SMC_SELECT_BANK(2);\ 801 mask = SMC_inb( (a), IM_REG );\ 802 mask &= ~(x);\ 803 SMC_outb( (a), mask, IM_REG ); \ 804 } 805 806 /*---------------------------------------------------------------------- 807 . Define the interrupts that I want to receive from the card 808 . 809 . I want: 810 . IM_EPH_INT, for nasty errors 811 . IM_RCV_INT, for happy received packets 812 . IM_RX_OVRN_INT, because I have to kick the receiver 813 . IM_MDINT, for PHY Register 18 Status Changes 814 --------------------------------------------------------------------------*/ 815 #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ 816 IM_MDINT) 817 818 #endif /* _SMC_91111_H_ */ 819