1*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /*------------------------------------------------------------------------ 2*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . smc91111.h - macros for the LAN91C111 Ethernet Driver 3*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 4*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . (C) Copyright 2002 5*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Sysgo Real-Time Solutions, GmbH <www.elinos.com> 6*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Rolf Offermanns <rof@sysgo.de> 7*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 8*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Developed by Simple Network Magic Corporation (SNMC) 9*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Copyright (C) 1996 by Erik Stahlman (ES) 10*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 11*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . This program is free software; you can redistribute it and/or modify 12*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . it under the terms of the GNU General Public License as published by 13*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . the Free Software Foundation; either version 2 of the License, or 14*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . (at your option) any later version. 15*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 16*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . This program is distributed in the hope that it will be useful, 17*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . but WITHOUT ANY WARRANTY; without even the implied warranty of 18*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . GNU General Public License for more details. 20*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 21*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . You should have received a copy of the GNU General Public License 22*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . along with this program; if not, write to the Free Software 23*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 25*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . This file contains register information and access macros for 26*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . the LAN91C111 single chip ethernet controller. It is a modified 27*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . version of the smc9194.h file. 28*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 29*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Information contained in this file was obtained from the LAN91C111 30*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . manual from SMC. To get a copy, if you really want one, you can find 31*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . information under www.smsc.com. 32*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 33*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Authors 34*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Erik Stahlman ( erik@vt.edu ) 35*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Daris A Nevil ( dnevil@snmc.com ) 36*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 37*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . History 38*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device 39*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 40*2439e4bfSJean-Christophe PLAGNIOL-VILLARD ---------------------------------------------------------------------------*/ 41*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifndef _SMC91111_H_ 42*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define _SMC91111_H_ 43*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 44*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <asm/types.h> 45*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <config.h> 46*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 47*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 48*2439e4bfSJean-Christophe PLAGNIOL-VILLARD * This function may be called by the board specific initialisation code 49*2439e4bfSJean-Christophe PLAGNIOL-VILLARD * in order to override the default mac address. 50*2439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 51*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 52*2439e4bfSJean-Christophe PLAGNIOL-VILLARD void smc_set_mac_addr (const unsigned char *addr); 53*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 54*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 55*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* I want some simple types */ 56*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 57*2439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef unsigned char byte; 58*2439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef unsigned short word; 59*2439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef unsigned long int dword; 60*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 61*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 62*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . DEBUGGING LEVELS 63*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 64*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 0 for normal operation 65*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 1 for slightly more details 66*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . >2 for various levels of increasingly useless information 67*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 2 for interrupt tracking, status flags 68*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 3 for packet info 69*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 4 for complete packet dumps 70*2439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 71*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /*#define SMC_DEBUG 0 */ 72*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 73*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 74*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 75*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_IO_EXTENT 16 76*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 77*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_PXA250 78*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 79*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_XSENGINE 80*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) 81*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1)))) 82*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inb(p) ({ \ 83*2439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \ 84*2439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ 85*2439e4bfSJean-Christophe PLAGNIOL-VILLARD if (__p & 2) __v >>= 8; \ 86*2439e4bfSJean-Christophe PLAGNIOL-VILLARD else __v &= 0xff; \ 87*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __v; }) 88*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_XAENIAX) 89*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) 90*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inw(z) ({ \ 91*2439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \ 92*2439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ 93*2439e4bfSJean-Christophe PLAGNIOL-VILLARD if (__p & 3) __v >>= 16; \ 94*2439e4bfSJean-Christophe PLAGNIOL-VILLARD else __v &= 0xffff; \ 95*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __v; }) 96*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inb(p) ({ \ 97*2439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int ___v = SMC_inw((p) & ~1); \ 98*2439e4bfSJean-Christophe PLAGNIOL-VILLARD if (p & 1) ___v >>= 8; \ 99*2439e4bfSJean-Christophe PLAGNIOL-VILLARD else ___v &= 0xff; \ 100*2439e4bfSJean-Christophe PLAGNIOL-VILLARD ___v; }) 101*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 102*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) 103*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) 104*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inb(p) ({ \ 105*2439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \ 106*2439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ 107*2439e4bfSJean-Christophe PLAGNIOL-VILLARD if (__p & 1) __v >>= 8; \ 108*2439e4bfSJean-Christophe PLAGNIOL-VILLARD else __v &= 0xff; \ 109*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __v; }) 110*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 111*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 112*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_XSENGINE 113*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) 114*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d) 115*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #elif defined (CONFIG_XAENIAX) 116*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) 117*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outw(d,p) ({ \ 118*2439e4bfSJean-Christophe PLAGNIOL-VILLARD dword __dwo = SMC_inl((p) & ~3); \ 119*2439e4bfSJean-Christophe PLAGNIOL-VILLARD dword __dwn = (word)(d); \ 120*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ 121*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ 122*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_outl(__dwo, (p) & ~3); \ 123*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 124*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 125*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) 126*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) 127*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 128*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 129*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outb(d,r) ({ word __d = (byte)(d); \ 130*2439e4bfSJean-Christophe PLAGNIOL-VILLARD word __w = SMC_inw((r)&~1); \ 131*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 132*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __w |= ((r)&1) ? __d<<8 : __d; \ 133*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_outw(__w,(r)&~1); \ 134*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 135*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 136*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outsl(r,b,l) ({ int __i; \ 137*2439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 138*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 139*2439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 140*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_outl( *(__b2 + __i), r); \ 141*2439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 142*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 143*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 144*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outsw(r,b,l) ({ int __i; \ 145*2439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 146*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 147*2439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 148*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_outw( *(__b2 + __i), r); \ 149*2439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 150*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 151*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 152*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_insl(r,b,l) ({ int __i ; \ 153*2439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 154*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 155*2439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 156*2439e4bfSJean-Christophe PLAGNIOL-VILLARD *(__b2 + __i) = SMC_inl(r); \ 157*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_inl(0); \ 158*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 159*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 160*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 161*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_insw(r,b,l) ({ int __i ; \ 162*2439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 163*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 164*2439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 165*2439e4bfSJean-Christophe PLAGNIOL-VILLARD *(__b2 + __i) = SMC_inw(r); \ 166*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_inw(0); \ 167*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 168*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 169*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 170*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_insb(r,b,l) ({ int __i ; \ 171*2439e4bfSJean-Christophe PLAGNIOL-VILLARD byte *__b2; \ 172*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (byte *) b; \ 173*2439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 174*2439e4bfSJean-Christophe PLAGNIOL-VILLARD *(__b2 + __i) = SMC_inb(r); \ 175*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_inb(0); \ 176*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 177*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 178*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 179*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else /* if not CONFIG_PXA250 */ 180*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 181*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ 182*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 183*2439e4bfSJean-Christophe PLAGNIOL-VILLARD * We have only 16 Bit PCMCIA access on Socket 0 184*2439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 185*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 186*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_ADNPESC1 187*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) 188*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #elif CONFIG_BLACKFIN 189*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;}) 190*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 191*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) 192*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 193*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) 194*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 195*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_ADNPESC1 196*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) 197*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #elif CONFIG_BLACKFIN 198*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");} 199*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 200*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) 201*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 202*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outb(d,r) ({ word __d = (byte)(d); \ 203*2439e4bfSJean-Christophe PLAGNIOL-VILLARD word __w = SMC_inw((r)&~1); \ 204*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 205*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __w |= ((r)&1) ? __d<<8 : __d; \ 206*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_outw(__w,(r)&~1); \ 207*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 208*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 209*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) 210*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 211*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outsw(r,b,l) ({ int __i; \ 212*2439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 213*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 214*2439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 215*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_outw( *(__b2 + __i), r); \ 216*2439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 217*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 218*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 219*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 220*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 221*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) 222*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 223*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_insw(r,b,l) ({ int __i ; \ 224*2439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 225*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 226*2439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 227*2439e4bfSJean-Christophe PLAGNIOL-VILLARD *(__b2 + __i) = SMC_inw(r); \ 228*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_inw(0); \ 229*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 230*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 231*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 232*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 233*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif /* CONFIG_SMC_USE_IOFUNCS */ 234*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 235*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SMC_USE_32_BIT) 236*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 237*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_XSENGINE 238*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) 239*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 240*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) 241*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 242*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 243*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_insl(r,b,l) ({ int __i ; \ 244*2439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 245*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 246*2439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 247*2439e4bfSJean-Christophe PLAGNIOL-VILLARD *(__b2 + __i) = SMC_inl(r); \ 248*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_inl(0); \ 249*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 250*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 251*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 252*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_XSENGINE 253*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) 254*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 255*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) 256*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 257*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_outsl(r,b,l) ({ int __i; \ 258*2439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 259*2439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 260*2439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 261*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_outl( *(__b2 + __i), r); \ 262*2439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 263*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 264*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 265*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif /* CONFIG_SMC_USE_32_BIT */ 266*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 267*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 268*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 269*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /*--------------------------------------------------------------- 270*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 271*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . A description of the SMSC registers is probably in order here, 272*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . although for details, the SMC datasheet is invaluable. 273*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 274*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Basically, the chip has 4 banks of registers ( 0 to 3 ), which 275*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . are accessed by writing a number into the BANK_SELECT register 276*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . ( I also use a SMC_SELECT_BANK macro for this ). 277*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 278*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . The banks are configured so that for most purposes, bank 2 is all 279*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . that is needed for simple run time tasks. 280*2439e4bfSJean-Christophe PLAGNIOL-VILLARD -----------------------------------------------------------------------*/ 281*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 282*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 283*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Bank Select Register: 284*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 285*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . yyyy yyyy 0000 00xx 286*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . xx = bank number 287*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . yyyy yyyy = 0x33, for identification purposes. 288*2439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 289*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BANK_SELECT 14 290*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 291*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Transmit Control Register */ 292*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 293*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_REG 0x0000 /* transmit control register */ 294*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_ENABLE 0x0001 /* When 1 we can transmit */ 295*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_LOOP 0x0002 /* Controls output pin LBK */ 296*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_FORCOL 0x0004 /* When 1 will force a collision */ 297*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ 298*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ 299*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ 300*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ 301*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ 302*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ 303*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ 304*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 305*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_CLEAR 0 /* do NOTHING */ 306*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* the default settings for the TCR register : */ 307*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* QUESTION: do I want to enable padding of short packets ? */ 308*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_DEFAULT TCR_ENABLE 309*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 310*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 311*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* EPH Status Register */ 312*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 313*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EPH_STATUS_REG 0x0002 314*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_TX_SUC 0x0001 /* Last TX was successful */ 315*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ 316*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ 317*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ 318*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_16COL 0x0010 /* 16 Collisions Reached */ 319*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_SQET 0x0020 /* Signal Quality Error Test */ 320*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ 321*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_TXDEFR 0x0080 /* Transmit Deferred */ 322*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LATCOL 0x0200 /* Late collision detected on last tx */ 323*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ 324*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_EXC_DEF 0x0800 /* Excessive Deferral */ 325*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ 326*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ 327*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_TXUNRN 0x8000 /* Tx Underrun */ 328*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 329*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 330*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Control Register */ 331*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 332*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_REG 0x0004 333*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ 334*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_PRMS 0x0002 /* Enable promiscuous mode */ 335*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ 336*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ 337*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ 338*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ 339*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ 340*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_SOFTRST 0x8000 /* resets the chip */ 341*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 342*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* the normal settings for the RCR register : */ 343*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 344*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_CLEAR 0x0 /* set it to a base state */ 345*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 346*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Counter Register */ 347*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 348*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define COUNTER_REG 0x0006 349*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 350*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Memory Information Register */ 351*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 352*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MIR_REG 0x0008 353*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 354*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive/Phy Control Register */ 355*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 356*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_REG 0x000A 357*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ 358*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ 359*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ 360*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ 361*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ 362*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ 363*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_RES (0x01) /* LED = Reserved */ 364*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ 365*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ 366*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ 367*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ 368*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_TX (0x06) /* LED = TX packet occurred */ 369*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_RX (0x07) /* LED = RX packet occurred */ 370*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) 371*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* buggy schematic: LEDa -> yellow, LEDb --> green */ 372*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 373*2439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 374*2439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 375*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_ADNPESC1) 376*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ 377*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 378*2439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 379*2439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 380*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 381*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* SMSC reference design: LEDa --> green, LEDb --> yellow */ 382*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 383*2439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ 384*2439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) 385*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 386*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 387*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Bank 0 0x000C is reserved */ 388*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 389*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Bank Select Register */ 390*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* All Banks */ 391*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BSR_REG 0x000E 392*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 393*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 394*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Configuration Reg */ 395*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 396*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_REG 0x0000 397*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ 398*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ 399*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ 400*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ 401*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 402*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ 403*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 404*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 405*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 406*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Base Address Register */ 407*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 408*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BASE_REG 0x0002 409*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 410*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 411*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Individual Address Registers */ 412*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 413*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADDR0_REG 0x0004 414*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADDR1_REG 0x0006 415*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADDR2_REG 0x0008 416*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 417*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 418*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* General Purpose Register */ 419*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 420*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define GP_REG 0x000A 421*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 422*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 423*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Control Register */ 424*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 425*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_REG 0x000C 426*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ 427*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ 428*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ 429*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ 430*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ 431*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ 432*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ 433*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ 434*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ 435*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 436*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* MMU Command Register */ 437*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 438*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MMU_CMD_REG 0x0000 439*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_BUSY 1 /* When 1 the last release has not completed */ 440*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_NOP (0<<5) /* No Op */ 441*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ 442*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_RESET (2<<5) /* Reset MMU to initial state */ 443*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_REMOVE (3<<5) /* Remove the current rx packet */ 444*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ 445*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_FREEPKT (5<<5) /* Release packet in PNR register */ 446*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ 447*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ 448*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 449*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 450*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Packet Number Register */ 451*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 452*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PN_REG 0x0002 453*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 454*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 455*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Allocation Result Register */ 456*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 457*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define AR_REG 0x0003 458*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define AR_FAILED 0x80 /* Alocation Failed */ 459*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 460*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 461*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* RX FIFO Ports Register */ 462*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 463*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RXFIFO_REG 0x0004 /* Must be read as a word */ 464*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ 465*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 466*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 467*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* TX FIFO Ports Register */ 468*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 469*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ 470*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ 471*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 472*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 473*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Pointer Register */ 474*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 475*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_REG 0x0006 476*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ 477*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ 478*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_READ 0x2000 /* When 1 the operation is a read */ 479*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ 480*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 481*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 482*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Data Register */ 483*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 484*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC91111_DATA_REG 0x0008 485*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 486*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 487*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Interrupt Status/Acknowledge Register */ 488*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 489*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC91111_INT_REG 0x000C 490*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 491*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 492*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Interrupt Mask Register */ 493*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 494*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_REG 0x000D 495*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ 496*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ 497*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ 498*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ 499*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ 500*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ 501*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_TX_INT 0x02 /* Transmit Interrrupt */ 502*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_RCV_INT 0x01 /* Receive Interrupt */ 503*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 504*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 505*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Multicast Table Registers */ 506*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 3 */ 507*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MCAST_REG1 0x0000 508*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MCAST_REG2 0x0002 509*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MCAST_REG3 0x0004 510*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MCAST_REG4 0x0006 511*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 512*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 513*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Management Interface Register (MII) */ 514*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 3 */ 515*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_REG 0x0008 516*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ 517*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MDOE 0x0008 /* MII Output Enable */ 518*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ 519*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MDI 0x0002 /* MII Input, pin MDI */ 520*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MDO 0x0001 /* MII Output, pin MDO */ 521*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 522*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 523*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Revision Register */ 524*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 3 */ 525*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ 526*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 527*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 528*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Early RCV Register */ 529*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 3 */ 530*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* this is NOT on SMC9192 */ 531*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ERCV_REG 0x000C 532*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ 533*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ 534*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 535*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* External Register */ 536*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 7 */ 537*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EXT_REG 0x0000 538*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 539*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 540*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_9192 3 541*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_9194 4 542*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_9195 5 543*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_9196 6 544*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_91100 7 545*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_91100FD 8 546*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_91111FD 9 547*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 548*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 549*2439e4bfSJean-Christophe PLAGNIOL-VILLARD static const char * chip_ids[ 15 ] = { 550*2439e4bfSJean-Christophe PLAGNIOL-VILLARD NULL, NULL, NULL, 551*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3 */ "SMC91C90/91C92", 552*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4 */ "SMC91C94", 553*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5 */ "SMC91C95", 554*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 6 */ "SMC91C96", 555*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 7 */ "SMC91C100", 556*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 8 */ "SMC91C100FD", 557*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 9 */ "SMC91C111", 558*2439e4bfSJean-Christophe PLAGNIOL-VILLARD NULL, NULL, 559*2439e4bfSJean-Christophe PLAGNIOL-VILLARD NULL, NULL, NULL}; 560*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 561*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 562*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 563*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Transmit status bits 564*2439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 565*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TS_SUCCESS 0x0001 566*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TS_LOSTCAR 0x0400 567*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TS_LATCOL 0x0200 568*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TS_16COL 0x0010 569*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 570*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 571*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Receive status bits 572*2439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 573*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_ALGNERR 0x8000 574*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_BRODCAST 0x4000 575*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_BADCRC 0x2000 576*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ 577*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_TOOLONG 0x0800 578*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_TOOSHORT 0x0400 579*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_MULTICAST 0x0001 580*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 581*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 582*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 583*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Types */ 584*2439e4bfSJean-Christophe PLAGNIOL-VILLARD enum { 585*2439e4bfSJean-Christophe PLAGNIOL-VILLARD PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ 586*2439e4bfSJean-Christophe PLAGNIOL-VILLARD PHY_LAN83C180 587*2439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 588*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 589*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 590*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Register Addresses (LAN91C111 Internal PHY) */ 591*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 592*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Control Register */ 593*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_REG 0x00 594*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ 595*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ 596*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ 597*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ 598*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ 599*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ 600*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ 601*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ 602*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ 603*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 604*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Status Register */ 605*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_REG 0x01 606*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ 607*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ 608*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ 609*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ 610*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ 611*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ 612*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ 613*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ 614*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ 615*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_LINK 0x0004 /* 1=valid link */ 616*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ 617*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ 618*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 619*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Identifier Registers */ 620*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ 621*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ 622*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 623*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Auto-Negotiation Advertisement Register */ 624*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_REG 0x04 625*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ 626*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ 627*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ 628*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ 629*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ 630*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ 631*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ 632*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ 633*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ 634*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 635*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Auto-negotiation Remote End Capability Register */ 636*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_RMT_REG 0x05 637*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Uses same bit definitions as PHY_AD_REG */ 638*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 639*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Configuration Register 1 */ 640*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_REG 0x10 641*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ 642*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ 643*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ 644*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ 645*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ 646*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ 647*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ 648*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ 649*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ 650*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_TLVL_MASK 0x003C 651*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ 652*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 653*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 654*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Configuration Register 2 */ 655*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_REG 0x11 656*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ 657*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ 658*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ 659*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ 660*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 661*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Status Output (and Interrupt status) Register */ 662*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ 663*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ 664*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ 665*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ 666*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ 667*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ 668*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ 669*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ 670*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ 671*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ 672*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ 673*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 674*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Interrupt/Status Mask Register */ 675*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_MASK_REG 0x13 /* Interrupt Mask */ 676*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Uses the same bit definitions as PHY_INT_REG */ 677*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 678*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 679*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /*------------------------------------------------------------------------- 680*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . I define some macros to make it easier to do somewhat common 681*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . or slightly complicated, repeated tasks. 682*2439e4bfSJean-Christophe PLAGNIOL-VILLARD --------------------------------------------------------------------------*/ 683*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 684*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* select a register bank, 0 to 3 */ 685*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 686*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); } 687*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 688*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* this enables an interrupt in the interrupt mask register */ 689*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_ENABLE_INT(x) {\ 690*2439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char mask;\ 691*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_SELECT_BANK(2);\ 692*2439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = SMC_inb( IM_REG );\ 693*2439e4bfSJean-Christophe PLAGNIOL-VILLARD mask |= (x);\ 694*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_outb( mask, IM_REG ); \ 695*2439e4bfSJean-Christophe PLAGNIOL-VILLARD } 696*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 697*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /* this disables an interrupt from the interrupt mask register */ 698*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 699*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_DISABLE_INT(x) {\ 700*2439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char mask;\ 701*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_SELECT_BANK(2);\ 702*2439e4bfSJean-Christophe PLAGNIOL-VILLARD mask = SMC_inb( IM_REG );\ 703*2439e4bfSJean-Christophe PLAGNIOL-VILLARD mask &= ~(x);\ 704*2439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_outb( mask, IM_REG ); \ 705*2439e4bfSJean-Christophe PLAGNIOL-VILLARD } 706*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 707*2439e4bfSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------- 708*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . Define the interrupts that I want to receive from the card 709*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . 710*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . I want: 711*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . IM_EPH_INT, for nasty errors 712*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . IM_RCV_INT, for happy received packets 713*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . IM_RX_OVRN_INT, because I have to kick the receiver 714*2439e4bfSJean-Christophe PLAGNIOL-VILLARD . IM_MDINT, for PHY Register 18 Status Changes 715*2439e4bfSJean-Christophe PLAGNIOL-VILLARD --------------------------------------------------------------------------*/ 716*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ 717*2439e4bfSJean-Christophe PLAGNIOL-VILLARD IM_MDINT) 718*2439e4bfSJean-Christophe PLAGNIOL-VILLARD 719*2439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif /* _SMC_91111_H_ */ 720