1 /*------------------------------------------------------------------------ 2 . smc91111.c 3 . This is a driver for SMSC's 91C111 single-chip Ethernet device. 4 . 5 . (C) Copyright 2002 6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 . Rolf Offermanns <rof@sysgo.de> 8 . 9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 10 . Developed by Simple Network Magic Corporation (SNMC) 11 . Copyright (C) 1996 by Erik Stahlman (ES) 12 . 13 * SPDX-License-Identifier: GPL-2.0+ 14 . 15 . Information contained in this file was obtained from the LAN91C111 16 . manual from SMC. To get a copy, if you really want one, you can find 17 . information under www.smsc.com. 18 . 19 . 20 . "Features" of the SMC chip: 21 . Integrated PHY/MAC for 10/100BaseT Operation 22 . Supports internal and external MII 23 . Integrated 8K packet memory 24 . EEPROM interface for configuration 25 . 26 . Arguments: 27 . io = for the base address 28 . irq = for the IRQ 29 . 30 . author: 31 . Erik Stahlman ( erik@vt.edu ) 32 . Daris A Nevil ( dnevil@snmc.com ) 33 . 34 . 35 . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) 36 . 37 . Sources: 38 . o SMSC LAN91C111 databook (www.smsc.com) 39 . o smc9194.c by Erik Stahlman 40 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) 41 . 42 . History: 43 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. 44 . 10/17/01 Marco Hasewinkel Modify for DNP/1110 45 . 07/25/01 Woojung Huh Modify for ADS Bitsy 46 . 04/25/01 Daris A Nevil Initial public release through SMSC 47 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 48 ----------------------------------------------------------------------------*/ 49 50 #include <common.h> 51 #include <command.h> 52 #include <config.h> 53 #include <malloc.h> 54 #include "smc91111.h" 55 #include <net.h> 56 57 /* Use power-down feature of the chip */ 58 #define POWER_DOWN 0 59 60 #define NO_AUTOPROBE 61 62 #define SMC_DEBUG 0 63 64 #if SMC_DEBUG > 1 65 static const char version[] = 66 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; 67 #endif 68 69 /* Autonegotiation timeout in seconds */ 70 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT 71 #define CONFIG_SMC_AUTONEG_TIMEOUT 10 72 #endif 73 74 /*------------------------------------------------------------------------ 75 . 76 . Configuration options, for the experienced user to change. 77 . 78 -------------------------------------------------------------------------*/ 79 80 /* 81 . Wait time for memory to be free. This probably shouldn't be 82 . tuned that much, as waiting for this means nothing else happens 83 . in the system 84 */ 85 #define MEMORY_WAIT_TIME 16 86 87 88 #if (SMC_DEBUG > 2 ) 89 #define PRINTK3(args...) printf(args) 90 #else 91 #define PRINTK3(args...) 92 #endif 93 94 #if SMC_DEBUG > 1 95 #define PRINTK2(args...) printf(args) 96 #else 97 #define PRINTK2(args...) 98 #endif 99 100 #ifdef SMC_DEBUG 101 #define PRINTK(args...) printf(args) 102 #else 103 #define PRINTK(args...) 104 #endif 105 106 107 /*------------------------------------------------------------------------ 108 . 109 . The internal workings of the driver. If you are changing anything 110 . here with the SMC stuff, you should have the datasheet and know 111 . what you are doing. 112 . 113 -------------------------------------------------------------------------*/ 114 115 /* Memory sizing constant */ 116 #define LAN91C111_MEMORY_MULTIPLIER (1024*2) 117 118 #ifndef CONFIG_SMC91111_BASE 119 #error "SMC91111 Base address must be passed to initialization funciton" 120 /* #define CONFIG_SMC91111_BASE 0x20000300 */ 121 #endif 122 123 #define SMC_DEV_NAME "SMC91111" 124 #define SMC_PHY_ADDR 0x0000 125 #define SMC_ALLOC_MAX_TRY 5 126 #define SMC_TX_TIMEOUT 30 127 128 #define SMC_PHY_CLOCK_DELAY 1000 129 130 #define ETH_ZLEN 60 131 132 #ifdef CONFIG_SMC_USE_32_BIT 133 #define USE_32_BIT 1 134 #else 135 #undef USE_32_BIT 136 #endif 137 138 #ifdef SHARED_RESOURCES 139 extern void swap_to(int device_id); 140 #else 141 # define swap_to(x) 142 #endif 143 144 #ifndef CONFIG_SMC91111_EXT_PHY 145 static void smc_phy_configure(struct eth_device *dev); 146 #endif /* !CONFIG_SMC91111_EXT_PHY */ 147 148 /* 149 ------------------------------------------------------------ 150 . 151 . Internal routines 152 . 153 ------------------------------------------------------------ 154 */ 155 156 #ifdef CONFIG_SMC_USE_IOFUNCS 157 /* 158 * input and output functions 159 * 160 * Implemented due to inx,outx macros accessing the device improperly 161 * and putting the device into an unkown state. 162 * 163 * For instance, on Sharp LPD7A400 SDK, affects were chip memory 164 * could not be free'd (hence the alloc failures), duplicate packets, 165 * packets being corrupt (shifted) on the wire, etc. Switching to the 166 * inx,outx functions fixed this problem. 167 */ 168 169 static inline word SMC_inw(struct eth_device *dev, dword offset) 170 { 171 word v; 172 v = *((volatile word*)(dev->iobase + offset)); 173 barrier(); *(volatile u32*)(0xc0000000); 174 return v; 175 } 176 177 static inline void SMC_outw(struct eth_device *dev, word value, dword offset) 178 { 179 *((volatile word*)(dev->iobase + offset)) = value; 180 barrier(); *(volatile u32*)(0xc0000000); 181 } 182 183 static inline byte SMC_inb(struct eth_device *dev, dword offset) 184 { 185 word _w; 186 187 _w = SMC_inw(dev, offset & ~((dword)1)); 188 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); 189 } 190 191 static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) 192 { 193 word _w; 194 195 _w = SMC_inw(dev, offset & ~((dword)1)); 196 if (offset & 1) 197 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = 198 (value<<8) | (_w & 0x00ff); 199 else 200 *((volatile word*)(dev->iobase + offset)) = 201 value | (_w & 0xff00); 202 } 203 204 static inline void SMC_insw(struct eth_device *dev, dword offset, 205 volatile uchar* buf, dword len) 206 { 207 volatile word *p = (volatile word *)buf; 208 209 while (len-- > 0) { 210 *p++ = SMC_inw(dev, offset); 211 barrier(); 212 *((volatile u32*)(0xc0000000)); 213 } 214 } 215 216 static inline void SMC_outsw(struct eth_device *dev, dword offset, 217 uchar* buf, dword len) 218 { 219 volatile word *p = (volatile word *)buf; 220 221 while (len-- > 0) { 222 SMC_outw(dev, *p++, offset); 223 barrier(); 224 *(volatile u32*)(0xc0000000); 225 } 226 } 227 #endif /* CONFIG_SMC_USE_IOFUNCS */ 228 229 /* 230 . A rather simple routine to print out a packet for debugging purposes. 231 */ 232 #if SMC_DEBUG > 2 233 static void print_packet( byte *, int ); 234 #endif 235 236 #define tx_done(dev) 1 237 238 static int poll4int (struct eth_device *dev, byte mask, int timeout) 239 { 240 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; 241 int is_timeout = 0; 242 word old_bank = SMC_inw (dev, BSR_REG); 243 244 PRINTK2 ("Polling...\n"); 245 SMC_SELECT_BANK (dev, 2); 246 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { 247 if (get_timer (0) >= tmo) { 248 is_timeout = 1; 249 break; 250 } 251 } 252 253 /* restore old bank selection */ 254 SMC_SELECT_BANK (dev, old_bank); 255 256 if (is_timeout) 257 return 1; 258 else 259 return 0; 260 } 261 262 /* Only one release command at a time, please */ 263 static inline void smc_wait_mmu_release_complete (struct eth_device *dev) 264 { 265 int count = 0; 266 267 /* assume bank 2 selected */ 268 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { 269 udelay (1); /* Wait until not busy */ 270 if (++count > 200) 271 break; 272 } 273 } 274 275 /* 276 . Function: smc_reset( void ) 277 . Purpose: 278 . This sets the SMC91111 chip to its normal state, hopefully from whatever 279 . mess that any other DOS driver has put it in. 280 . 281 . Maybe I should reset more registers to defaults in here? SOFTRST should 282 . do that for me. 283 . 284 . Method: 285 . 1. send a SOFT RESET 286 . 2. wait for it to finish 287 . 3. enable autorelease mode 288 . 4. reset the memory management unit 289 . 5. clear all interrupts 290 . 291 */ 292 static void smc_reset (struct eth_device *dev) 293 { 294 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); 295 296 /* This resets the registers mostly to defaults, but doesn't 297 affect EEPROM. That seems unnecessary */ 298 SMC_SELECT_BANK (dev, 0); 299 SMC_outw (dev, RCR_SOFTRST, RCR_REG); 300 301 /* Setup the Configuration Register */ 302 /* This is necessary because the CONFIG_REG is not affected */ 303 /* by a soft reset */ 304 305 SMC_SELECT_BANK (dev, 1); 306 #if defined(CONFIG_SMC91111_EXT_PHY) 307 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); 308 #else 309 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); 310 #endif 311 312 313 /* Release from possible power-down state */ 314 /* Configuration register is not affected by Soft Reset */ 315 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, 316 CONFIG_REG); 317 318 SMC_SELECT_BANK (dev, 0); 319 320 /* this should pause enough for the chip to be happy */ 321 udelay (10); 322 323 /* Disable transmit and receive functionality */ 324 SMC_outw (dev, RCR_CLEAR, RCR_REG); 325 SMC_outw (dev, TCR_CLEAR, TCR_REG); 326 327 /* set the control register */ 328 SMC_SELECT_BANK (dev, 1); 329 SMC_outw (dev, CTL_DEFAULT, CTL_REG); 330 331 /* Reset the MMU */ 332 SMC_SELECT_BANK (dev, 2); 333 smc_wait_mmu_release_complete (dev); 334 SMC_outw (dev, MC_RESET, MMU_CMD_REG); 335 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) 336 udelay (1); /* Wait until not busy */ 337 338 /* Note: It doesn't seem that waiting for the MMU busy is needed here, 339 but this is a place where future chipsets _COULD_ break. Be wary 340 of issuing another MMU command right after this */ 341 342 /* Disable all interrupts */ 343 SMC_outb (dev, 0, IM_REG); 344 } 345 346 /* 347 . Function: smc_enable 348 . Purpose: let the chip talk to the outside work 349 . Method: 350 . 1. Enable the transmitter 351 . 2. Enable the receiver 352 . 3. Enable interrupts 353 */ 354 static void smc_enable(struct eth_device *dev) 355 { 356 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); 357 SMC_SELECT_BANK( dev, 0 ); 358 /* see the header file for options in TCR/RCR DEFAULT*/ 359 SMC_outw( dev, TCR_DEFAULT, TCR_REG ); 360 SMC_outw( dev, RCR_DEFAULT, RCR_REG ); 361 362 /* clear MII_DIS */ 363 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ 364 } 365 366 /* 367 . Function: smc_halt 368 . Purpose: closes down the SMC91xxx chip. 369 . Method: 370 . 1. zero the interrupt mask 371 . 2. clear the enable receive flag 372 . 3. clear the enable xmit flags 373 . 374 . TODO: 375 . (1) maybe utilize power down mode. 376 . Why not yet? Because while the chip will go into power down mode, 377 . the manual says that it will wake up in response to any I/O requests 378 . in the register space. Empirical results do not show this working. 379 */ 380 static void smc_halt(struct eth_device *dev) 381 { 382 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); 383 384 /* no more interrupts for me */ 385 SMC_SELECT_BANK( dev, 2 ); 386 SMC_outb( dev, 0, IM_REG ); 387 388 /* and tell the card to stay away from that nasty outside world */ 389 SMC_SELECT_BANK( dev, 0 ); 390 SMC_outb( dev, RCR_CLEAR, RCR_REG ); 391 SMC_outb( dev, TCR_CLEAR, TCR_REG ); 392 393 swap_to(FLASH); 394 } 395 396 397 /* 398 . Function: smc_send(struct net_device * ) 399 . Purpose: 400 . This sends the actual packet to the SMC9xxx chip. 401 . 402 . Algorithm: 403 . First, see if a saved_skb is available. 404 . ( this should NOT be called if there is no 'saved_skb' 405 . Now, find the packet number that the chip allocated 406 . Point the data pointers at it in memory 407 . Set the length word in the chip's memory 408 . Dump the packet to chip memory 409 . Check if a last byte is needed ( odd length packet ) 410 . if so, set the control flag right 411 . Tell the card to send it 412 . Enable the transmit interrupt, so I know if it failed 413 . Free the kernel data if I actually sent it. 414 */ 415 static int smc_send(struct eth_device *dev, void *packet, int packet_length) 416 { 417 byte packet_no; 418 byte *buf; 419 int length; 420 int numPages; 421 int try = 0; 422 int time_out; 423 byte status; 424 byte saved_pnr; 425 word saved_ptr; 426 427 /* save PTR and PNR registers before manipulation */ 428 SMC_SELECT_BANK (dev, 2); 429 saved_pnr = SMC_inb( dev, PN_REG ); 430 saved_ptr = SMC_inw( dev, PTR_REG ); 431 432 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); 433 434 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; 435 436 /* allocate memory 437 ** The MMU wants the number of pages to be the number of 256 bytes 438 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) 439 ** 440 ** The 91C111 ignores the size bits, but the code is left intact 441 ** for backwards and future compatibility. 442 ** 443 ** Pkt size for allocating is data length +6 (for additional status 444 ** words, length and ctl!) 445 ** 446 ** If odd size then last byte is included in this header. 447 */ 448 numPages = ((length & 0xfffe) + 6); 449 numPages >>= 8; /* Divide by 256 */ 450 451 if (numPages > 7) { 452 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); 453 return 0; 454 } 455 456 /* now, try to allocate the memory */ 457 SMC_SELECT_BANK (dev, 2); 458 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); 459 460 /* FIXME: the ALLOC_INT bit never gets set * 461 * so the following will always give a * 462 * memory allocation error. * 463 * same code works in armboot though * 464 * -ro 465 */ 466 467 again: 468 try++; 469 time_out = MEMORY_WAIT_TIME; 470 do { 471 status = SMC_inb (dev, SMC91111_INT_REG); 472 if (status & IM_ALLOC_INT) { 473 /* acknowledge the interrupt */ 474 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); 475 break; 476 } 477 } while (--time_out); 478 479 if (!time_out) { 480 PRINTK2 ("%s: memory allocation, try %d failed ...\n", 481 SMC_DEV_NAME, try); 482 if (try < SMC_ALLOC_MAX_TRY) 483 goto again; 484 else 485 return 0; 486 } 487 488 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", 489 SMC_DEV_NAME, try); 490 491 buf = (byte *) packet; 492 493 /* If I get here, I _know_ there is a packet slot waiting for me */ 494 packet_no = SMC_inb (dev, AR_REG); 495 if (packet_no & AR_FAILED) { 496 /* or isn't there? BAD CHIP! */ 497 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); 498 return 0; 499 } 500 501 /* we have a packet address, so tell the card to use it */ 502 #ifndef CONFIG_XAENIAX 503 SMC_outb (dev, packet_no, PN_REG); 504 #else 505 /* On Xaeniax board, we can't use SMC_outb here because that way 506 * the Allocate MMU command will end up written to the command register 507 * as well, which will lead to a problem. 508 */ 509 SMC_outl (dev, packet_no << 16, 0); 510 #endif 511 /* do not write new ptr value if Write data fifo not empty */ 512 while ( saved_ptr & PTR_NOTEMPTY ) 513 printf ("Write data fifo not empty!\n"); 514 515 /* point to the beginning of the packet */ 516 SMC_outw (dev, PTR_AUTOINC, PTR_REG); 517 518 PRINTK3 ("%s: Trying to xmit packet of length %x\n", 519 SMC_DEV_NAME, length); 520 521 #if SMC_DEBUG > 2 522 printf ("Transmitting Packet\n"); 523 print_packet (buf, length); 524 #endif 525 526 /* send the packet length ( +6 for status, length and ctl byte ) 527 and the status word ( set to zeros ) */ 528 #ifdef USE_32_BIT 529 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); 530 #else 531 SMC_outw (dev, 0, SMC91111_DATA_REG); 532 /* send the packet length ( +6 for status words, length, and ctl */ 533 SMC_outw (dev, (length + 6), SMC91111_DATA_REG); 534 #endif 535 536 /* send the actual data 537 . I _think_ it's faster to send the longs first, and then 538 . mop up by sending the last word. It depends heavily 539 . on alignment, at least on the 486. Maybe it would be 540 . a good idea to check which is optimal? But that could take 541 . almost as much time as is saved? 542 */ 543 #ifdef USE_32_BIT 544 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); 545 #ifndef CONFIG_XAENIAX 546 if (length & 0x2) 547 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), 548 SMC91111_DATA_REG); 549 #else 550 /* On XANEIAX, we can only use 32-bit writes, so we need to handle 551 * unaligned tail part specially. The standard code doesn't work. 552 */ 553 if ((length & 3) == 3) { 554 u16 * ptr = (u16*) &buf[length-3]; 555 SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), 556 SMC91111_DATA_REG); 557 } else if ((length & 2) == 2) { 558 u16 * ptr = (u16*) &buf[length-2]; 559 SMC_outl(dev, *ptr, SMC91111_DATA_REG); 560 } else if (length & 1) { 561 SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); 562 } else { 563 SMC_outl(dev, 0, SMC91111_DATA_REG); 564 } 565 #endif 566 #else 567 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); 568 #endif /* USE_32_BIT */ 569 570 #ifndef CONFIG_XAENIAX 571 /* Send the last byte, if there is one. */ 572 if ((length & 1) == 0) { 573 SMC_outw (dev, 0, SMC91111_DATA_REG); 574 } else { 575 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); 576 } 577 #endif 578 579 /* and let the chipset deal with it */ 580 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); 581 582 /* poll for TX INT */ 583 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ 584 /* poll for TX_EMPTY INT - autorelease enabled */ 585 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { 586 /* sending failed */ 587 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); 588 589 /* release packet */ 590 /* no need to release, MMU does that now */ 591 #ifdef CONFIG_XAENIAX 592 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); 593 #endif 594 595 /* wait for MMU getting ready (low) */ 596 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { 597 udelay (10); 598 } 599 600 PRINTK2 ("MMU ready\n"); 601 602 603 return 0; 604 } else { 605 /* ack. int */ 606 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); 607 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ 608 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, 609 length); 610 611 /* release packet */ 612 /* no need to release, MMU does that now */ 613 #ifdef CONFIG_XAENIAX 614 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); 615 #endif 616 617 /* wait for MMU getting ready (low) */ 618 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { 619 udelay (10); 620 } 621 622 PRINTK2 ("MMU ready\n"); 623 624 625 } 626 627 /* restore previously saved registers */ 628 #ifndef CONFIG_XAENIAX 629 SMC_outb( dev, saved_pnr, PN_REG ); 630 #else 631 /* On Xaeniax board, we can't use SMC_outb here because that way 632 * the Allocate MMU command will end up written to the command register 633 * as well, which will lead to a problem. 634 */ 635 SMC_outl(dev, saved_pnr << 16, 0); 636 #endif 637 SMC_outw( dev, saved_ptr, PTR_REG ); 638 639 return length; 640 } 641 642 static int smc_write_hwaddr(struct eth_device *dev) 643 { 644 int i; 645 646 swap_to(ETHERNET); 647 SMC_SELECT_BANK (dev, 1); 648 #ifdef USE_32_BIT 649 for (i = 0; i < 6; i += 2) { 650 word address; 651 652 address = dev->enetaddr[i + 1] << 8; 653 address |= dev->enetaddr[i]; 654 SMC_outw(dev, address, (ADDR0_REG + i)); 655 } 656 #else 657 for (i = 0; i < 6; i++) 658 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); 659 #endif 660 swap_to(FLASH); 661 return 0; 662 } 663 664 /* 665 * Open and Initialize the board 666 * 667 * Set up everything, reset the card, etc .. 668 * 669 */ 670 static int smc_init(struct eth_device *dev, bd_t *bd) 671 { 672 swap_to(ETHERNET); 673 674 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); 675 676 /* reset the hardware */ 677 smc_reset (dev); 678 smc_enable (dev); 679 680 /* Configure the PHY */ 681 #ifndef CONFIG_SMC91111_EXT_PHY 682 smc_phy_configure (dev); 683 #endif 684 685 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ 686 /* SMC_SELECT_BANK(dev, 0); */ 687 /* SMC_outw(dev, 0, RPC_REG); */ 688 689 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); 690 691 return 0; 692 } 693 694 /*------------------------------------------------------------- 695 . 696 . smc_rcv - receive a packet from the card 697 . 698 . There is ( at least ) a packet waiting to be read from 699 . chip-memory. 700 . 701 . o Read the status 702 . o If an error, record it 703 . o otherwise, read in the packet 704 -------------------------------------------------------------- 705 */ 706 static int smc_rcv(struct eth_device *dev) 707 { 708 int packet_number; 709 word status; 710 word packet_length; 711 int is_error = 0; 712 #ifdef USE_32_BIT 713 dword stat_len; 714 #endif 715 byte saved_pnr; 716 word saved_ptr; 717 718 SMC_SELECT_BANK(dev, 2); 719 /* save PTR and PTR registers */ 720 saved_pnr = SMC_inb( dev, PN_REG ); 721 saved_ptr = SMC_inw( dev, PTR_REG ); 722 723 packet_number = SMC_inw( dev, RXFIFO_REG ); 724 725 if ( packet_number & RXFIFO_REMPTY ) { 726 727 return 0; 728 } 729 730 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); 731 /* start reading from the start of the packet */ 732 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); 733 734 /* First two words are status and packet_length */ 735 #ifdef USE_32_BIT 736 stat_len = SMC_inl(dev, SMC91111_DATA_REG); 737 status = stat_len & 0xffff; 738 packet_length = stat_len >> 16; 739 #else 740 status = SMC_inw( dev, SMC91111_DATA_REG ); 741 packet_length = SMC_inw( dev, SMC91111_DATA_REG ); 742 #endif 743 744 packet_length &= 0x07ff; /* mask off top bits */ 745 746 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); 747 748 if ( !(status & RS_ERRORS ) ){ 749 /* Adjust for having already read the first two words */ 750 packet_length -= 4; /*4; */ 751 752 753 /* set odd length for bug in LAN91C111, */ 754 /* which never sets RS_ODDFRAME */ 755 /* TODO ? */ 756 757 758 #ifdef USE_32_BIT 759 PRINTK3(" Reading %d dwords (and %d bytes)\n", 760 packet_length >> 2, packet_length & 3 ); 761 /* QUESTION: Like in the TX routine, do I want 762 to send the DWORDs or the bytes first, or some 763 mixture. A mixture might improve already slow PIO 764 performance */ 765 SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0], 766 packet_length >> 2); 767 /* read the left over bytes */ 768 if (packet_length & 3) { 769 int i; 770 771 byte *tail = (byte *)(net_rx_packets[0] + 772 (packet_length & ~3)); 773 dword leftover = SMC_inl(dev, SMC91111_DATA_REG); 774 for (i=0; i<(packet_length & 3); i++) 775 *tail++ = (byte) (leftover >> (8*i)) & 0xff; 776 } 777 #else 778 PRINTK3(" Reading %d words and %d byte(s)\n", 779 (packet_length >> 1 ), packet_length & 1 ); 780 SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0], 781 packet_length >> 1); 782 783 #endif /* USE_32_BIT */ 784 785 #if SMC_DEBUG > 2 786 printf("Receiving Packet\n"); 787 print_packet(net_rx_packets[0], packet_length); 788 #endif 789 } else { 790 /* error ... */ 791 /* TODO ? */ 792 is_error = 1; 793 } 794 795 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) 796 udelay(1); /* Wait until not busy */ 797 798 /* error or good, tell the card to get rid of this packet */ 799 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); 800 801 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) 802 udelay(1); /* Wait until not busy */ 803 804 /* restore saved registers */ 805 #ifndef CONFIG_XAENIAX 806 SMC_outb( dev, saved_pnr, PN_REG ); 807 #else 808 /* On Xaeniax board, we can't use SMC_outb here because that way 809 * the Allocate MMU command will end up written to the command register 810 * as well, which will lead to a problem. 811 */ 812 SMC_outl( dev, saved_pnr << 16, 0); 813 #endif 814 SMC_outw( dev, saved_ptr, PTR_REG ); 815 816 if (!is_error) { 817 /* Pass the packet up to the protocol layers. */ 818 net_process_received_packet(net_rx_packets[0], packet_length); 819 return packet_length; 820 } else { 821 return 0; 822 } 823 824 } 825 826 827 #if 0 828 /*------------------------------------------------------------ 829 . Modify a bit in the LAN91C111 register set 830 .-------------------------------------------------------------*/ 831 static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, 832 unsigned int bit, int val) 833 { 834 word regval; 835 836 SMC_SELECT_BANK( dev, bank ); 837 838 regval = SMC_inw( dev, reg ); 839 if (val) 840 regval |= bit; 841 else 842 regval &= ~bit; 843 844 SMC_outw( dev, regval, 0 ); 845 return(regval); 846 } 847 848 849 /*------------------------------------------------------------ 850 . Retrieve a bit in the LAN91C111 register set 851 .-------------------------------------------------------------*/ 852 static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) 853 { 854 SMC_SELECT_BANK( dev, bank ); 855 if ( SMC_inw( dev, reg ) & bit) 856 return(1); 857 else 858 return(0); 859 } 860 861 862 /*------------------------------------------------------------ 863 . Modify a LAN91C111 register (word access only) 864 .-------------------------------------------------------------*/ 865 static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) 866 { 867 SMC_SELECT_BANK( dev, bank ); 868 SMC_outw( dev, val, reg ); 869 } 870 871 872 /*------------------------------------------------------------ 873 . Retrieve a LAN91C111 register (word access only) 874 .-------------------------------------------------------------*/ 875 static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) 876 { 877 SMC_SELECT_BANK( dev, bank ); 878 return(SMC_inw( dev, reg )); 879 } 880 881 #endif /* 0 */ 882 883 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ 884 885 #if (SMC_DEBUG > 2 ) 886 887 /*------------------------------------------------------------ 888 . Debugging function for viewing MII Management serial bitstream 889 .-------------------------------------------------------------*/ 890 static void smc_dump_mii_stream (byte * bits, int size) 891 { 892 int i; 893 894 printf ("BIT#:"); 895 for (i = 0; i < size; ++i) { 896 printf ("%d", i % 10); 897 } 898 899 printf ("\nMDOE:"); 900 for (i = 0; i < size; ++i) { 901 if (bits[i] & MII_MDOE) 902 printf ("1"); 903 else 904 printf ("0"); 905 } 906 907 printf ("\nMDO :"); 908 for (i = 0; i < size; ++i) { 909 if (bits[i] & MII_MDO) 910 printf ("1"); 911 else 912 printf ("0"); 913 } 914 915 printf ("\nMDI :"); 916 for (i = 0; i < size; ++i) { 917 if (bits[i] & MII_MDI) 918 printf ("1"); 919 else 920 printf ("0"); 921 } 922 923 printf ("\n"); 924 } 925 #endif 926 927 /*------------------------------------------------------------ 928 . Reads a register from the MII Management serial interface 929 .-------------------------------------------------------------*/ 930 #ifndef CONFIG_SMC91111_EXT_PHY 931 static word smc_read_phy_register (struct eth_device *dev, byte phyreg) 932 { 933 int oldBank; 934 int i; 935 byte mask; 936 word mii_reg; 937 byte bits[64]; 938 int clk_idx = 0; 939 int input_idx; 940 word phydata; 941 byte phyaddr = SMC_PHY_ADDR; 942 943 /* 32 consecutive ones on MDO to establish sync */ 944 for (i = 0; i < 32; ++i) 945 bits[clk_idx++] = MII_MDOE | MII_MDO; 946 947 /* Start code <01> */ 948 bits[clk_idx++] = MII_MDOE; 949 bits[clk_idx++] = MII_MDOE | MII_MDO; 950 951 /* Read command <10> */ 952 bits[clk_idx++] = MII_MDOE | MII_MDO; 953 bits[clk_idx++] = MII_MDOE; 954 955 /* Output the PHY address, msb first */ 956 mask = (byte) 0x10; 957 for (i = 0; i < 5; ++i) { 958 if (phyaddr & mask) 959 bits[clk_idx++] = MII_MDOE | MII_MDO; 960 else 961 bits[clk_idx++] = MII_MDOE; 962 963 /* Shift to next lowest bit */ 964 mask >>= 1; 965 } 966 967 /* Output the phy register number, msb first */ 968 mask = (byte) 0x10; 969 for (i = 0; i < 5; ++i) { 970 if (phyreg & mask) 971 bits[clk_idx++] = MII_MDOE | MII_MDO; 972 else 973 bits[clk_idx++] = MII_MDOE; 974 975 /* Shift to next lowest bit */ 976 mask >>= 1; 977 } 978 979 /* Tristate and turnaround (2 bit times) */ 980 bits[clk_idx++] = 0; 981 /*bits[clk_idx++] = 0; */ 982 983 /* Input starts at this bit time */ 984 input_idx = clk_idx; 985 986 /* Will input 16 bits */ 987 for (i = 0; i < 16; ++i) 988 bits[clk_idx++] = 0; 989 990 /* Final clock bit */ 991 bits[clk_idx++] = 0; 992 993 /* Save the current bank */ 994 oldBank = SMC_inw (dev, BANK_SELECT); 995 996 /* Select bank 3 */ 997 SMC_SELECT_BANK (dev, 3); 998 999 /* Get the current MII register value */ 1000 mii_reg = SMC_inw (dev, MII_REG); 1001 1002 /* Turn off all MII Interface bits */ 1003 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); 1004 1005 /* Clock all 64 cycles */ 1006 for (i = 0; i < sizeof bits; ++i) { 1007 /* Clock Low - output data */ 1008 SMC_outw (dev, mii_reg | bits[i], MII_REG); 1009 udelay (SMC_PHY_CLOCK_DELAY); 1010 1011 1012 /* Clock Hi - input data */ 1013 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); 1014 udelay (SMC_PHY_CLOCK_DELAY); 1015 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; 1016 } 1017 1018 /* Return to idle state */ 1019 /* Set clock to low, data to low, and output tristated */ 1020 SMC_outw (dev, mii_reg, MII_REG); 1021 udelay (SMC_PHY_CLOCK_DELAY); 1022 1023 /* Restore original bank select */ 1024 SMC_SELECT_BANK (dev, oldBank); 1025 1026 /* Recover input data */ 1027 phydata = 0; 1028 for (i = 0; i < 16; ++i) { 1029 phydata <<= 1; 1030 1031 if (bits[input_idx++] & MII_MDI) 1032 phydata |= 0x0001; 1033 } 1034 1035 #if (SMC_DEBUG > 2 ) 1036 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", 1037 phyaddr, phyreg, phydata); 1038 smc_dump_mii_stream (bits, sizeof bits); 1039 #endif 1040 1041 return (phydata); 1042 } 1043 1044 1045 /*------------------------------------------------------------ 1046 . Writes a register to the MII Management serial interface 1047 .-------------------------------------------------------------*/ 1048 static void smc_write_phy_register (struct eth_device *dev, byte phyreg, 1049 word phydata) 1050 { 1051 int oldBank; 1052 int i; 1053 word mask; 1054 word mii_reg; 1055 byte bits[65]; 1056 int clk_idx = 0; 1057 byte phyaddr = SMC_PHY_ADDR; 1058 1059 /* 32 consecutive ones on MDO to establish sync */ 1060 for (i = 0; i < 32; ++i) 1061 bits[clk_idx++] = MII_MDOE | MII_MDO; 1062 1063 /* Start code <01> */ 1064 bits[clk_idx++] = MII_MDOE; 1065 bits[clk_idx++] = MII_MDOE | MII_MDO; 1066 1067 /* Write command <01> */ 1068 bits[clk_idx++] = MII_MDOE; 1069 bits[clk_idx++] = MII_MDOE | MII_MDO; 1070 1071 /* Output the PHY address, msb first */ 1072 mask = (byte) 0x10; 1073 for (i = 0; i < 5; ++i) { 1074 if (phyaddr & mask) 1075 bits[clk_idx++] = MII_MDOE | MII_MDO; 1076 else 1077 bits[clk_idx++] = MII_MDOE; 1078 1079 /* Shift to next lowest bit */ 1080 mask >>= 1; 1081 } 1082 1083 /* Output the phy register number, msb first */ 1084 mask = (byte) 0x10; 1085 for (i = 0; i < 5; ++i) { 1086 if (phyreg & mask) 1087 bits[clk_idx++] = MII_MDOE | MII_MDO; 1088 else 1089 bits[clk_idx++] = MII_MDOE; 1090 1091 /* Shift to next lowest bit */ 1092 mask >>= 1; 1093 } 1094 1095 /* Tristate and turnaround (2 bit times) */ 1096 bits[clk_idx++] = 0; 1097 bits[clk_idx++] = 0; 1098 1099 /* Write out 16 bits of data, msb first */ 1100 mask = 0x8000; 1101 for (i = 0; i < 16; ++i) { 1102 if (phydata & mask) 1103 bits[clk_idx++] = MII_MDOE | MII_MDO; 1104 else 1105 bits[clk_idx++] = MII_MDOE; 1106 1107 /* Shift to next lowest bit */ 1108 mask >>= 1; 1109 } 1110 1111 /* Final clock bit (tristate) */ 1112 bits[clk_idx++] = 0; 1113 1114 /* Save the current bank */ 1115 oldBank = SMC_inw (dev, BANK_SELECT); 1116 1117 /* Select bank 3 */ 1118 SMC_SELECT_BANK (dev, 3); 1119 1120 /* Get the current MII register value */ 1121 mii_reg = SMC_inw (dev, MII_REG); 1122 1123 /* Turn off all MII Interface bits */ 1124 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); 1125 1126 /* Clock all cycles */ 1127 for (i = 0; i < sizeof bits; ++i) { 1128 /* Clock Low - output data */ 1129 SMC_outw (dev, mii_reg | bits[i], MII_REG); 1130 udelay (SMC_PHY_CLOCK_DELAY); 1131 1132 1133 /* Clock Hi - input data */ 1134 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); 1135 udelay (SMC_PHY_CLOCK_DELAY); 1136 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; 1137 } 1138 1139 /* Return to idle state */ 1140 /* Set clock to low, data to low, and output tristated */ 1141 SMC_outw (dev, mii_reg, MII_REG); 1142 udelay (SMC_PHY_CLOCK_DELAY); 1143 1144 /* Restore original bank select */ 1145 SMC_SELECT_BANK (dev, oldBank); 1146 1147 #if (SMC_DEBUG > 2 ) 1148 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", 1149 phyaddr, phyreg, phydata); 1150 smc_dump_mii_stream (bits, sizeof bits); 1151 #endif 1152 } 1153 #endif /* !CONFIG_SMC91111_EXT_PHY */ 1154 1155 1156 /*------------------------------------------------------------ 1157 . Configures the specified PHY using Autonegotiation. Calls 1158 . smc_phy_fixed() if the user has requested a certain config. 1159 .-------------------------------------------------------------*/ 1160 #ifndef CONFIG_SMC91111_EXT_PHY 1161 static void smc_phy_configure (struct eth_device *dev) 1162 { 1163 int timeout; 1164 word my_phy_caps; /* My PHY capabilities */ 1165 word my_ad_caps; /* My Advertised capabilities */ 1166 word status = 0; /*;my status = 0 */ 1167 1168 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); 1169 1170 /* Reset the PHY, setting all other bits to zero */ 1171 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); 1172 1173 /* Wait for the reset to complete, or time out */ 1174 timeout = 6; /* Wait up to 3 seconds */ 1175 while (timeout--) { 1176 if (!(smc_read_phy_register (dev, PHY_CNTL_REG) 1177 & PHY_CNTL_RST)) { 1178 /* reset complete */ 1179 break; 1180 } 1181 1182 mdelay(500); /* wait 500 millisecs */ 1183 } 1184 1185 if (timeout < 1) { 1186 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); 1187 goto smc_phy_configure_exit; 1188 } 1189 1190 /* Read PHY Register 18, Status Output */ 1191 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ 1192 1193 /* Enable PHY Interrupts (for register 18) */ 1194 /* Interrupts listed here are disabled */ 1195 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); 1196 1197 /* Configure the Receive/Phy Control register */ 1198 SMC_SELECT_BANK (dev, 0); 1199 SMC_outw (dev, RPC_DEFAULT, RPC_REG); 1200 1201 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ 1202 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); 1203 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ 1204 1205 if (my_phy_caps & PHY_STAT_CAP_T4) 1206 my_ad_caps |= PHY_AD_T4; 1207 1208 if (my_phy_caps & PHY_STAT_CAP_TXF) 1209 my_ad_caps |= PHY_AD_TX_FDX; 1210 1211 if (my_phy_caps & PHY_STAT_CAP_TXH) 1212 my_ad_caps |= PHY_AD_TX_HDX; 1213 1214 if (my_phy_caps & PHY_STAT_CAP_TF) 1215 my_ad_caps |= PHY_AD_10_FDX; 1216 1217 if (my_phy_caps & PHY_STAT_CAP_TH) 1218 my_ad_caps |= PHY_AD_10_HDX; 1219 1220 /* Update our Auto-Neg Advertisement Register */ 1221 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); 1222 1223 /* Read the register back. Without this, it appears that when */ 1224 /* auto-negotiation is restarted, sometimes it isn't ready and */ 1225 /* the link does not come up. */ 1226 smc_read_phy_register(dev, PHY_AD_REG); 1227 1228 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); 1229 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); 1230 1231 /* Restart auto-negotiation process in order to advertise my caps */ 1232 smc_write_phy_register (dev, PHY_CNTL_REG, 1233 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); 1234 1235 /* Wait for the auto-negotiation to complete. This may take from */ 1236 /* 2 to 3 seconds. */ 1237 /* Wait for the reset to complete, or time out */ 1238 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; 1239 while (timeout--) { 1240 1241 status = smc_read_phy_register (dev, PHY_STAT_REG); 1242 if (status & PHY_STAT_ANEG_ACK) { 1243 /* auto-negotiate complete */ 1244 break; 1245 } 1246 1247 mdelay(500); /* wait 500 millisecs */ 1248 1249 /* Restart auto-negotiation if remote fault */ 1250 if (status & PHY_STAT_REM_FLT) { 1251 printf ("%s: PHY remote fault detected\n", 1252 SMC_DEV_NAME); 1253 1254 /* Restart auto-negotiation */ 1255 printf ("%s: PHY restarting auto-negotiation\n", 1256 SMC_DEV_NAME); 1257 smc_write_phy_register (dev, PHY_CNTL_REG, 1258 PHY_CNTL_ANEG_EN | 1259 PHY_CNTL_ANEG_RST | 1260 PHY_CNTL_SPEED | 1261 PHY_CNTL_DPLX); 1262 } 1263 } 1264 1265 if (timeout < 1) { 1266 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); 1267 } 1268 1269 /* Fail if we detected an auto-negotiate remote fault */ 1270 if (status & PHY_STAT_REM_FLT) { 1271 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); 1272 } 1273 1274 /* Re-Configure the Receive/Phy Control register */ 1275 SMC_outw (dev, RPC_DEFAULT, RPC_REG); 1276 1277 smc_phy_configure_exit: ; 1278 1279 } 1280 #endif /* !CONFIG_SMC91111_EXT_PHY */ 1281 1282 1283 #if SMC_DEBUG > 2 1284 static void print_packet( byte * buf, int length ) 1285 { 1286 int i; 1287 int remainder; 1288 int lines; 1289 1290 printf("Packet of length %d \n", length ); 1291 1292 #if SMC_DEBUG > 3 1293 lines = length / 16; 1294 remainder = length % 16; 1295 1296 for ( i = 0; i < lines ; i ++ ) { 1297 int cur; 1298 1299 for ( cur = 0; cur < 8; cur ++ ) { 1300 byte a, b; 1301 1302 a = *(buf ++ ); 1303 b = *(buf ++ ); 1304 printf("%02x%02x ", a, b ); 1305 } 1306 printf("\n"); 1307 } 1308 for ( i = 0; i < remainder/2 ; i++ ) { 1309 byte a, b; 1310 1311 a = *(buf ++ ); 1312 b = *(buf ++ ); 1313 printf("%02x%02x ", a, b ); 1314 } 1315 printf("\n"); 1316 #endif 1317 } 1318 #endif 1319 1320 int smc91111_initialize(u8 dev_num, int base_addr) 1321 { 1322 struct smc91111_priv *priv; 1323 struct eth_device *dev; 1324 int i; 1325 1326 priv = malloc(sizeof(*priv)); 1327 if (!priv) 1328 return 0; 1329 dev = malloc(sizeof(*dev)); 1330 if (!dev) { 1331 free(priv); 1332 return 0; 1333 } 1334 1335 memset(dev, 0, sizeof(*dev)); 1336 priv->dev_num = dev_num; 1337 dev->priv = priv; 1338 dev->iobase = base_addr; 1339 1340 swap_to(ETHERNET); 1341 SMC_SELECT_BANK(dev, 1); 1342 for (i = 0; i < 6; ++i) 1343 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); 1344 swap_to(FLASH); 1345 1346 dev->init = smc_init; 1347 dev->halt = smc_halt; 1348 dev->send = smc_send; 1349 dev->recv = smc_rcv; 1350 dev->write_hwaddr = smc_write_hwaddr; 1351 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); 1352 1353 eth_register(dev); 1354 return 0; 1355 } 1356