1 /*------------------------------------------------------------------------ 2 . smc91111.c 3 . This is a driver for SMSC's 91C111 single-chip Ethernet device. 4 . 5 . (C) Copyright 2002 6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 . Rolf Offermanns <rof@sysgo.de> 8 . 9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 10 . Developed by Simple Network Magic Corporation (SNMC) 11 . Copyright (C) 1996 by Erik Stahlman (ES) 12 . 13 . This program is free software; you can redistribute it and/or modify 14 . it under the terms of the GNU General Public License as published by 15 . the Free Software Foundation; either version 2 of the License, or 16 . (at your option) any later version. 17 . 18 . This program is distributed in the hope that it will be useful, 19 . but WITHOUT ANY WARRANTY; without even the implied warranty of 20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 . GNU General Public License for more details. 22 . 23 . You should have received a copy of the GNU General Public License 24 . along with this program; if not, write to the Free Software 25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 . 27 . Information contained in this file was obtained from the LAN91C111 28 . manual from SMC. To get a copy, if you really want one, you can find 29 . information under www.smsc.com. 30 . 31 . 32 . "Features" of the SMC chip: 33 . Integrated PHY/MAC for 10/100BaseT Operation 34 . Supports internal and external MII 35 . Integrated 8K packet memory 36 . EEPROM interface for configuration 37 . 38 . Arguments: 39 . io = for the base address 40 . irq = for the IRQ 41 . 42 . author: 43 . Erik Stahlman ( erik@vt.edu ) 44 . Daris A Nevil ( dnevil@snmc.com ) 45 . 46 . 47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) 48 . 49 . Sources: 50 . o SMSC LAN91C111 databook (www.smsc.com) 51 . o smc9194.c by Erik Stahlman 52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) 53 . 54 . History: 55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. 56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110 57 . 07/25/01 Woojung Huh Modify for ADS Bitsy 58 . 04/25/01 Daris A Nevil Initial public release through SMSC 59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 60 ----------------------------------------------------------------------------*/ 61 62 #include <common.h> 63 #include <command.h> 64 #include <config.h> 65 #include <malloc.h> 66 #include "smc91111.h" 67 #include <net.h> 68 69 /* Use power-down feature of the chip */ 70 #define POWER_DOWN 0 71 72 #define NO_AUTOPROBE 73 74 #define SMC_DEBUG 0 75 76 #if SMC_DEBUG > 1 77 static const char version[] = 78 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; 79 #endif 80 81 /* Autonegotiation timeout in seconds */ 82 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT 83 #define CONFIG_SMC_AUTONEG_TIMEOUT 10 84 #endif 85 86 /*------------------------------------------------------------------------ 87 . 88 . Configuration options, for the experienced user to change. 89 . 90 -------------------------------------------------------------------------*/ 91 92 /* 93 . Wait time for memory to be free. This probably shouldn't be 94 . tuned that much, as waiting for this means nothing else happens 95 . in the system 96 */ 97 #define MEMORY_WAIT_TIME 16 98 99 100 #if (SMC_DEBUG > 2 ) 101 #define PRINTK3(args...) printf(args) 102 #else 103 #define PRINTK3(args...) 104 #endif 105 106 #if SMC_DEBUG > 1 107 #define PRINTK2(args...) printf(args) 108 #else 109 #define PRINTK2(args...) 110 #endif 111 112 #ifdef SMC_DEBUG 113 #define PRINTK(args...) printf(args) 114 #else 115 #define PRINTK(args...) 116 #endif 117 118 119 /*------------------------------------------------------------------------ 120 . 121 . The internal workings of the driver. If you are changing anything 122 . here with the SMC stuff, you should have the datasheet and know 123 . what you are doing. 124 . 125 -------------------------------------------------------------------------*/ 126 127 /* Memory sizing constant */ 128 #define LAN91C111_MEMORY_MULTIPLIER (1024*2) 129 130 #ifndef CONFIG_SMC91111_BASE 131 #error "SMC91111 Base address must be passed to initialization funciton" 132 /* #define CONFIG_SMC91111_BASE 0x20000300 */ 133 #endif 134 135 #define SMC_DEV_NAME "SMC91111" 136 #define SMC_PHY_ADDR 0x0000 137 #define SMC_ALLOC_MAX_TRY 5 138 #define SMC_TX_TIMEOUT 30 139 140 #define SMC_PHY_CLOCK_DELAY 1000 141 142 #define ETH_ZLEN 60 143 144 #ifdef CONFIG_SMC_USE_32_BIT 145 #define USE_32_BIT 1 146 #else 147 #undef USE_32_BIT 148 #endif 149 150 #ifdef SHARED_RESOURCES 151 extern void swap_to(int device_id); 152 #else 153 # define swap_to(x) 154 #endif 155 156 #ifndef CONFIG_SMC91111_EXT_PHY 157 static void smc_phy_configure(struct eth_device *dev); 158 #endif /* !CONFIG_SMC91111_EXT_PHY */ 159 160 /* 161 ------------------------------------------------------------ 162 . 163 . Internal routines 164 . 165 ------------------------------------------------------------ 166 */ 167 168 #ifdef CONFIG_SMC_USE_IOFUNCS 169 /* 170 * input and output functions 171 * 172 * Implemented due to inx,outx macros accessing the device improperly 173 * and putting the device into an unkown state. 174 * 175 * For instance, on Sharp LPD7A400 SDK, affects were chip memory 176 * could not be free'd (hence the alloc failures), duplicate packets, 177 * packets being corrupt (shifted) on the wire, etc. Switching to the 178 * inx,outx functions fixed this problem. 179 */ 180 181 static inline word SMC_inw(struct eth_device *dev, dword offset) 182 { 183 word v; 184 v = *((volatile word*)(dev->iobase + offset)); 185 barrier(); *(volatile u32*)(0xc0000000); 186 return v; 187 } 188 189 static inline void SMC_outw(struct eth_device *dev, word value, dword offset) 190 { 191 *((volatile word*)(dev->iobase + offset)) = value; 192 barrier(); *(volatile u32*)(0xc0000000); 193 } 194 195 static inline byte SMC_inb(struct eth_device *dev, dword offset) 196 { 197 word _w; 198 199 _w = SMC_inw(dev, offset & ~((dword)1)); 200 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); 201 } 202 203 static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) 204 { 205 word _w; 206 207 _w = SMC_inw(dev, offset & ~((dword)1)); 208 if (offset & 1) 209 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = 210 (value<<8) | (_w & 0x00ff); 211 else 212 *((volatile word*)(dev->iobase + offset)) = 213 value | (_w & 0xff00); 214 } 215 216 static inline void SMC_insw(struct eth_device *dev, dword offset, 217 volatile uchar* buf, dword len) 218 { 219 volatile word *p = (volatile word *)buf; 220 221 while (len-- > 0) { 222 *p++ = SMC_inw(dev, offset); 223 barrier(); 224 *((volatile u32*)(0xc0000000)); 225 } 226 } 227 228 static inline void SMC_outsw(struct eth_device *dev, dword offset, 229 uchar* buf, dword len) 230 { 231 volatile word *p = (volatile word *)buf; 232 233 while (len-- > 0) { 234 SMC_outw(dev, *p++, offset); 235 barrier(); 236 *(volatile u32*)(0xc0000000); 237 } 238 } 239 #endif /* CONFIG_SMC_USE_IOFUNCS */ 240 241 /* 242 . A rather simple routine to print out a packet for debugging purposes. 243 */ 244 #if SMC_DEBUG > 2 245 static void print_packet( byte *, int ); 246 #endif 247 248 #define tx_done(dev) 1 249 250 static int poll4int (struct eth_device *dev, byte mask, int timeout) 251 { 252 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; 253 int is_timeout = 0; 254 word old_bank = SMC_inw (dev, BSR_REG); 255 256 PRINTK2 ("Polling...\n"); 257 SMC_SELECT_BANK (dev, 2); 258 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { 259 if (get_timer (0) >= tmo) { 260 is_timeout = 1; 261 break; 262 } 263 } 264 265 /* restore old bank selection */ 266 SMC_SELECT_BANK (dev, old_bank); 267 268 if (is_timeout) 269 return 1; 270 else 271 return 0; 272 } 273 274 /* Only one release command at a time, please */ 275 static inline void smc_wait_mmu_release_complete (struct eth_device *dev) 276 { 277 int count = 0; 278 279 /* assume bank 2 selected */ 280 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { 281 udelay (1); /* Wait until not busy */ 282 if (++count > 200) 283 break; 284 } 285 } 286 287 /* 288 . Function: smc_reset( void ) 289 . Purpose: 290 . This sets the SMC91111 chip to its normal state, hopefully from whatever 291 . mess that any other DOS driver has put it in. 292 . 293 . Maybe I should reset more registers to defaults in here? SOFTRST should 294 . do that for me. 295 . 296 . Method: 297 . 1. send a SOFT RESET 298 . 2. wait for it to finish 299 . 3. enable autorelease mode 300 . 4. reset the memory management unit 301 . 5. clear all interrupts 302 . 303 */ 304 static void smc_reset (struct eth_device *dev) 305 { 306 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); 307 308 /* This resets the registers mostly to defaults, but doesn't 309 affect EEPROM. That seems unnecessary */ 310 SMC_SELECT_BANK (dev, 0); 311 SMC_outw (dev, RCR_SOFTRST, RCR_REG); 312 313 /* Setup the Configuration Register */ 314 /* This is necessary because the CONFIG_REG is not affected */ 315 /* by a soft reset */ 316 317 SMC_SELECT_BANK (dev, 1); 318 #if defined(CONFIG_SMC91111_EXT_PHY) 319 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); 320 #else 321 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); 322 #endif 323 324 325 /* Release from possible power-down state */ 326 /* Configuration register is not affected by Soft Reset */ 327 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, 328 CONFIG_REG); 329 330 SMC_SELECT_BANK (dev, 0); 331 332 /* this should pause enough for the chip to be happy */ 333 udelay (10); 334 335 /* Disable transmit and receive functionality */ 336 SMC_outw (dev, RCR_CLEAR, RCR_REG); 337 SMC_outw (dev, TCR_CLEAR, TCR_REG); 338 339 /* set the control register */ 340 SMC_SELECT_BANK (dev, 1); 341 SMC_outw (dev, CTL_DEFAULT, CTL_REG); 342 343 /* Reset the MMU */ 344 SMC_SELECT_BANK (dev, 2); 345 smc_wait_mmu_release_complete (dev); 346 SMC_outw (dev, MC_RESET, MMU_CMD_REG); 347 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) 348 udelay (1); /* Wait until not busy */ 349 350 /* Note: It doesn't seem that waiting for the MMU busy is needed here, 351 but this is a place where future chipsets _COULD_ break. Be wary 352 of issuing another MMU command right after this */ 353 354 /* Disable all interrupts */ 355 SMC_outb (dev, 0, IM_REG); 356 } 357 358 /* 359 . Function: smc_enable 360 . Purpose: let the chip talk to the outside work 361 . Method: 362 . 1. Enable the transmitter 363 . 2. Enable the receiver 364 . 3. Enable interrupts 365 */ 366 static void smc_enable(struct eth_device *dev) 367 { 368 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); 369 SMC_SELECT_BANK( dev, 0 ); 370 /* see the header file for options in TCR/RCR DEFAULT*/ 371 SMC_outw( dev, TCR_DEFAULT, TCR_REG ); 372 SMC_outw( dev, RCR_DEFAULT, RCR_REG ); 373 374 /* clear MII_DIS */ 375 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ 376 } 377 378 /* 379 . Function: smc_halt 380 . Purpose: closes down the SMC91xxx chip. 381 . Method: 382 . 1. zero the interrupt mask 383 . 2. clear the enable receive flag 384 . 3. clear the enable xmit flags 385 . 386 . TODO: 387 . (1) maybe utilize power down mode. 388 . Why not yet? Because while the chip will go into power down mode, 389 . the manual says that it will wake up in response to any I/O requests 390 . in the register space. Empirical results do not show this working. 391 */ 392 static void smc_halt(struct eth_device *dev) 393 { 394 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); 395 396 /* no more interrupts for me */ 397 SMC_SELECT_BANK( dev, 2 ); 398 SMC_outb( dev, 0, IM_REG ); 399 400 /* and tell the card to stay away from that nasty outside world */ 401 SMC_SELECT_BANK( dev, 0 ); 402 SMC_outb( dev, RCR_CLEAR, RCR_REG ); 403 SMC_outb( dev, TCR_CLEAR, TCR_REG ); 404 405 swap_to(FLASH); 406 } 407 408 409 /* 410 . Function: smc_send(struct net_device * ) 411 . Purpose: 412 . This sends the actual packet to the SMC9xxx chip. 413 . 414 . Algorithm: 415 . First, see if a saved_skb is available. 416 . ( this should NOT be called if there is no 'saved_skb' 417 . Now, find the packet number that the chip allocated 418 . Point the data pointers at it in memory 419 . Set the length word in the chip's memory 420 . Dump the packet to chip memory 421 . Check if a last byte is needed ( odd length packet ) 422 . if so, set the control flag right 423 . Tell the card to send it 424 . Enable the transmit interrupt, so I know if it failed 425 . Free the kernel data if I actually sent it. 426 */ 427 static int smc_send(struct eth_device *dev, void *packet, int packet_length) 428 { 429 byte packet_no; 430 byte *buf; 431 int length; 432 int numPages; 433 int try = 0; 434 int time_out; 435 byte status; 436 byte saved_pnr; 437 word saved_ptr; 438 439 /* save PTR and PNR registers before manipulation */ 440 SMC_SELECT_BANK (dev, 2); 441 saved_pnr = SMC_inb( dev, PN_REG ); 442 saved_ptr = SMC_inw( dev, PTR_REG ); 443 444 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); 445 446 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; 447 448 /* allocate memory 449 ** The MMU wants the number of pages to be the number of 256 bytes 450 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) 451 ** 452 ** The 91C111 ignores the size bits, but the code is left intact 453 ** for backwards and future compatibility. 454 ** 455 ** Pkt size for allocating is data length +6 (for additional status 456 ** words, length and ctl!) 457 ** 458 ** If odd size then last byte is included in this header. 459 */ 460 numPages = ((length & 0xfffe) + 6); 461 numPages >>= 8; /* Divide by 256 */ 462 463 if (numPages > 7) { 464 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); 465 return 0; 466 } 467 468 /* now, try to allocate the memory */ 469 SMC_SELECT_BANK (dev, 2); 470 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); 471 472 /* FIXME: the ALLOC_INT bit never gets set * 473 * so the following will always give a * 474 * memory allocation error. * 475 * same code works in armboot though * 476 * -ro 477 */ 478 479 again: 480 try++; 481 time_out = MEMORY_WAIT_TIME; 482 do { 483 status = SMC_inb (dev, SMC91111_INT_REG); 484 if (status & IM_ALLOC_INT) { 485 /* acknowledge the interrupt */ 486 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); 487 break; 488 } 489 } while (--time_out); 490 491 if (!time_out) { 492 PRINTK2 ("%s: memory allocation, try %d failed ...\n", 493 SMC_DEV_NAME, try); 494 if (try < SMC_ALLOC_MAX_TRY) 495 goto again; 496 else 497 return 0; 498 } 499 500 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", 501 SMC_DEV_NAME, try); 502 503 buf = (byte *) packet; 504 505 /* If I get here, I _know_ there is a packet slot waiting for me */ 506 packet_no = SMC_inb (dev, AR_REG); 507 if (packet_no & AR_FAILED) { 508 /* or isn't there? BAD CHIP! */ 509 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); 510 return 0; 511 } 512 513 /* we have a packet address, so tell the card to use it */ 514 #ifndef CONFIG_XAENIAX 515 SMC_outb (dev, packet_no, PN_REG); 516 #else 517 /* On Xaeniax board, we can't use SMC_outb here because that way 518 * the Allocate MMU command will end up written to the command register 519 * as well, which will lead to a problem. 520 */ 521 SMC_outl (dev, packet_no << 16, 0); 522 #endif 523 /* do not write new ptr value if Write data fifo not empty */ 524 while ( saved_ptr & PTR_NOTEMPTY ) 525 printf ("Write data fifo not empty!\n"); 526 527 /* point to the beginning of the packet */ 528 SMC_outw (dev, PTR_AUTOINC, PTR_REG); 529 530 PRINTK3 ("%s: Trying to xmit packet of length %x\n", 531 SMC_DEV_NAME, length); 532 533 #if SMC_DEBUG > 2 534 printf ("Transmitting Packet\n"); 535 print_packet (buf, length); 536 #endif 537 538 /* send the packet length ( +6 for status, length and ctl byte ) 539 and the status word ( set to zeros ) */ 540 #ifdef USE_32_BIT 541 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); 542 #else 543 SMC_outw (dev, 0, SMC91111_DATA_REG); 544 /* send the packet length ( +6 for status words, length, and ctl */ 545 SMC_outw (dev, (length + 6), SMC91111_DATA_REG); 546 #endif 547 548 /* send the actual data 549 . I _think_ it's faster to send the longs first, and then 550 . mop up by sending the last word. It depends heavily 551 . on alignment, at least on the 486. Maybe it would be 552 . a good idea to check which is optimal? But that could take 553 . almost as much time as is saved? 554 */ 555 #ifdef USE_32_BIT 556 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); 557 #ifndef CONFIG_XAENIAX 558 if (length & 0x2) 559 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), 560 SMC91111_DATA_REG); 561 #else 562 /* On XANEIAX, we can only use 32-bit writes, so we need to handle 563 * unaligned tail part specially. The standard code doesn't work. 564 */ 565 if ((length & 3) == 3) { 566 u16 * ptr = (u16*) &buf[length-3]; 567 SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), 568 SMC91111_DATA_REG); 569 } else if ((length & 2) == 2) { 570 u16 * ptr = (u16*) &buf[length-2]; 571 SMC_outl(dev, *ptr, SMC91111_DATA_REG); 572 } else if (length & 1) { 573 SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); 574 } else { 575 SMC_outl(dev, 0, SMC91111_DATA_REG); 576 } 577 #endif 578 #else 579 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); 580 #endif /* USE_32_BIT */ 581 582 #ifndef CONFIG_XAENIAX 583 /* Send the last byte, if there is one. */ 584 if ((length & 1) == 0) { 585 SMC_outw (dev, 0, SMC91111_DATA_REG); 586 } else { 587 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); 588 } 589 #endif 590 591 /* and let the chipset deal with it */ 592 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); 593 594 /* poll for TX INT */ 595 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ 596 /* poll for TX_EMPTY INT - autorelease enabled */ 597 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { 598 /* sending failed */ 599 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); 600 601 /* release packet */ 602 /* no need to release, MMU does that now */ 603 #ifdef CONFIG_XAENIAX 604 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); 605 #endif 606 607 /* wait for MMU getting ready (low) */ 608 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { 609 udelay (10); 610 } 611 612 PRINTK2 ("MMU ready\n"); 613 614 615 return 0; 616 } else { 617 /* ack. int */ 618 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); 619 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ 620 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, 621 length); 622 623 /* release packet */ 624 /* no need to release, MMU does that now */ 625 #ifdef CONFIG_XAENIAX 626 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); 627 #endif 628 629 /* wait for MMU getting ready (low) */ 630 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { 631 udelay (10); 632 } 633 634 PRINTK2 ("MMU ready\n"); 635 636 637 } 638 639 /* restore previously saved registers */ 640 #ifndef CONFIG_XAENIAX 641 SMC_outb( dev, saved_pnr, PN_REG ); 642 #else 643 /* On Xaeniax board, we can't use SMC_outb here because that way 644 * the Allocate MMU command will end up written to the command register 645 * as well, which will lead to a problem. 646 */ 647 SMC_outl(dev, saved_pnr << 16, 0); 648 #endif 649 SMC_outw( dev, saved_ptr, PTR_REG ); 650 651 return length; 652 } 653 654 static int smc_write_hwaddr(struct eth_device *dev) 655 { 656 int i; 657 658 swap_to(ETHERNET); 659 SMC_SELECT_BANK (dev, 1); 660 #ifdef USE_32_BIT 661 for (i = 0; i < 6; i += 2) { 662 word address; 663 664 address = dev->enetaddr[i + 1] << 8; 665 address |= dev->enetaddr[i]; 666 SMC_outw(dev, address, (ADDR0_REG + i)); 667 } 668 #else 669 for (i = 0; i < 6; i++) 670 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); 671 #endif 672 swap_to(FLASH); 673 return 0; 674 } 675 676 /* 677 * Open and Initialize the board 678 * 679 * Set up everything, reset the card, etc .. 680 * 681 */ 682 static int smc_init(struct eth_device *dev, bd_t *bd) 683 { 684 swap_to(ETHERNET); 685 686 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); 687 688 /* reset the hardware */ 689 smc_reset (dev); 690 smc_enable (dev); 691 692 /* Configure the PHY */ 693 #ifndef CONFIG_SMC91111_EXT_PHY 694 smc_phy_configure (dev); 695 #endif 696 697 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ 698 /* SMC_SELECT_BANK(dev, 0); */ 699 /* SMC_outw(dev, 0, RPC_REG); */ 700 701 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); 702 703 return 0; 704 } 705 706 /*------------------------------------------------------------- 707 . 708 . smc_rcv - receive a packet from the card 709 . 710 . There is ( at least ) a packet waiting to be read from 711 . chip-memory. 712 . 713 . o Read the status 714 . o If an error, record it 715 . o otherwise, read in the packet 716 -------------------------------------------------------------- 717 */ 718 static int smc_rcv(struct eth_device *dev) 719 { 720 int packet_number; 721 word status; 722 word packet_length; 723 int is_error = 0; 724 #ifdef USE_32_BIT 725 dword stat_len; 726 #endif 727 byte saved_pnr; 728 word saved_ptr; 729 730 SMC_SELECT_BANK(dev, 2); 731 /* save PTR and PTR registers */ 732 saved_pnr = SMC_inb( dev, PN_REG ); 733 saved_ptr = SMC_inw( dev, PTR_REG ); 734 735 packet_number = SMC_inw( dev, RXFIFO_REG ); 736 737 if ( packet_number & RXFIFO_REMPTY ) { 738 739 return 0; 740 } 741 742 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); 743 /* start reading from the start of the packet */ 744 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); 745 746 /* First two words are status and packet_length */ 747 #ifdef USE_32_BIT 748 stat_len = SMC_inl(dev, SMC91111_DATA_REG); 749 status = stat_len & 0xffff; 750 packet_length = stat_len >> 16; 751 #else 752 status = SMC_inw( dev, SMC91111_DATA_REG ); 753 packet_length = SMC_inw( dev, SMC91111_DATA_REG ); 754 #endif 755 756 packet_length &= 0x07ff; /* mask off top bits */ 757 758 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); 759 760 if ( !(status & RS_ERRORS ) ){ 761 /* Adjust for having already read the first two words */ 762 packet_length -= 4; /*4; */ 763 764 765 /* set odd length for bug in LAN91C111, */ 766 /* which never sets RS_ODDFRAME */ 767 /* TODO ? */ 768 769 770 #ifdef USE_32_BIT 771 PRINTK3(" Reading %d dwords (and %d bytes) \n", 772 packet_length >> 2, packet_length & 3 ); 773 /* QUESTION: Like in the TX routine, do I want 774 to send the DWORDs or the bytes first, or some 775 mixture. A mixture might improve already slow PIO 776 performance */ 777 SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0], 778 packet_length >> 2 ); 779 /* read the left over bytes */ 780 if (packet_length & 3) { 781 int i; 782 783 byte *tail = (byte *)(NetRxPackets[0] + 784 (packet_length & ~3)); 785 dword leftover = SMC_inl(dev, SMC91111_DATA_REG); 786 for (i=0; i<(packet_length & 3); i++) 787 *tail++ = (byte) (leftover >> (8*i)) & 0xff; 788 } 789 #else 790 PRINTK3(" Reading %d words and %d byte(s) \n", 791 (packet_length >> 1 ), packet_length & 1 ); 792 SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0], 793 packet_length >> 1); 794 795 #endif /* USE_32_BIT */ 796 797 #if SMC_DEBUG > 2 798 printf("Receiving Packet\n"); 799 print_packet( NetRxPackets[0], packet_length ); 800 #endif 801 } else { 802 /* error ... */ 803 /* TODO ? */ 804 is_error = 1; 805 } 806 807 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) 808 udelay(1); /* Wait until not busy */ 809 810 /* error or good, tell the card to get rid of this packet */ 811 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); 812 813 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) 814 udelay(1); /* Wait until not busy */ 815 816 /* restore saved registers */ 817 #ifndef CONFIG_XAENIAX 818 SMC_outb( dev, saved_pnr, PN_REG ); 819 #else 820 /* On Xaeniax board, we can't use SMC_outb here because that way 821 * the Allocate MMU command will end up written to the command register 822 * as well, which will lead to a problem. 823 */ 824 SMC_outl( dev, saved_pnr << 16, 0); 825 #endif 826 SMC_outw( dev, saved_ptr, PTR_REG ); 827 828 if (!is_error) { 829 /* Pass the packet up to the protocol layers. */ 830 NetReceive(NetRxPackets[0], packet_length); 831 return packet_length; 832 } else { 833 return 0; 834 } 835 836 } 837 838 839 #if 0 840 /*------------------------------------------------------------ 841 . Modify a bit in the LAN91C111 register set 842 .-------------------------------------------------------------*/ 843 static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, 844 unsigned int bit, int val) 845 { 846 word regval; 847 848 SMC_SELECT_BANK( dev, bank ); 849 850 regval = SMC_inw( dev, reg ); 851 if (val) 852 regval |= bit; 853 else 854 regval &= ~bit; 855 856 SMC_outw( dev, regval, 0 ); 857 return(regval); 858 } 859 860 861 /*------------------------------------------------------------ 862 . Retrieve a bit in the LAN91C111 register set 863 .-------------------------------------------------------------*/ 864 static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) 865 { 866 SMC_SELECT_BANK( dev, bank ); 867 if ( SMC_inw( dev, reg ) & bit) 868 return(1); 869 else 870 return(0); 871 } 872 873 874 /*------------------------------------------------------------ 875 . Modify a LAN91C111 register (word access only) 876 .-------------------------------------------------------------*/ 877 static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) 878 { 879 SMC_SELECT_BANK( dev, bank ); 880 SMC_outw( dev, val, reg ); 881 } 882 883 884 /*------------------------------------------------------------ 885 . Retrieve a LAN91C111 register (word access only) 886 .-------------------------------------------------------------*/ 887 static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) 888 { 889 SMC_SELECT_BANK( dev, bank ); 890 return(SMC_inw( dev, reg )); 891 } 892 893 #endif /* 0 */ 894 895 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ 896 897 #if (SMC_DEBUG > 2 ) 898 899 /*------------------------------------------------------------ 900 . Debugging function for viewing MII Management serial bitstream 901 .-------------------------------------------------------------*/ 902 static void smc_dump_mii_stream (byte * bits, int size) 903 { 904 int i; 905 906 printf ("BIT#:"); 907 for (i = 0; i < size; ++i) { 908 printf ("%d", i % 10); 909 } 910 911 printf ("\nMDOE:"); 912 for (i = 0; i < size; ++i) { 913 if (bits[i] & MII_MDOE) 914 printf ("1"); 915 else 916 printf ("0"); 917 } 918 919 printf ("\nMDO :"); 920 for (i = 0; i < size; ++i) { 921 if (bits[i] & MII_MDO) 922 printf ("1"); 923 else 924 printf ("0"); 925 } 926 927 printf ("\nMDI :"); 928 for (i = 0; i < size; ++i) { 929 if (bits[i] & MII_MDI) 930 printf ("1"); 931 else 932 printf ("0"); 933 } 934 935 printf ("\n"); 936 } 937 #endif 938 939 /*------------------------------------------------------------ 940 . Reads a register from the MII Management serial interface 941 .-------------------------------------------------------------*/ 942 #ifndef CONFIG_SMC91111_EXT_PHY 943 static word smc_read_phy_register (struct eth_device *dev, byte phyreg) 944 { 945 int oldBank; 946 int i; 947 byte mask; 948 word mii_reg; 949 byte bits[64]; 950 int clk_idx = 0; 951 int input_idx; 952 word phydata; 953 byte phyaddr = SMC_PHY_ADDR; 954 955 /* 32 consecutive ones on MDO to establish sync */ 956 for (i = 0; i < 32; ++i) 957 bits[clk_idx++] = MII_MDOE | MII_MDO; 958 959 /* Start code <01> */ 960 bits[clk_idx++] = MII_MDOE; 961 bits[clk_idx++] = MII_MDOE | MII_MDO; 962 963 /* Read command <10> */ 964 bits[clk_idx++] = MII_MDOE | MII_MDO; 965 bits[clk_idx++] = MII_MDOE; 966 967 /* Output the PHY address, msb first */ 968 mask = (byte) 0x10; 969 for (i = 0; i < 5; ++i) { 970 if (phyaddr & mask) 971 bits[clk_idx++] = MII_MDOE | MII_MDO; 972 else 973 bits[clk_idx++] = MII_MDOE; 974 975 /* Shift to next lowest bit */ 976 mask >>= 1; 977 } 978 979 /* Output the phy register number, msb first */ 980 mask = (byte) 0x10; 981 for (i = 0; i < 5; ++i) { 982 if (phyreg & mask) 983 bits[clk_idx++] = MII_MDOE | MII_MDO; 984 else 985 bits[clk_idx++] = MII_MDOE; 986 987 /* Shift to next lowest bit */ 988 mask >>= 1; 989 } 990 991 /* Tristate and turnaround (2 bit times) */ 992 bits[clk_idx++] = 0; 993 /*bits[clk_idx++] = 0; */ 994 995 /* Input starts at this bit time */ 996 input_idx = clk_idx; 997 998 /* Will input 16 bits */ 999 for (i = 0; i < 16; ++i) 1000 bits[clk_idx++] = 0; 1001 1002 /* Final clock bit */ 1003 bits[clk_idx++] = 0; 1004 1005 /* Save the current bank */ 1006 oldBank = SMC_inw (dev, BANK_SELECT); 1007 1008 /* Select bank 3 */ 1009 SMC_SELECT_BANK (dev, 3); 1010 1011 /* Get the current MII register value */ 1012 mii_reg = SMC_inw (dev, MII_REG); 1013 1014 /* Turn off all MII Interface bits */ 1015 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); 1016 1017 /* Clock all 64 cycles */ 1018 for (i = 0; i < sizeof bits; ++i) { 1019 /* Clock Low - output data */ 1020 SMC_outw (dev, mii_reg | bits[i], MII_REG); 1021 udelay (SMC_PHY_CLOCK_DELAY); 1022 1023 1024 /* Clock Hi - input data */ 1025 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); 1026 udelay (SMC_PHY_CLOCK_DELAY); 1027 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; 1028 } 1029 1030 /* Return to idle state */ 1031 /* Set clock to low, data to low, and output tristated */ 1032 SMC_outw (dev, mii_reg, MII_REG); 1033 udelay (SMC_PHY_CLOCK_DELAY); 1034 1035 /* Restore original bank select */ 1036 SMC_SELECT_BANK (dev, oldBank); 1037 1038 /* Recover input data */ 1039 phydata = 0; 1040 for (i = 0; i < 16; ++i) { 1041 phydata <<= 1; 1042 1043 if (bits[input_idx++] & MII_MDI) 1044 phydata |= 0x0001; 1045 } 1046 1047 #if (SMC_DEBUG > 2 ) 1048 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", 1049 phyaddr, phyreg, phydata); 1050 smc_dump_mii_stream (bits, sizeof bits); 1051 #endif 1052 1053 return (phydata); 1054 } 1055 1056 1057 /*------------------------------------------------------------ 1058 . Writes a register to the MII Management serial interface 1059 .-------------------------------------------------------------*/ 1060 static void smc_write_phy_register (struct eth_device *dev, byte phyreg, 1061 word phydata) 1062 { 1063 int oldBank; 1064 int i; 1065 word mask; 1066 word mii_reg; 1067 byte bits[65]; 1068 int clk_idx = 0; 1069 byte phyaddr = SMC_PHY_ADDR; 1070 1071 /* 32 consecutive ones on MDO to establish sync */ 1072 for (i = 0; i < 32; ++i) 1073 bits[clk_idx++] = MII_MDOE | MII_MDO; 1074 1075 /* Start code <01> */ 1076 bits[clk_idx++] = MII_MDOE; 1077 bits[clk_idx++] = MII_MDOE | MII_MDO; 1078 1079 /* Write command <01> */ 1080 bits[clk_idx++] = MII_MDOE; 1081 bits[clk_idx++] = MII_MDOE | MII_MDO; 1082 1083 /* Output the PHY address, msb first */ 1084 mask = (byte) 0x10; 1085 for (i = 0; i < 5; ++i) { 1086 if (phyaddr & mask) 1087 bits[clk_idx++] = MII_MDOE | MII_MDO; 1088 else 1089 bits[clk_idx++] = MII_MDOE; 1090 1091 /* Shift to next lowest bit */ 1092 mask >>= 1; 1093 } 1094 1095 /* Output the phy register number, msb first */ 1096 mask = (byte) 0x10; 1097 for (i = 0; i < 5; ++i) { 1098 if (phyreg & mask) 1099 bits[clk_idx++] = MII_MDOE | MII_MDO; 1100 else 1101 bits[clk_idx++] = MII_MDOE; 1102 1103 /* Shift to next lowest bit */ 1104 mask >>= 1; 1105 } 1106 1107 /* Tristate and turnaround (2 bit times) */ 1108 bits[clk_idx++] = 0; 1109 bits[clk_idx++] = 0; 1110 1111 /* Write out 16 bits of data, msb first */ 1112 mask = 0x8000; 1113 for (i = 0; i < 16; ++i) { 1114 if (phydata & mask) 1115 bits[clk_idx++] = MII_MDOE | MII_MDO; 1116 else 1117 bits[clk_idx++] = MII_MDOE; 1118 1119 /* Shift to next lowest bit */ 1120 mask >>= 1; 1121 } 1122 1123 /* Final clock bit (tristate) */ 1124 bits[clk_idx++] = 0; 1125 1126 /* Save the current bank */ 1127 oldBank = SMC_inw (dev, BANK_SELECT); 1128 1129 /* Select bank 3 */ 1130 SMC_SELECT_BANK (dev, 3); 1131 1132 /* Get the current MII register value */ 1133 mii_reg = SMC_inw (dev, MII_REG); 1134 1135 /* Turn off all MII Interface bits */ 1136 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); 1137 1138 /* Clock all cycles */ 1139 for (i = 0; i < sizeof bits; ++i) { 1140 /* Clock Low - output data */ 1141 SMC_outw (dev, mii_reg | bits[i], MII_REG); 1142 udelay (SMC_PHY_CLOCK_DELAY); 1143 1144 1145 /* Clock Hi - input data */ 1146 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); 1147 udelay (SMC_PHY_CLOCK_DELAY); 1148 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; 1149 } 1150 1151 /* Return to idle state */ 1152 /* Set clock to low, data to low, and output tristated */ 1153 SMC_outw (dev, mii_reg, MII_REG); 1154 udelay (SMC_PHY_CLOCK_DELAY); 1155 1156 /* Restore original bank select */ 1157 SMC_SELECT_BANK (dev, oldBank); 1158 1159 #if (SMC_DEBUG > 2 ) 1160 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", 1161 phyaddr, phyreg, phydata); 1162 smc_dump_mii_stream (bits, sizeof bits); 1163 #endif 1164 } 1165 #endif /* !CONFIG_SMC91111_EXT_PHY */ 1166 1167 1168 /*------------------------------------------------------------ 1169 . Configures the specified PHY using Autonegotiation. Calls 1170 . smc_phy_fixed() if the user has requested a certain config. 1171 .-------------------------------------------------------------*/ 1172 #ifndef CONFIG_SMC91111_EXT_PHY 1173 static void smc_phy_configure (struct eth_device *dev) 1174 { 1175 int timeout; 1176 word my_phy_caps; /* My PHY capabilities */ 1177 word my_ad_caps; /* My Advertised capabilities */ 1178 word status = 0; /*;my status = 0 */ 1179 1180 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); 1181 1182 /* Reset the PHY, setting all other bits to zero */ 1183 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); 1184 1185 /* Wait for the reset to complete, or time out */ 1186 timeout = 6; /* Wait up to 3 seconds */ 1187 while (timeout--) { 1188 if (!(smc_read_phy_register (dev, PHY_CNTL_REG) 1189 & PHY_CNTL_RST)) { 1190 /* reset complete */ 1191 break; 1192 } 1193 1194 mdelay(500); /* wait 500 millisecs */ 1195 } 1196 1197 if (timeout < 1) { 1198 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); 1199 goto smc_phy_configure_exit; 1200 } 1201 1202 /* Read PHY Register 18, Status Output */ 1203 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ 1204 1205 /* Enable PHY Interrupts (for register 18) */ 1206 /* Interrupts listed here are disabled */ 1207 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); 1208 1209 /* Configure the Receive/Phy Control register */ 1210 SMC_SELECT_BANK (dev, 0); 1211 SMC_outw (dev, RPC_DEFAULT, RPC_REG); 1212 1213 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ 1214 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); 1215 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ 1216 1217 if (my_phy_caps & PHY_STAT_CAP_T4) 1218 my_ad_caps |= PHY_AD_T4; 1219 1220 if (my_phy_caps & PHY_STAT_CAP_TXF) 1221 my_ad_caps |= PHY_AD_TX_FDX; 1222 1223 if (my_phy_caps & PHY_STAT_CAP_TXH) 1224 my_ad_caps |= PHY_AD_TX_HDX; 1225 1226 if (my_phy_caps & PHY_STAT_CAP_TF) 1227 my_ad_caps |= PHY_AD_10_FDX; 1228 1229 if (my_phy_caps & PHY_STAT_CAP_TH) 1230 my_ad_caps |= PHY_AD_10_HDX; 1231 1232 /* Update our Auto-Neg Advertisement Register */ 1233 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); 1234 1235 /* Read the register back. Without this, it appears that when */ 1236 /* auto-negotiation is restarted, sometimes it isn't ready and */ 1237 /* the link does not come up. */ 1238 smc_read_phy_register(dev, PHY_AD_REG); 1239 1240 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); 1241 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); 1242 1243 /* Restart auto-negotiation process in order to advertise my caps */ 1244 smc_write_phy_register (dev, PHY_CNTL_REG, 1245 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); 1246 1247 /* Wait for the auto-negotiation to complete. This may take from */ 1248 /* 2 to 3 seconds. */ 1249 /* Wait for the reset to complete, or time out */ 1250 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; 1251 while (timeout--) { 1252 1253 status = smc_read_phy_register (dev, PHY_STAT_REG); 1254 if (status & PHY_STAT_ANEG_ACK) { 1255 /* auto-negotiate complete */ 1256 break; 1257 } 1258 1259 mdelay(500); /* wait 500 millisecs */ 1260 1261 /* Restart auto-negotiation if remote fault */ 1262 if (status & PHY_STAT_REM_FLT) { 1263 printf ("%s: PHY remote fault detected\n", 1264 SMC_DEV_NAME); 1265 1266 /* Restart auto-negotiation */ 1267 printf ("%s: PHY restarting auto-negotiation\n", 1268 SMC_DEV_NAME); 1269 smc_write_phy_register (dev, PHY_CNTL_REG, 1270 PHY_CNTL_ANEG_EN | 1271 PHY_CNTL_ANEG_RST | 1272 PHY_CNTL_SPEED | 1273 PHY_CNTL_DPLX); 1274 } 1275 } 1276 1277 if (timeout < 1) { 1278 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); 1279 } 1280 1281 /* Fail if we detected an auto-negotiate remote fault */ 1282 if (status & PHY_STAT_REM_FLT) { 1283 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); 1284 } 1285 1286 /* Re-Configure the Receive/Phy Control register */ 1287 SMC_outw (dev, RPC_DEFAULT, RPC_REG); 1288 1289 smc_phy_configure_exit: ; 1290 1291 } 1292 #endif /* !CONFIG_SMC91111_EXT_PHY */ 1293 1294 1295 #if SMC_DEBUG > 2 1296 static void print_packet( byte * buf, int length ) 1297 { 1298 int i; 1299 int remainder; 1300 int lines; 1301 1302 printf("Packet of length %d \n", length ); 1303 1304 #if SMC_DEBUG > 3 1305 lines = length / 16; 1306 remainder = length % 16; 1307 1308 for ( i = 0; i < lines ; i ++ ) { 1309 int cur; 1310 1311 for ( cur = 0; cur < 8; cur ++ ) { 1312 byte a, b; 1313 1314 a = *(buf ++ ); 1315 b = *(buf ++ ); 1316 printf("%02x%02x ", a, b ); 1317 } 1318 printf("\n"); 1319 } 1320 for ( i = 0; i < remainder/2 ; i++ ) { 1321 byte a, b; 1322 1323 a = *(buf ++ ); 1324 b = *(buf ++ ); 1325 printf("%02x%02x ", a, b ); 1326 } 1327 printf("\n"); 1328 #endif 1329 } 1330 #endif 1331 1332 int smc91111_initialize(u8 dev_num, int base_addr) 1333 { 1334 struct smc91111_priv *priv; 1335 struct eth_device *dev; 1336 int i; 1337 1338 priv = malloc(sizeof(*priv)); 1339 if (!priv) 1340 return 0; 1341 dev = malloc(sizeof(*dev)); 1342 if (!dev) { 1343 free(priv); 1344 return 0; 1345 } 1346 1347 memset(dev, 0, sizeof(*dev)); 1348 priv->dev_num = dev_num; 1349 dev->priv = priv; 1350 dev->iobase = base_addr; 1351 1352 swap_to(ETHERNET); 1353 SMC_SELECT_BANK(dev, 1); 1354 for (i = 0; i < 6; ++i) 1355 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); 1356 swap_to(FLASH); 1357 1358 dev->init = smc_init; 1359 dev->halt = smc_halt; 1360 dev->send = smc_send; 1361 dev->recv = smc_rcv; 1362 dev->write_hwaddr = smc_write_hwaddr; 1363 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); 1364 1365 eth_register(dev); 1366 return 0; 1367 } 1368