1 /*------------------------------------------------------------------------ 2 . smc91111.c 3 . This is a driver for SMSC's 91C111 single-chip Ethernet device. 4 . 5 . (C) Copyright 2002 6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 . Rolf Offermanns <rof@sysgo.de> 8 . 9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 10 . Developed by Simple Network Magic Corporation (SNMC) 11 . Copyright (C) 1996 by Erik Stahlman (ES) 12 . 13 . This program is free software; you can redistribute it and/or modify 14 . it under the terms of the GNU General Public License as published by 15 . the Free Software Foundation; either version 2 of the License, or 16 . (at your option) any later version. 17 . 18 . This program is distributed in the hope that it will be useful, 19 . but WITHOUT ANY WARRANTY; without even the implied warranty of 20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 . GNU General Public License for more details. 22 . 23 . You should have received a copy of the GNU General Public License 24 . along with this program; if not, write to the Free Software 25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 . 27 . Information contained in this file was obtained from the LAN91C111 28 . manual from SMC. To get a copy, if you really want one, you can find 29 . information under www.smsc.com. 30 . 31 . 32 . "Features" of the SMC chip: 33 . Integrated PHY/MAC for 10/100BaseT Operation 34 . Supports internal and external MII 35 . Integrated 8K packet memory 36 . EEPROM interface for configuration 37 . 38 . Arguments: 39 . io = for the base address 40 . irq = for the IRQ 41 . 42 . author: 43 . Erik Stahlman ( erik@vt.edu ) 44 . Daris A Nevil ( dnevil@snmc.com ) 45 . 46 . 47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) 48 . 49 . Sources: 50 . o SMSC LAN91C111 databook (www.smsc.com) 51 . o smc9194.c by Erik Stahlman 52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) 53 . 54 . History: 55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. 56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110 57 . 07/25/01 Woojung Huh Modify for ADS Bitsy 58 . 04/25/01 Daris A Nevil Initial public release through SMSC 59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 60 ----------------------------------------------------------------------------*/ 61 62 #include <common.h> 63 #include <command.h> 64 #include <config.h> 65 #include <malloc.h> 66 #include "smc91111.h" 67 #include <net.h> 68 69 /* Use power-down feature of the chip */ 70 #define POWER_DOWN 0 71 72 #define NO_AUTOPROBE 73 74 #define SMC_DEBUG 0 75 76 #if SMC_DEBUG > 1 77 static const char version[] = 78 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; 79 #endif 80 81 /* Autonegotiation timeout in seconds */ 82 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT 83 #define CONFIG_SMC_AUTONEG_TIMEOUT 10 84 #endif 85 86 /*------------------------------------------------------------------------ 87 . 88 . Configuration options, for the experienced user to change. 89 . 90 -------------------------------------------------------------------------*/ 91 92 /* 93 . Wait time for memory to be free. This probably shouldn't be 94 . tuned that much, as waiting for this means nothing else happens 95 . in the system 96 */ 97 #define MEMORY_WAIT_TIME 16 98 99 100 #if (SMC_DEBUG > 2 ) 101 #define PRINTK3(args...) printf(args) 102 #else 103 #define PRINTK3(args...) 104 #endif 105 106 #if SMC_DEBUG > 1 107 #define PRINTK2(args...) printf(args) 108 #else 109 #define PRINTK2(args...) 110 #endif 111 112 #ifdef SMC_DEBUG 113 #define PRINTK(args...) printf(args) 114 #else 115 #define PRINTK(args...) 116 #endif 117 118 119 /*------------------------------------------------------------------------ 120 . 121 . The internal workings of the driver. If you are changing anything 122 . here with the SMC stuff, you should have the datasheet and know 123 . what you are doing. 124 . 125 -------------------------------------------------------------------------*/ 126 127 /* Memory sizing constant */ 128 #define LAN91C111_MEMORY_MULTIPLIER (1024*2) 129 130 #ifndef CONFIG_SMC91111_BASE 131 #error "SMC91111 Base address must be passed to initialization funciton" 132 /* #define CONFIG_SMC91111_BASE 0x20000300 */ 133 #endif 134 135 #define SMC_DEV_NAME "SMC91111" 136 #define SMC_PHY_ADDR 0x0000 137 #define SMC_ALLOC_MAX_TRY 5 138 #define SMC_TX_TIMEOUT 30 139 140 #define SMC_PHY_CLOCK_DELAY 1000 141 142 #define ETH_ZLEN 60 143 144 #ifdef CONFIG_SMC_USE_32_BIT 145 #define USE_32_BIT 1 146 #else 147 #undef USE_32_BIT 148 #endif 149 150 #ifdef SHARED_RESOURCES 151 extern void swap_to(int device_id); 152 #else 153 # define swap_to(x) 154 #endif 155 156 #ifndef CONFIG_SMC91111_EXT_PHY 157 static void smc_phy_configure(struct eth_device *dev); 158 #endif /* !CONFIG_SMC91111_EXT_PHY */ 159 160 /* 161 ------------------------------------------------------------ 162 . 163 . Internal routines 164 . 165 ------------------------------------------------------------ 166 */ 167 168 #ifdef CONFIG_SMC_USE_IOFUNCS 169 /* 170 * input and output functions 171 * 172 * Implemented due to inx,outx macros accessing the device improperly 173 * and putting the device into an unkown state. 174 * 175 * For instance, on Sharp LPD7A400 SDK, affects were chip memory 176 * could not be free'd (hence the alloc failures), duplicate packets, 177 * packets being corrupt (shifted) on the wire, etc. Switching to the 178 * inx,outx functions fixed this problem. 179 */ 180 181 #define barrier() __asm__ __volatile__("": : :"memory") 182 183 static inline word SMC_inw(struct eth_device *dev, dword offset) 184 { 185 word v; 186 v = *((volatile word*)(dev->iobase + offset)); 187 barrier(); *(volatile u32*)(0xc0000000); 188 return v; 189 } 190 191 static inline void SMC_outw(struct eth_device *dev, word value, dword offset) 192 { 193 *((volatile word*)(dev->iobase + offset)) = value; 194 barrier(); *(volatile u32*)(0xc0000000); 195 } 196 197 static inline byte SMC_inb(struct eth_device *dev, dword offset) 198 { 199 word _w; 200 201 _w = SMC_inw(dev, offset & ~((dword)1)); 202 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); 203 } 204 205 static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) 206 { 207 word _w; 208 209 _w = SMC_inw(dev, offset & ~((dword)1)); 210 if (offset & 1) 211 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = 212 (value<<8) | (_w & 0x00ff); 213 else 214 *((volatile word*)(dev->iobase + offset)) = 215 value | (_w & 0xff00); 216 } 217 218 static inline void SMC_insw(struct eth_device *dev, dword offset, 219 volatile uchar* buf, dword len) 220 { 221 volatile word *p = (volatile word *)buf; 222 223 while (len-- > 0) { 224 *p++ = SMC_inw(dev, offset); 225 barrier(); 226 *((volatile u32*)(0xc0000000)); 227 } 228 } 229 230 static inline void SMC_outsw(struct eth_device *dev, dword offset, 231 uchar* buf, dword len) 232 { 233 volatile word *p = (volatile word *)buf; 234 235 while (len-- > 0) { 236 SMC_outw(dev, *p++, offset); 237 barrier(); 238 *(volatile u32*)(0xc0000000); 239 } 240 } 241 #endif /* CONFIG_SMC_USE_IOFUNCS */ 242 243 /* 244 . A rather simple routine to print out a packet for debugging purposes. 245 */ 246 #if SMC_DEBUG > 2 247 static void print_packet( byte *, int ); 248 #endif 249 250 #define tx_done(dev) 1 251 252 static int poll4int (struct eth_device *dev, byte mask, int timeout) 253 { 254 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; 255 int is_timeout = 0; 256 word old_bank = SMC_inw (dev, BSR_REG); 257 258 PRINTK2 ("Polling...\n"); 259 SMC_SELECT_BANK (dev, 2); 260 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { 261 if (get_timer (0) >= tmo) { 262 is_timeout = 1; 263 break; 264 } 265 } 266 267 /* restore old bank selection */ 268 SMC_SELECT_BANK (dev, old_bank); 269 270 if (is_timeout) 271 return 1; 272 else 273 return 0; 274 } 275 276 /* Only one release command at a time, please */ 277 static inline void smc_wait_mmu_release_complete (struct eth_device *dev) 278 { 279 int count = 0; 280 281 /* assume bank 2 selected */ 282 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { 283 udelay (1); /* Wait until not busy */ 284 if (++count > 200) 285 break; 286 } 287 } 288 289 /* 290 . Function: smc_reset( void ) 291 . Purpose: 292 . This sets the SMC91111 chip to its normal state, hopefully from whatever 293 . mess that any other DOS driver has put it in. 294 . 295 . Maybe I should reset more registers to defaults in here? SOFTRST should 296 . do that for me. 297 . 298 . Method: 299 . 1. send a SOFT RESET 300 . 2. wait for it to finish 301 . 3. enable autorelease mode 302 . 4. reset the memory management unit 303 . 5. clear all interrupts 304 . 305 */ 306 static void smc_reset (struct eth_device *dev) 307 { 308 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); 309 310 /* This resets the registers mostly to defaults, but doesn't 311 affect EEPROM. That seems unnecessary */ 312 SMC_SELECT_BANK (dev, 0); 313 SMC_outw (dev, RCR_SOFTRST, RCR_REG); 314 315 /* Setup the Configuration Register */ 316 /* This is necessary because the CONFIG_REG is not affected */ 317 /* by a soft reset */ 318 319 SMC_SELECT_BANK (dev, 1); 320 #if defined(CONFIG_SMC91111_EXT_PHY) 321 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); 322 #else 323 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); 324 #endif 325 326 327 /* Release from possible power-down state */ 328 /* Configuration register is not affected by Soft Reset */ 329 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, 330 CONFIG_REG); 331 332 SMC_SELECT_BANK (dev, 0); 333 334 /* this should pause enough for the chip to be happy */ 335 udelay (10); 336 337 /* Disable transmit and receive functionality */ 338 SMC_outw (dev, RCR_CLEAR, RCR_REG); 339 SMC_outw (dev, TCR_CLEAR, TCR_REG); 340 341 /* set the control register */ 342 SMC_SELECT_BANK (dev, 1); 343 SMC_outw (dev, CTL_DEFAULT, CTL_REG); 344 345 /* Reset the MMU */ 346 SMC_SELECT_BANK (dev, 2); 347 smc_wait_mmu_release_complete (dev); 348 SMC_outw (dev, MC_RESET, MMU_CMD_REG); 349 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) 350 udelay (1); /* Wait until not busy */ 351 352 /* Note: It doesn't seem that waiting for the MMU busy is needed here, 353 but this is a place where future chipsets _COULD_ break. Be wary 354 of issuing another MMU command right after this */ 355 356 /* Disable all interrupts */ 357 SMC_outb (dev, 0, IM_REG); 358 } 359 360 /* 361 . Function: smc_enable 362 . Purpose: let the chip talk to the outside work 363 . Method: 364 . 1. Enable the transmitter 365 . 2. Enable the receiver 366 . 3. Enable interrupts 367 */ 368 static void smc_enable(struct eth_device *dev) 369 { 370 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); 371 SMC_SELECT_BANK( dev, 0 ); 372 /* see the header file for options in TCR/RCR DEFAULT*/ 373 SMC_outw( dev, TCR_DEFAULT, TCR_REG ); 374 SMC_outw( dev, RCR_DEFAULT, RCR_REG ); 375 376 /* clear MII_DIS */ 377 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ 378 } 379 380 /* 381 . Function: smc_halt 382 . Purpose: closes down the SMC91xxx chip. 383 . Method: 384 . 1. zero the interrupt mask 385 . 2. clear the enable receive flag 386 . 3. clear the enable xmit flags 387 . 388 . TODO: 389 . (1) maybe utilize power down mode. 390 . Why not yet? Because while the chip will go into power down mode, 391 . the manual says that it will wake up in response to any I/O requests 392 . in the register space. Empirical results do not show this working. 393 */ 394 static void smc_halt(struct eth_device *dev) 395 { 396 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); 397 398 /* no more interrupts for me */ 399 SMC_SELECT_BANK( dev, 2 ); 400 SMC_outb( dev, 0, IM_REG ); 401 402 /* and tell the card to stay away from that nasty outside world */ 403 SMC_SELECT_BANK( dev, 0 ); 404 SMC_outb( dev, RCR_CLEAR, RCR_REG ); 405 SMC_outb( dev, TCR_CLEAR, TCR_REG ); 406 407 swap_to(FLASH); 408 } 409 410 411 /* 412 . Function: smc_send(struct net_device * ) 413 . Purpose: 414 . This sends the actual packet to the SMC9xxx chip. 415 . 416 . Algorithm: 417 . First, see if a saved_skb is available. 418 . ( this should NOT be called if there is no 'saved_skb' 419 . Now, find the packet number that the chip allocated 420 . Point the data pointers at it in memory 421 . Set the length word in the chip's memory 422 . Dump the packet to chip memory 423 . Check if a last byte is needed ( odd length packet ) 424 . if so, set the control flag right 425 . Tell the card to send it 426 . Enable the transmit interrupt, so I know if it failed 427 . Free the kernel data if I actually sent it. 428 */ 429 static int smc_send(struct eth_device *dev, volatile void *packet, 430 int packet_length) 431 { 432 byte packet_no; 433 byte *buf; 434 int length; 435 int numPages; 436 int try = 0; 437 int time_out; 438 byte status; 439 byte saved_pnr; 440 word saved_ptr; 441 442 /* save PTR and PNR registers before manipulation */ 443 SMC_SELECT_BANK (dev, 2); 444 saved_pnr = SMC_inb( dev, PN_REG ); 445 saved_ptr = SMC_inw( dev, PTR_REG ); 446 447 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); 448 449 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; 450 451 /* allocate memory 452 ** The MMU wants the number of pages to be the number of 256 bytes 453 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) 454 ** 455 ** The 91C111 ignores the size bits, but the code is left intact 456 ** for backwards and future compatibility. 457 ** 458 ** Pkt size for allocating is data length +6 (for additional status 459 ** words, length and ctl!) 460 ** 461 ** If odd size then last byte is included in this header. 462 */ 463 numPages = ((length & 0xfffe) + 6); 464 numPages >>= 8; /* Divide by 256 */ 465 466 if (numPages > 7) { 467 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); 468 return 0; 469 } 470 471 /* now, try to allocate the memory */ 472 SMC_SELECT_BANK (dev, 2); 473 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); 474 475 /* FIXME: the ALLOC_INT bit never gets set * 476 * so the following will always give a * 477 * memory allocation error. * 478 * same code works in armboot though * 479 * -ro 480 */ 481 482 again: 483 try++; 484 time_out = MEMORY_WAIT_TIME; 485 do { 486 status = SMC_inb (dev, SMC91111_INT_REG); 487 if (status & IM_ALLOC_INT) { 488 /* acknowledge the interrupt */ 489 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); 490 break; 491 } 492 } while (--time_out); 493 494 if (!time_out) { 495 PRINTK2 ("%s: memory allocation, try %d failed ...\n", 496 SMC_DEV_NAME, try); 497 if (try < SMC_ALLOC_MAX_TRY) 498 goto again; 499 else 500 return 0; 501 } 502 503 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", 504 SMC_DEV_NAME, try); 505 506 buf = (byte *) packet; 507 508 /* If I get here, I _know_ there is a packet slot waiting for me */ 509 packet_no = SMC_inb (dev, AR_REG); 510 if (packet_no & AR_FAILED) { 511 /* or isn't there? BAD CHIP! */ 512 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); 513 return 0; 514 } 515 516 /* we have a packet address, so tell the card to use it */ 517 #ifndef CONFIG_XAENIAX 518 SMC_outb (dev, packet_no, PN_REG); 519 #else 520 /* On Xaeniax board, we can't use SMC_outb here because that way 521 * the Allocate MMU command will end up written to the command register 522 * as well, which will lead to a problem. 523 */ 524 SMC_outl (dev, packet_no << 16, 0); 525 #endif 526 /* do not write new ptr value if Write data fifo not empty */ 527 while ( saved_ptr & PTR_NOTEMPTY ) 528 printf ("Write data fifo not empty!\n"); 529 530 /* point to the beginning of the packet */ 531 SMC_outw (dev, PTR_AUTOINC, PTR_REG); 532 533 PRINTK3 ("%s: Trying to xmit packet of length %x\n", 534 SMC_DEV_NAME, length); 535 536 #if SMC_DEBUG > 2 537 printf ("Transmitting Packet\n"); 538 print_packet (buf, length); 539 #endif 540 541 /* send the packet length ( +6 for status, length and ctl byte ) 542 and the status word ( set to zeros ) */ 543 #ifdef USE_32_BIT 544 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); 545 #else 546 SMC_outw (dev, 0, SMC91111_DATA_REG); 547 /* send the packet length ( +6 for status words, length, and ctl */ 548 SMC_outw (dev, (length + 6), SMC91111_DATA_REG); 549 #endif 550 551 /* send the actual data 552 . I _think_ it's faster to send the longs first, and then 553 . mop up by sending the last word. It depends heavily 554 . on alignment, at least on the 486. Maybe it would be 555 . a good idea to check which is optimal? But that could take 556 . almost as much time as is saved? 557 */ 558 #ifdef USE_32_BIT 559 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); 560 #ifndef CONFIG_XAENIAX 561 if (length & 0x2) 562 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), 563 SMC91111_DATA_REG); 564 #else 565 /* On XANEIAX, we can only use 32-bit writes, so we need to handle 566 * unaligned tail part specially. The standard code doesn't work. 567 */ 568 if ((length & 3) == 3) { 569 u16 * ptr = (u16*) &buf[length-3]; 570 SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), 571 SMC91111_DATA_REG); 572 } else if ((length & 2) == 2) { 573 u16 * ptr = (u16*) &buf[length-2]; 574 SMC_outl(dev, *ptr, SMC91111_DATA_REG); 575 } else if (length & 1) { 576 SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); 577 } else { 578 SMC_outl(dev, 0, SMC91111_DATA_REG); 579 } 580 #endif 581 #else 582 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); 583 #endif /* USE_32_BIT */ 584 585 #ifndef CONFIG_XAENIAX 586 /* Send the last byte, if there is one. */ 587 if ((length & 1) == 0) { 588 SMC_outw (dev, 0, SMC91111_DATA_REG); 589 } else { 590 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); 591 } 592 #endif 593 594 /* and let the chipset deal with it */ 595 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); 596 597 /* poll for TX INT */ 598 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ 599 /* poll for TX_EMPTY INT - autorelease enabled */ 600 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { 601 /* sending failed */ 602 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); 603 604 /* release packet */ 605 /* no need to release, MMU does that now */ 606 #ifdef CONFIG_XAENIAX 607 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); 608 #endif 609 610 /* wait for MMU getting ready (low) */ 611 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { 612 udelay (10); 613 } 614 615 PRINTK2 ("MMU ready\n"); 616 617 618 return 0; 619 } else { 620 /* ack. int */ 621 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); 622 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ 623 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, 624 length); 625 626 /* release packet */ 627 /* no need to release, MMU does that now */ 628 #ifdef CONFIG_XAENIAX 629 SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); 630 #endif 631 632 /* wait for MMU getting ready (low) */ 633 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { 634 udelay (10); 635 } 636 637 PRINTK2 ("MMU ready\n"); 638 639 640 } 641 642 /* restore previously saved registers */ 643 #ifndef CONFIG_XAENIAX 644 SMC_outb( dev, saved_pnr, PN_REG ); 645 #else 646 /* On Xaeniax board, we can't use SMC_outb here because that way 647 * the Allocate MMU command will end up written to the command register 648 * as well, which will lead to a problem. 649 */ 650 SMC_outl(dev, saved_pnr << 16, 0); 651 #endif 652 SMC_outw( dev, saved_ptr, PTR_REG ); 653 654 return length; 655 } 656 657 static int smc_write_hwaddr(struct eth_device *dev) 658 { 659 int i; 660 661 swap_to(ETHERNET); 662 SMC_SELECT_BANK (dev, 1); 663 #ifdef USE_32_BIT 664 for (i = 0; i < 6; i += 2) { 665 word address; 666 667 address = dev->enetaddr[i + 1] << 8; 668 address |= dev->enetaddr[i]; 669 SMC_outw(dev, address, (ADDR0_REG + i)); 670 } 671 #else 672 for (i = 0; i < 6; i++) 673 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); 674 #endif 675 swap_to(FLASH); 676 return 0; 677 } 678 679 /* 680 * Open and Initialize the board 681 * 682 * Set up everything, reset the card, etc .. 683 * 684 */ 685 static int smc_init(struct eth_device *dev, bd_t *bd) 686 { 687 swap_to(ETHERNET); 688 689 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); 690 691 /* reset the hardware */ 692 smc_reset (dev); 693 smc_enable (dev); 694 695 /* Configure the PHY */ 696 #ifndef CONFIG_SMC91111_EXT_PHY 697 smc_phy_configure (dev); 698 #endif 699 700 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ 701 /* SMC_SELECT_BANK(dev, 0); */ 702 /* SMC_outw(dev, 0, RPC_REG); */ 703 704 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); 705 706 return 0; 707 } 708 709 /*------------------------------------------------------------- 710 . 711 . smc_rcv - receive a packet from the card 712 . 713 . There is ( at least ) a packet waiting to be read from 714 . chip-memory. 715 . 716 . o Read the status 717 . o If an error, record it 718 . o otherwise, read in the packet 719 -------------------------------------------------------------- 720 */ 721 static int smc_rcv(struct eth_device *dev) 722 { 723 int packet_number; 724 word status; 725 word packet_length; 726 int is_error = 0; 727 #ifdef USE_32_BIT 728 dword stat_len; 729 #endif 730 byte saved_pnr; 731 word saved_ptr; 732 733 SMC_SELECT_BANK(dev, 2); 734 /* save PTR and PTR registers */ 735 saved_pnr = SMC_inb( dev, PN_REG ); 736 saved_ptr = SMC_inw( dev, PTR_REG ); 737 738 packet_number = SMC_inw( dev, RXFIFO_REG ); 739 740 if ( packet_number & RXFIFO_REMPTY ) { 741 742 return 0; 743 } 744 745 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); 746 /* start reading from the start of the packet */ 747 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); 748 749 /* First two words are status and packet_length */ 750 #ifdef USE_32_BIT 751 stat_len = SMC_inl(dev, SMC91111_DATA_REG); 752 status = stat_len & 0xffff; 753 packet_length = stat_len >> 16; 754 #else 755 status = SMC_inw( dev, SMC91111_DATA_REG ); 756 packet_length = SMC_inw( dev, SMC91111_DATA_REG ); 757 #endif 758 759 packet_length &= 0x07ff; /* mask off top bits */ 760 761 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); 762 763 if ( !(status & RS_ERRORS ) ){ 764 /* Adjust for having already read the first two words */ 765 packet_length -= 4; /*4; */ 766 767 768 /* set odd length for bug in LAN91C111, */ 769 /* which never sets RS_ODDFRAME */ 770 /* TODO ? */ 771 772 773 #ifdef USE_32_BIT 774 PRINTK3(" Reading %d dwords (and %d bytes) \n", 775 packet_length >> 2, packet_length & 3 ); 776 /* QUESTION: Like in the TX routine, do I want 777 to send the DWORDs or the bytes first, or some 778 mixture. A mixture might improve already slow PIO 779 performance */ 780 SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0], 781 packet_length >> 2 ); 782 /* read the left over bytes */ 783 if (packet_length & 3) { 784 int i; 785 786 byte *tail = (byte *)(NetRxPackets[0] + 787 (packet_length & ~3)); 788 dword leftover = SMC_inl(dev, SMC91111_DATA_REG); 789 for (i=0; i<(packet_length & 3); i++) 790 *tail++ = (byte) (leftover >> (8*i)) & 0xff; 791 } 792 #else 793 PRINTK3(" Reading %d words and %d byte(s) \n", 794 (packet_length >> 1 ), packet_length & 1 ); 795 SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0], 796 packet_length >> 1); 797 798 #endif /* USE_32_BIT */ 799 800 #if SMC_DEBUG > 2 801 printf("Receiving Packet\n"); 802 print_packet( NetRxPackets[0], packet_length ); 803 #endif 804 } else { 805 /* error ... */ 806 /* TODO ? */ 807 is_error = 1; 808 } 809 810 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) 811 udelay(1); /* Wait until not busy */ 812 813 /* error or good, tell the card to get rid of this packet */ 814 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); 815 816 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) 817 udelay(1); /* Wait until not busy */ 818 819 /* restore saved registers */ 820 #ifndef CONFIG_XAENIAX 821 SMC_outb( dev, saved_pnr, PN_REG ); 822 #else 823 /* On Xaeniax board, we can't use SMC_outb here because that way 824 * the Allocate MMU command will end up written to the command register 825 * as well, which will lead to a problem. 826 */ 827 SMC_outl( dev, saved_pnr << 16, 0); 828 #endif 829 SMC_outw( dev, saved_ptr, PTR_REG ); 830 831 if (!is_error) { 832 /* Pass the packet up to the protocol layers. */ 833 NetReceive(NetRxPackets[0], packet_length); 834 return packet_length; 835 } else { 836 return 0; 837 } 838 839 } 840 841 842 #if 0 843 /*------------------------------------------------------------ 844 . Modify a bit in the LAN91C111 register set 845 .-------------------------------------------------------------*/ 846 static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, 847 unsigned int bit, int val) 848 { 849 word regval; 850 851 SMC_SELECT_BANK( dev, bank ); 852 853 regval = SMC_inw( dev, reg ); 854 if (val) 855 regval |= bit; 856 else 857 regval &= ~bit; 858 859 SMC_outw( dev, regval, 0 ); 860 return(regval); 861 } 862 863 864 /*------------------------------------------------------------ 865 . Retrieve a bit in the LAN91C111 register set 866 .-------------------------------------------------------------*/ 867 static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) 868 { 869 SMC_SELECT_BANK( dev, bank ); 870 if ( SMC_inw( dev, reg ) & bit) 871 return(1); 872 else 873 return(0); 874 } 875 876 877 /*------------------------------------------------------------ 878 . Modify a LAN91C111 register (word access only) 879 .-------------------------------------------------------------*/ 880 static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) 881 { 882 SMC_SELECT_BANK( dev, bank ); 883 SMC_outw( dev, val, reg ); 884 } 885 886 887 /*------------------------------------------------------------ 888 . Retrieve a LAN91C111 register (word access only) 889 .-------------------------------------------------------------*/ 890 static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) 891 { 892 SMC_SELECT_BANK( dev, bank ); 893 return(SMC_inw( dev, reg )); 894 } 895 896 #endif /* 0 */ 897 898 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ 899 900 #if (SMC_DEBUG > 2 ) 901 902 /*------------------------------------------------------------ 903 . Debugging function for viewing MII Management serial bitstream 904 .-------------------------------------------------------------*/ 905 static void smc_dump_mii_stream (byte * bits, int size) 906 { 907 int i; 908 909 printf ("BIT#:"); 910 for (i = 0; i < size; ++i) { 911 printf ("%d", i % 10); 912 } 913 914 printf ("\nMDOE:"); 915 for (i = 0; i < size; ++i) { 916 if (bits[i] & MII_MDOE) 917 printf ("1"); 918 else 919 printf ("0"); 920 } 921 922 printf ("\nMDO :"); 923 for (i = 0; i < size; ++i) { 924 if (bits[i] & MII_MDO) 925 printf ("1"); 926 else 927 printf ("0"); 928 } 929 930 printf ("\nMDI :"); 931 for (i = 0; i < size; ++i) { 932 if (bits[i] & MII_MDI) 933 printf ("1"); 934 else 935 printf ("0"); 936 } 937 938 printf ("\n"); 939 } 940 #endif 941 942 /*------------------------------------------------------------ 943 . Reads a register from the MII Management serial interface 944 .-------------------------------------------------------------*/ 945 #ifndef CONFIG_SMC91111_EXT_PHY 946 static word smc_read_phy_register (struct eth_device *dev, byte phyreg) 947 { 948 int oldBank; 949 int i; 950 byte mask; 951 word mii_reg; 952 byte bits[64]; 953 int clk_idx = 0; 954 int input_idx; 955 word phydata; 956 byte phyaddr = SMC_PHY_ADDR; 957 958 /* 32 consecutive ones on MDO to establish sync */ 959 for (i = 0; i < 32; ++i) 960 bits[clk_idx++] = MII_MDOE | MII_MDO; 961 962 /* Start code <01> */ 963 bits[clk_idx++] = MII_MDOE; 964 bits[clk_idx++] = MII_MDOE | MII_MDO; 965 966 /* Read command <10> */ 967 bits[clk_idx++] = MII_MDOE | MII_MDO; 968 bits[clk_idx++] = MII_MDOE; 969 970 /* Output the PHY address, msb first */ 971 mask = (byte) 0x10; 972 for (i = 0; i < 5; ++i) { 973 if (phyaddr & mask) 974 bits[clk_idx++] = MII_MDOE | MII_MDO; 975 else 976 bits[clk_idx++] = MII_MDOE; 977 978 /* Shift to next lowest bit */ 979 mask >>= 1; 980 } 981 982 /* Output the phy register number, msb first */ 983 mask = (byte) 0x10; 984 for (i = 0; i < 5; ++i) { 985 if (phyreg & mask) 986 bits[clk_idx++] = MII_MDOE | MII_MDO; 987 else 988 bits[clk_idx++] = MII_MDOE; 989 990 /* Shift to next lowest bit */ 991 mask >>= 1; 992 } 993 994 /* Tristate and turnaround (2 bit times) */ 995 bits[clk_idx++] = 0; 996 /*bits[clk_idx++] = 0; */ 997 998 /* Input starts at this bit time */ 999 input_idx = clk_idx; 1000 1001 /* Will input 16 bits */ 1002 for (i = 0; i < 16; ++i) 1003 bits[clk_idx++] = 0; 1004 1005 /* Final clock bit */ 1006 bits[clk_idx++] = 0; 1007 1008 /* Save the current bank */ 1009 oldBank = SMC_inw (dev, BANK_SELECT); 1010 1011 /* Select bank 3 */ 1012 SMC_SELECT_BANK (dev, 3); 1013 1014 /* Get the current MII register value */ 1015 mii_reg = SMC_inw (dev, MII_REG); 1016 1017 /* Turn off all MII Interface bits */ 1018 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); 1019 1020 /* Clock all 64 cycles */ 1021 for (i = 0; i < sizeof bits; ++i) { 1022 /* Clock Low - output data */ 1023 SMC_outw (dev, mii_reg | bits[i], MII_REG); 1024 udelay (SMC_PHY_CLOCK_DELAY); 1025 1026 1027 /* Clock Hi - input data */ 1028 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); 1029 udelay (SMC_PHY_CLOCK_DELAY); 1030 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; 1031 } 1032 1033 /* Return to idle state */ 1034 /* Set clock to low, data to low, and output tristated */ 1035 SMC_outw (dev, mii_reg, MII_REG); 1036 udelay (SMC_PHY_CLOCK_DELAY); 1037 1038 /* Restore original bank select */ 1039 SMC_SELECT_BANK (dev, oldBank); 1040 1041 /* Recover input data */ 1042 phydata = 0; 1043 for (i = 0; i < 16; ++i) { 1044 phydata <<= 1; 1045 1046 if (bits[input_idx++] & MII_MDI) 1047 phydata |= 0x0001; 1048 } 1049 1050 #if (SMC_DEBUG > 2 ) 1051 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", 1052 phyaddr, phyreg, phydata); 1053 smc_dump_mii_stream (bits, sizeof bits); 1054 #endif 1055 1056 return (phydata); 1057 } 1058 1059 1060 /*------------------------------------------------------------ 1061 . Writes a register to the MII Management serial interface 1062 .-------------------------------------------------------------*/ 1063 static void smc_write_phy_register (struct eth_device *dev, byte phyreg, 1064 word phydata) 1065 { 1066 int oldBank; 1067 int i; 1068 word mask; 1069 word mii_reg; 1070 byte bits[65]; 1071 int clk_idx = 0; 1072 byte phyaddr = SMC_PHY_ADDR; 1073 1074 /* 32 consecutive ones on MDO to establish sync */ 1075 for (i = 0; i < 32; ++i) 1076 bits[clk_idx++] = MII_MDOE | MII_MDO; 1077 1078 /* Start code <01> */ 1079 bits[clk_idx++] = MII_MDOE; 1080 bits[clk_idx++] = MII_MDOE | MII_MDO; 1081 1082 /* Write command <01> */ 1083 bits[clk_idx++] = MII_MDOE; 1084 bits[clk_idx++] = MII_MDOE | MII_MDO; 1085 1086 /* Output the PHY address, msb first */ 1087 mask = (byte) 0x10; 1088 for (i = 0; i < 5; ++i) { 1089 if (phyaddr & mask) 1090 bits[clk_idx++] = MII_MDOE | MII_MDO; 1091 else 1092 bits[clk_idx++] = MII_MDOE; 1093 1094 /* Shift to next lowest bit */ 1095 mask >>= 1; 1096 } 1097 1098 /* Output the phy register number, msb first */ 1099 mask = (byte) 0x10; 1100 for (i = 0; i < 5; ++i) { 1101 if (phyreg & mask) 1102 bits[clk_idx++] = MII_MDOE | MII_MDO; 1103 else 1104 bits[clk_idx++] = MII_MDOE; 1105 1106 /* Shift to next lowest bit */ 1107 mask >>= 1; 1108 } 1109 1110 /* Tristate and turnaround (2 bit times) */ 1111 bits[clk_idx++] = 0; 1112 bits[clk_idx++] = 0; 1113 1114 /* Write out 16 bits of data, msb first */ 1115 mask = 0x8000; 1116 for (i = 0; i < 16; ++i) { 1117 if (phydata & mask) 1118 bits[clk_idx++] = MII_MDOE | MII_MDO; 1119 else 1120 bits[clk_idx++] = MII_MDOE; 1121 1122 /* Shift to next lowest bit */ 1123 mask >>= 1; 1124 } 1125 1126 /* Final clock bit (tristate) */ 1127 bits[clk_idx++] = 0; 1128 1129 /* Save the current bank */ 1130 oldBank = SMC_inw (dev, BANK_SELECT); 1131 1132 /* Select bank 3 */ 1133 SMC_SELECT_BANK (dev, 3); 1134 1135 /* Get the current MII register value */ 1136 mii_reg = SMC_inw (dev, MII_REG); 1137 1138 /* Turn off all MII Interface bits */ 1139 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); 1140 1141 /* Clock all cycles */ 1142 for (i = 0; i < sizeof bits; ++i) { 1143 /* Clock Low - output data */ 1144 SMC_outw (dev, mii_reg | bits[i], MII_REG); 1145 udelay (SMC_PHY_CLOCK_DELAY); 1146 1147 1148 /* Clock Hi - input data */ 1149 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); 1150 udelay (SMC_PHY_CLOCK_DELAY); 1151 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; 1152 } 1153 1154 /* Return to idle state */ 1155 /* Set clock to low, data to low, and output tristated */ 1156 SMC_outw (dev, mii_reg, MII_REG); 1157 udelay (SMC_PHY_CLOCK_DELAY); 1158 1159 /* Restore original bank select */ 1160 SMC_SELECT_BANK (dev, oldBank); 1161 1162 #if (SMC_DEBUG > 2 ) 1163 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", 1164 phyaddr, phyreg, phydata); 1165 smc_dump_mii_stream (bits, sizeof bits); 1166 #endif 1167 } 1168 #endif /* !CONFIG_SMC91111_EXT_PHY */ 1169 1170 1171 /*------------------------------------------------------------ 1172 . Configures the specified PHY using Autonegotiation. Calls 1173 . smc_phy_fixed() if the user has requested a certain config. 1174 .-------------------------------------------------------------*/ 1175 #ifndef CONFIG_SMC91111_EXT_PHY 1176 static void smc_phy_configure (struct eth_device *dev) 1177 { 1178 int timeout; 1179 word my_phy_caps; /* My PHY capabilities */ 1180 word my_ad_caps; /* My Advertised capabilities */ 1181 word status = 0; /*;my status = 0 */ 1182 1183 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); 1184 1185 /* Reset the PHY, setting all other bits to zero */ 1186 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); 1187 1188 /* Wait for the reset to complete, or time out */ 1189 timeout = 6; /* Wait up to 3 seconds */ 1190 while (timeout--) { 1191 if (!(smc_read_phy_register (dev, PHY_CNTL_REG) 1192 & PHY_CNTL_RST)) { 1193 /* reset complete */ 1194 break; 1195 } 1196 1197 mdelay(500); /* wait 500 millisecs */ 1198 } 1199 1200 if (timeout < 1) { 1201 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); 1202 goto smc_phy_configure_exit; 1203 } 1204 1205 /* Read PHY Register 18, Status Output */ 1206 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ 1207 1208 /* Enable PHY Interrupts (for register 18) */ 1209 /* Interrupts listed here are disabled */ 1210 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); 1211 1212 /* Configure the Receive/Phy Control register */ 1213 SMC_SELECT_BANK (dev, 0); 1214 SMC_outw (dev, RPC_DEFAULT, RPC_REG); 1215 1216 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ 1217 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); 1218 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ 1219 1220 if (my_phy_caps & PHY_STAT_CAP_T4) 1221 my_ad_caps |= PHY_AD_T4; 1222 1223 if (my_phy_caps & PHY_STAT_CAP_TXF) 1224 my_ad_caps |= PHY_AD_TX_FDX; 1225 1226 if (my_phy_caps & PHY_STAT_CAP_TXH) 1227 my_ad_caps |= PHY_AD_TX_HDX; 1228 1229 if (my_phy_caps & PHY_STAT_CAP_TF) 1230 my_ad_caps |= PHY_AD_10_FDX; 1231 1232 if (my_phy_caps & PHY_STAT_CAP_TH) 1233 my_ad_caps |= PHY_AD_10_HDX; 1234 1235 /* Update our Auto-Neg Advertisement Register */ 1236 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); 1237 1238 /* Read the register back. Without this, it appears that when */ 1239 /* auto-negotiation is restarted, sometimes it isn't ready and */ 1240 /* the link does not come up. */ 1241 smc_read_phy_register(dev, PHY_AD_REG); 1242 1243 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); 1244 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); 1245 1246 /* Restart auto-negotiation process in order to advertise my caps */ 1247 smc_write_phy_register (dev, PHY_CNTL_REG, 1248 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); 1249 1250 /* Wait for the auto-negotiation to complete. This may take from */ 1251 /* 2 to 3 seconds. */ 1252 /* Wait for the reset to complete, or time out */ 1253 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; 1254 while (timeout--) { 1255 1256 status = smc_read_phy_register (dev, PHY_STAT_REG); 1257 if (status & PHY_STAT_ANEG_ACK) { 1258 /* auto-negotiate complete */ 1259 break; 1260 } 1261 1262 mdelay(500); /* wait 500 millisecs */ 1263 1264 /* Restart auto-negotiation if remote fault */ 1265 if (status & PHY_STAT_REM_FLT) { 1266 printf ("%s: PHY remote fault detected\n", 1267 SMC_DEV_NAME); 1268 1269 /* Restart auto-negotiation */ 1270 printf ("%s: PHY restarting auto-negotiation\n", 1271 SMC_DEV_NAME); 1272 smc_write_phy_register (dev, PHY_CNTL_REG, 1273 PHY_CNTL_ANEG_EN | 1274 PHY_CNTL_ANEG_RST | 1275 PHY_CNTL_SPEED | 1276 PHY_CNTL_DPLX); 1277 } 1278 } 1279 1280 if (timeout < 1) { 1281 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); 1282 } 1283 1284 /* Fail if we detected an auto-negotiate remote fault */ 1285 if (status & PHY_STAT_REM_FLT) { 1286 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); 1287 } 1288 1289 /* Re-Configure the Receive/Phy Control register */ 1290 SMC_outw (dev, RPC_DEFAULT, RPC_REG); 1291 1292 smc_phy_configure_exit: ; 1293 1294 } 1295 #endif /* !CONFIG_SMC91111_EXT_PHY */ 1296 1297 1298 #if SMC_DEBUG > 2 1299 static void print_packet( byte * buf, int length ) 1300 { 1301 int i; 1302 int remainder; 1303 int lines; 1304 1305 printf("Packet of length %d \n", length ); 1306 1307 #if SMC_DEBUG > 3 1308 lines = length / 16; 1309 remainder = length % 16; 1310 1311 for ( i = 0; i < lines ; i ++ ) { 1312 int cur; 1313 1314 for ( cur = 0; cur < 8; cur ++ ) { 1315 byte a, b; 1316 1317 a = *(buf ++ ); 1318 b = *(buf ++ ); 1319 printf("%02x%02x ", a, b ); 1320 } 1321 printf("\n"); 1322 } 1323 for ( i = 0; i < remainder/2 ; i++ ) { 1324 byte a, b; 1325 1326 a = *(buf ++ ); 1327 b = *(buf ++ ); 1328 printf("%02x%02x ", a, b ); 1329 } 1330 printf("\n"); 1331 #endif 1332 } 1333 #endif 1334 1335 int smc91111_initialize(u8 dev_num, int base_addr) 1336 { 1337 struct smc91111_priv *priv; 1338 struct eth_device *dev; 1339 int i; 1340 1341 priv = malloc(sizeof(*priv)); 1342 if (!priv) 1343 return 0; 1344 dev = malloc(sizeof(*dev)); 1345 if (!dev) { 1346 free(priv); 1347 return 0; 1348 } 1349 1350 memset(dev, 0, sizeof(*dev)); 1351 priv->dev_num = dev_num; 1352 dev->priv = priv; 1353 dev->iobase = base_addr; 1354 1355 swap_to(ETHERNET); 1356 SMC_SELECT_BANK(dev, 1); 1357 for (i = 0; i < 6; ++i) 1358 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); 1359 swap_to(FLASH); 1360 1361 dev->init = smc_init; 1362 dev->halt = smc_halt; 1363 dev->send = smc_send; 1364 dev->recv = smc_rcv; 1365 dev->write_hwaddr = smc_write_hwaddr; 1366 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); 1367 1368 eth_register(dev); 1369 return 0; 1370 } 1371