xref: /openbmc/u-boot/drivers/net/sh_eth.h (revision e0708fb5)
1 /*
2  * sh_eth.h - Driver for Renesas SuperH ethernet controler.
3  *
4  * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
5  * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #include <netdev.h>
12 #include <asm/types.h>
13 
14 #define SHETHER_NAME "sh_eth"
15 
16 #if defined(CONFIG_SH)
17 /* Malloc returns addresses in the P1 area (cacheable). However we need to
18    use area P2 (non-cacheable) */
19 #define ADDR_TO_P2(addr)	((((int)(addr) & ~0xe0000000) | 0xa0000000))
20 
21 /* The ethernet controller needs to use physical addresses */
22 #if defined(CONFIG_SH_32BIT)
23 #define ADDR_TO_PHY(addr)	((((int)(addr) & ~0xe0000000) | 0x40000000))
24 #else
25 #define ADDR_TO_PHY(addr)	((int)(addr) & ~0xe0000000)
26 #endif
27 #elif defined(CONFIG_ARM)
28 #define inl		readl
29 #define outl	writel
30 #define ADDR_TO_PHY(addr)	((int)(addr))
31 #define ADDR_TO_P2(addr)	(addr)
32 #endif /* defined(CONFIG_SH) */
33 
34 /* base padding size is 16 */
35 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
36 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
37 #endif
38 
39 /* Number of supported ports */
40 #define MAX_PORT_NUM	2
41 
42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
43    buffers must be a multiple of 32 bytes */
44 #define MAX_BUF_SIZE	(48 * 32)
45 
46 /* The number of tx descriptors must be large enough to point to 5 or more
47    frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
48    We use one descriptor per frame */
49 #define NUM_TX_DESC		8
50 
51 /* The size of the tx descriptor is determined by how much padding is used.
52    4, 20, or 52 bytes of padding can be used */
53 #define TX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
54 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
55 #define TX_DESC_SIZE	(12 + TX_DESC_PADDING)
56 
57 /* Tx descriptor. We always use 3 bytes of padding */
58 struct tx_desc_s {
59 	volatile u32 td0;
60 	u32 td1;
61 	u32 td2;		/* Buffer start */
62 	u8 padding[TX_DESC_PADDING];	/* aligned cache line size */
63 };
64 
65 /* There is no limitation in the number of rx descriptors */
66 #define NUM_RX_DESC	8
67 
68 /* The size of the rx descriptor is determined by how much padding is used.
69    4, 20, or 52 bytes of padding can be used */
70 #define RX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
71 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
72 #define RX_DESC_SIZE		(12 + RX_DESC_PADDING)
73 /* aligned cache line size */
74 #define RX_BUF_ALIGNE_SIZE	(CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
75 
76 /* Rx descriptor. We always use 4 bytes of padding */
77 struct rx_desc_s {
78 	volatile u32 rd0;
79 	volatile u32 rd1;
80 	u32 rd2;		/* Buffer start */
81 	u8 padding[TX_DESC_PADDING];	/* aligned cache line size */
82 };
83 
84 struct sh_eth_info {
85 	struct tx_desc_s *tx_desc_malloc;
86 	struct tx_desc_s *tx_desc_base;
87 	struct tx_desc_s *tx_desc_cur;
88 	struct rx_desc_s *rx_desc_malloc;
89 	struct rx_desc_s *rx_desc_base;
90 	struct rx_desc_s *rx_desc_cur;
91 	u8 *rx_buf_malloc;
92 	u8 *rx_buf_base;
93 	u8 mac_addr[6];
94 	u8 phy_addr;
95 	struct eth_device *dev;
96 	struct phy_device *phydev;
97 };
98 
99 struct sh_eth_dev {
100 	int port;
101 	struct sh_eth_info port_info[MAX_PORT_NUM];
102 };
103 
104 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
105 enum {
106 	/* E-DMAC registers */
107 	EDSR = 0,
108 	EDMR,
109 	EDTRR,
110 	EDRRR,
111 	EESR,
112 	EESIPR,
113 	TDLAR,
114 	TDFAR,
115 	TDFXR,
116 	TDFFR,
117 	RDLAR,
118 	RDFAR,
119 	RDFXR,
120 	RDFFR,
121 	TRSCER,
122 	RMFCR,
123 	TFTR,
124 	FDR,
125 	RMCR,
126 	EDOCR,
127 	TFUCR,
128 	RFOCR,
129 	FCFTR,
130 	RPADIR,
131 	TRIMD,
132 	RBWAR,
133 	TBRAR,
134 
135 	/* Ether registers */
136 	ECMR,
137 	ECSR,
138 	ECSIPR,
139 	PIR,
140 	PSR,
141 	RDMLR,
142 	PIPR,
143 	RFLR,
144 	IPGR,
145 	APR,
146 	MPR,
147 	PFTCR,
148 	PFRCR,
149 	RFCR,
150 	RFCF,
151 	TPAUSER,
152 	TPAUSECR,
153 	BCFR,
154 	BCFRR,
155 	GECMR,
156 	BCULR,
157 	MAHR,
158 	MALR,
159 	TROCR,
160 	CDCR,
161 	LCCR,
162 	CNDCR,
163 	CEFCR,
164 	FRECR,
165 	TSFRCR,
166 	TLFRCR,
167 	CERCR,
168 	CEECR,
169 	RMIIMR, /* R8A7790 */
170 	MAFCR,
171 	RTRATE,
172 	CSMR,
173 	RMII_MII,
174 
175 	/* This value must be written at last. */
176 	SH_ETH_MAX_REGISTER_OFFSET,
177 };
178 
179 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
180 	[EDSR]	= 0x0000,
181 	[EDMR]	= 0x0400,
182 	[EDTRR]	= 0x0408,
183 	[EDRRR]	= 0x0410,
184 	[EESR]	= 0x0428,
185 	[EESIPR]	= 0x0430,
186 	[TDLAR]	= 0x0010,
187 	[TDFAR]	= 0x0014,
188 	[TDFXR]	= 0x0018,
189 	[TDFFR]	= 0x001c,
190 	[RDLAR]	= 0x0030,
191 	[RDFAR]	= 0x0034,
192 	[RDFXR]	= 0x0038,
193 	[RDFFR]	= 0x003c,
194 	[TRSCER]	= 0x0438,
195 	[RMFCR]	= 0x0440,
196 	[TFTR]	= 0x0448,
197 	[FDR]	= 0x0450,
198 	[RMCR]	= 0x0458,
199 	[RPADIR]	= 0x0460,
200 	[FCFTR]	= 0x0468,
201 	[CSMR] = 0x04E4,
202 
203 	[ECMR]	= 0x0500,
204 	[ECSR]	= 0x0510,
205 	[ECSIPR]	= 0x0518,
206 	[PIR]	= 0x0520,
207 	[PSR]	= 0x0528,
208 	[PIPR]	= 0x052c,
209 	[RFLR]	= 0x0508,
210 	[APR]	= 0x0554,
211 	[MPR]	= 0x0558,
212 	[PFTCR]	= 0x055c,
213 	[PFRCR]	= 0x0560,
214 	[TPAUSER]	= 0x0564,
215 	[GECMR]	= 0x05b0,
216 	[BCULR]	= 0x05b4,
217 	[MAHR]	= 0x05c0,
218 	[MALR]	= 0x05c8,
219 	[TROCR]	= 0x0700,
220 	[CDCR]	= 0x0708,
221 	[LCCR]	= 0x0710,
222 	[CEFCR]	= 0x0740,
223 	[FRECR]	= 0x0748,
224 	[TSFRCR]	= 0x0750,
225 	[TLFRCR]	= 0x0758,
226 	[RFCR]	= 0x0760,
227 	[CERCR]	= 0x0768,
228 	[CEECR]	= 0x0770,
229 	[MAFCR]	= 0x0778,
230 	[RMII_MII] =  0x0790,
231 };
232 
233 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
234 	[ECMR]	= 0x0100,
235 	[RFLR]	= 0x0108,
236 	[ECSR]	= 0x0110,
237 	[ECSIPR]	= 0x0118,
238 	[PIR]	= 0x0120,
239 	[PSR]	= 0x0128,
240 	[RDMLR]	= 0x0140,
241 	[IPGR]	= 0x0150,
242 	[APR]	= 0x0154,
243 	[MPR]	= 0x0158,
244 	[TPAUSER]	= 0x0164,
245 	[RFCF]	= 0x0160,
246 	[TPAUSECR]	= 0x0168,
247 	[BCFRR]	= 0x016c,
248 	[MAHR]	= 0x01c0,
249 	[MALR]	= 0x01c8,
250 	[TROCR]	= 0x01d0,
251 	[CDCR]	= 0x01d4,
252 	[LCCR]	= 0x01d8,
253 	[CNDCR]	= 0x01dc,
254 	[CEFCR]	= 0x01e4,
255 	[FRECR]	= 0x01e8,
256 	[TSFRCR]	= 0x01ec,
257 	[TLFRCR]	= 0x01f0,
258 	[RFCR]	= 0x01f4,
259 	[MAFCR]	= 0x01f8,
260 	[RTRATE]	= 0x01fc,
261 
262 	[EDMR]	= 0x0000,
263 	[EDTRR]	= 0x0008,
264 	[EDRRR]	= 0x0010,
265 	[TDLAR]	= 0x0018,
266 	[RDLAR]	= 0x0020,
267 	[EESR]	= 0x0028,
268 	[EESIPR]	= 0x0030,
269 	[TRSCER]	= 0x0038,
270 	[RMFCR]	= 0x0040,
271 	[TFTR]	= 0x0048,
272 	[FDR]	= 0x0050,
273 	[RMCR]	= 0x0058,
274 	[TFUCR]	= 0x0064,
275 	[RFOCR]	= 0x0068,
276 	[RMIIMR] = 0x006C,
277 	[FCFTR]	= 0x0070,
278 	[RPADIR]	= 0x0078,
279 	[TRIMD]	= 0x007c,
280 	[RBWAR]	= 0x00c8,
281 	[RDFAR]	= 0x00cc,
282 	[TBRAR]	= 0x00d4,
283 	[TDFAR]	= 0x00d8,
284 };
285 
286 /* Register Address */
287 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
288 #define SH_ETH_TYPE_GETHER
289 #define BASE_IO_ADDR	0xfee00000
290 #elif defined(CONFIG_CPU_SH7757) || \
291 	defined(CONFIG_CPU_SH7752) || \
292 	defined(CONFIG_CPU_SH7753)
293 #if defined(CONFIG_SH_ETHER_USE_GETHER)
294 #define SH_ETH_TYPE_GETHER
295 #define BASE_IO_ADDR	0xfee00000
296 #else
297 #define SH_ETH_TYPE_ETHER
298 #define BASE_IO_ADDR	0xfef00000
299 #endif
300 #elif defined(CONFIG_CPU_SH7724)
301 #define SH_ETH_TYPE_ETHER
302 #define BASE_IO_ADDR	0xA4600000
303 #elif defined(CONFIG_R8A7740)
304 #define SH_ETH_TYPE_GETHER
305 #define BASE_IO_ADDR	0xE9A00000
306 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
307 #define SH_ETH_TYPE_ETHER
308 #define BASE_IO_ADDR	0xEE700200
309 #endif
310 
311 /*
312  * Register's bits
313  * Copy from Linux driver source code
314  */
315 #if defined(SH_ETH_TYPE_GETHER)
316 /* EDSR */
317 enum EDSR_BIT {
318 	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
319 };
320 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
321 #endif
322 
323 /* EDMR */
324 enum DMAC_M_BIT {
325 	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
326 #if defined(SH_ETH_TYPE_GETHER)
327 	EDMR_SRST	= 0x03, /* Receive/Send reset */
328 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
329 	EDMR_EL		= 0x40, /* Litte endian */
330 #elif defined(SH_ETH_TYPE_ETHER)
331 	EDMR_SRST	= 0x01,
332 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
333 	EDMR_EL		= 0x40, /* Litte endian */
334 #else
335 	EDMR_SRST = 0x01,
336 #endif
337 };
338 
339 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
340 # define EMDR_DESC EDMR_DL1
341 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
342 # define EMDR_DESC EDMR_DL0
343 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
344 # define EMDR_DESC 0
345 #endif
346 
347 /* RFLR */
348 #define RFLR_RFL_MIN	0x05EE	/* Recv Frame length 1518 byte */
349 
350 /* EDTRR */
351 enum DMAC_T_BIT {
352 #if defined(SH_ETH_TYPE_GETHER)
353 	EDTRR_TRNS = 0x03,
354 #else
355 	EDTRR_TRNS = 0x01,
356 #endif
357 };
358 
359 /* GECMR */
360 enum GECMR_BIT {
361 #if defined(CONFIG_CPU_SH7757) || \
362 	defined(CONFIG_CPU_SH7752) || \
363 	defined(CONFIG_CPU_SH7753)
364 	GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
365 #else
366 	GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
367 #endif
368 };
369 
370 /* EDRRR*/
371 enum EDRRR_R_BIT {
372 	EDRRR_R = 0x01,
373 };
374 
375 /* TPAUSER */
376 enum TPAUSER_BIT {
377 	TPAUSER_TPAUSE = 0x0000ffff,
378 	TPAUSER_UNLIMITED = 0,
379 };
380 
381 /* BCFR */
382 enum BCFR_BIT {
383 	BCFR_RPAUSE = 0x0000ffff,
384 	BCFR_UNLIMITED = 0,
385 };
386 
387 /* PIR */
388 enum PIR_BIT {
389 	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
390 };
391 
392 /* PSR */
393 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
394 
395 /* EESR */
396 enum EESR_BIT {
397 
398 #if defined(SH_ETH_TYPE_ETHER)
399 	EESR_TWB  = 0x40000000,
400 #else
401 	EESR_TWB  = 0xC0000000,
402 	EESR_TC1  = 0x20000000,
403 	EESR_TUC  = 0x10000000,
404 	EESR_ROC  = 0x80000000,
405 #endif
406 	EESR_TABT = 0x04000000,
407 	EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
408 #if defined(SH_ETH_TYPE_ETHER)
409 	EESR_ADE  = 0x00800000,
410 #endif
411 	EESR_ECI  = 0x00400000,
412 	EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
413 	EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
414 	EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
415 #if defined(SH_ETH_TYPE_ETHER)
416 	EESR_CND  = 0x00000800,
417 #endif
418 	EESR_DLC  = 0x00000400,
419 	EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
420 	EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
421 	EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
422 	rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
423 	EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
424 };
425 
426 
427 #if defined(SH_ETH_TYPE_GETHER)
428 # define TX_CHECK (EESR_TC1 | EESR_FTC)
429 # define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
430 		| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
431 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
432 
433 #else
434 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
435 # define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
436 		| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
437 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
438 #endif
439 
440 /* EESIPR */
441 enum DMAC_IM_BIT {
442 	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
443 	DMAC_M_RABT = 0x02000000,
444 	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
445 	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
446 	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
447 	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
448 	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
449 	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
450 	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
451 	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
452 	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
453 	DMAC_M_RINT1 = 0x00000001,
454 };
455 
456 /* Receive descriptor bit */
457 enum RD_STS_BIT {
458 	RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
459 	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
460 	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
461 	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
462 	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
463 	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
464 	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
465 	RD_RFS1 = 0x00000001,
466 };
467 #define RDF1ST	RD_RFP1
468 #define RDFEND	RD_RFP0
469 #define RD_RFP	(RD_RFP1|RD_RFP0)
470 
471 /* RDFFR*/
472 enum RDFFR_BIT {
473 	RDFFR_RDLF = 0x01,
474 };
475 
476 /* FCFTR */
477 enum FCFTR_BIT {
478 	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
479 	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
480 	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
481 };
482 #define FIFO_F_D_RFF	(FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
483 #define FIFO_F_D_RFD	(FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
484 
485 /* Transfer descriptor bit */
486 enum TD_STS_BIT {
487 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER)
488 	TD_TACT = 0x80000000,
489 #else
490 	TD_TACT = 0x7fffffff,
491 #endif
492 	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
493 	TD_TFP0 = 0x10000000,
494 };
495 #define TDF1ST	TD_TFP1
496 #define TDFEND	TD_TFP0
497 #define TD_TFP	(TD_TFP1|TD_TFP0)
498 
499 /* RMCR */
500 enum RECV_RST_BIT { RMCR_RST = 0x01, };
501 /* ECMR */
502 enum FELIC_MODE_BIT {
503 #if defined(SH_ETH_TYPE_GETHER)
504 	ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
505 	ECMR_RZPF = 0x00100000,
506 #endif
507 	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
508 	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
509 	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
510 	ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
511 	ECMR_PRM = 0x00000001,
512 #ifdef CONFIG_CPU_SH7724
513 	ECMR_RTM = 0x00000010,
514 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
515 	ECMR_RTM = 0x00000004,
516 #endif
517 
518 };
519 
520 #if defined(SH_ETH_TYPE_GETHER)
521 #define ECMR_CHG_DM	(ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
522 						ECMR_TXF | ECMR_MCT)
523 #elif defined(SH_ETH_TYPE_ETHER)
524 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
525 #else
526 #define ECMR_CHG_DM	(ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
527 #endif
528 
529 /* ECSR */
530 enum ECSR_STATUS_BIT {
531 #if defined(SH_ETH_TYPE_ETHER)
532 	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
533 #endif
534 	ECSR_LCHNG = 0x04,
535 	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
536 };
537 
538 #if defined(SH_ETH_TYPE_GETHER)
539 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
540 #else
541 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
542 			ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
543 #endif
544 
545 /* ECSIPR */
546 enum ECSIPR_STATUS_MASK_BIT {
547 #if defined(SH_ETH_TYPE_ETHER)
548 	ECSIPR_BRCRXIP = 0x20,
549 	ECSIPR_PSRTOIP = 0x10,
550 #elif defined(SH_ETY_TYPE_GETHER)
551 	ECSIPR_PSRTOIP = 0x10,
552 	ECSIPR_PHYIP = 0x08,
553 #endif
554 	ECSIPR_LCHNGIP = 0x04,
555 	ECSIPR_MPDIP = 0x02,
556 	ECSIPR_ICDIP = 0x01,
557 };
558 
559 #if defined(SH_ETH_TYPE_GETHER)
560 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
561 #else
562 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
563 				ECSIPR_ICDIP | ECSIPR_MPDIP)
564 #endif
565 
566 /* APR */
567 enum APR_BIT {
568 	APR_AP = 0x00000004,
569 };
570 
571 /* MPR */
572 enum MPR_BIT {
573 	MPR_MP = 0x00000006,
574 };
575 
576 /* TRSCER */
577 enum DESC_I_BIT {
578 	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
579 	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
580 	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
581 	DESC_I_RINT1 = 0x0001,
582 };
583 
584 /* RPADIR */
585 enum RPADIR_BIT {
586 	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
587 	RPADIR_PADR = 0x0003f,
588 };
589 
590 #if defined(SH_ETH_TYPE_GETHER)
591 # define RPADIR_INIT (0x00)
592 #else
593 # define RPADIR_INIT (RPADIR_PADS1)
594 #endif
595 
596 /* FDR */
597 enum FIFO_SIZE_BIT {
598 	FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
599 };
600 
601 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
602 					    int enum_index)
603 {
604 #if defined(SH_ETH_TYPE_GETHER)
605 	const u16 *reg_offset = sh_eth_offset_gigabit;
606 #elif defined(SH_ETH_TYPE_ETHER)
607 	const u16 *reg_offset = sh_eth_offset_fast_sh4;
608 #else
609 #error
610 #endif
611 	return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
612 }
613 
614 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
615 				int enum_index)
616 {
617 	outl(data, sh_eth_reg_addr(eth, enum_index));
618 }
619 
620 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
621 					int enum_index)
622 {
623 	return inl(sh_eth_reg_addr(eth, enum_index));
624 }
625