1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controler. 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (c) 2008 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <netdev.h> 24 #include <asm/types.h> 25 26 #define SHETHER_NAME "sh_eth" 27 28 /* Malloc returns addresses in the P1 area (cacheable). However we need to 29 use area P2 (non-cacheable) */ 30 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 31 32 /* The ethernet controller needs to use physical addresses */ 33 #if defined(CONFIG_SH_32BIT) 34 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 35 #else 36 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 37 #endif 38 39 /* Number of supported ports */ 40 #define MAX_PORT_NUM 2 41 42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 43 buffers must be a multiple of 32 bytes */ 44 #define MAX_BUF_SIZE (48 * 32) 45 46 /* The number of tx descriptors must be large enough to point to 5 or more 47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 48 We use one descriptor per frame */ 49 #define NUM_TX_DESC 8 50 51 /* The size of the tx descriptor is determined by how much padding is used. 52 4, 20, or 52 bytes of padding can be used */ 53 #define TX_DESC_PADDING 4 54 #define TX_DESC_SIZE (12 + TX_DESC_PADDING) 55 56 /* Tx descriptor. We always use 3 bytes of padding */ 57 struct tx_desc_s { 58 volatile u32 td0; 59 u32 td1; 60 u32 td2; /* Buffer start */ 61 u32 padding; 62 }; 63 64 /* There is no limitation in the number of rx descriptors */ 65 #define NUM_RX_DESC 8 66 67 /* The size of the rx descriptor is determined by how much padding is used. 68 4, 20, or 52 bytes of padding can be used */ 69 #define RX_DESC_PADDING 4 70 #define RX_DESC_SIZE (12 + RX_DESC_PADDING) 71 72 /* Rx descriptor. We always use 4 bytes of padding */ 73 struct rx_desc_s { 74 volatile u32 rd0; 75 volatile u32 rd1; 76 u32 rd2; /* Buffer start */ 77 u32 padding; 78 }; 79 80 struct sh_eth_info { 81 struct tx_desc_s *tx_desc_malloc; 82 struct tx_desc_s *tx_desc_base; 83 struct tx_desc_s *tx_desc_cur; 84 struct rx_desc_s *rx_desc_malloc; 85 struct rx_desc_s *rx_desc_base; 86 struct rx_desc_s *rx_desc_cur; 87 u8 *rx_buf_malloc; 88 u8 *rx_buf_base; 89 u8 mac_addr[6]; 90 u8 phy_addr; 91 struct eth_device *dev; 92 struct phy_device *phydev; 93 }; 94 95 struct sh_eth_dev { 96 int port; 97 struct sh_eth_info port_info[MAX_PORT_NUM]; 98 }; 99 100 /* Register Address */ 101 #ifdef CONFIG_CPU_SH7763 102 #define BASE_IO_ADDR 0xfee00000 103 104 #define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) 105 106 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) 107 #define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014) 108 #define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) 109 #define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c) 110 111 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) 112 #define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034) 113 #define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) 114 #define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c) 115 116 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400) 117 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408) 118 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410) 119 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428) 120 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430) 121 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438) 122 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448) 123 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450) 124 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458) 125 #define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460) 126 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468) 127 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500) 128 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508) 129 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518) 130 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520) 131 #define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c) 132 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554) 133 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558) 134 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564) 135 #define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0) 136 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) 137 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) 138 139 #elif defined(CONFIG_CPU_SH7757) 140 #define BASE_IO_ADDR 0xfef00000 141 142 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) 143 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020) 144 145 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) 146 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008) 147 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) 148 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028) 149 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) 150 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) 151 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048) 152 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050) 153 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058) 154 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070) 155 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100) 156 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108) 157 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118) 158 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120) 159 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154) 160 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158) 161 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164) 162 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0) 163 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8) 164 #define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc) 165 #endif 166 167 /* 168 * Register's bits 169 * Copy from Linux driver source code 170 */ 171 #ifdef CONFIG_CPU_SH7763 172 /* EDSR */ 173 enum EDSR_BIT { 174 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 175 }; 176 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 177 #endif 178 179 /* EDMR */ 180 enum DMAC_M_BIT { 181 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 182 #ifdef CONFIG_CPU_SH7763 183 EDMR_SRST = 0x03, 184 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 185 EDMR_EL = 0x40, /* Litte endian */ 186 #elif defined CONFIG_CPU_SH7757 187 EDMR_SRST = 0x01, 188 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 189 EDMR_EL = 0x40, /* Litte endian */ 190 #else /* CONFIG_CPU_SH7763 */ 191 EDMR_SRST = 0x01, 192 #endif 193 }; 194 195 /* RFLR */ 196 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 197 198 /* EDTRR */ 199 enum DMAC_T_BIT { 200 #ifdef CONFIG_CPU_SH7763 201 EDTRR_TRNS = 0x03, 202 #else 203 EDTRR_TRNS = 0x01, 204 #endif 205 }; 206 207 /* GECMR */ 208 enum GECMR_BIT { 209 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 210 }; 211 212 /* EDRRR*/ 213 enum EDRRR_R_BIT { 214 EDRRR_R = 0x01, 215 }; 216 217 /* TPAUSER */ 218 enum TPAUSER_BIT { 219 TPAUSER_TPAUSE = 0x0000ffff, 220 TPAUSER_UNLIMITED = 0, 221 }; 222 223 /* BCFR */ 224 enum BCFR_BIT { 225 BCFR_RPAUSE = 0x0000ffff, 226 BCFR_UNLIMITED = 0, 227 }; 228 229 /* PIR */ 230 enum PIR_BIT { 231 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 232 }; 233 234 /* PSR */ 235 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 236 237 /* EESR */ 238 enum EESR_BIT { 239 #ifndef CONFIG_CPU_SH7763 240 EESR_TWB = 0x40000000, 241 #else 242 EESR_TWB = 0xC0000000, 243 EESR_TC1 = 0x20000000, 244 EESR_TUC = 0x10000000, 245 EESR_ROC = 0x80000000, 246 #endif 247 EESR_TABT = 0x04000000, 248 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 249 #ifndef CONFIG_CPU_SH7763 250 EESR_ADE = 0x00800000, 251 #endif 252 EESR_ECI = 0x00400000, 253 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 254 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 255 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 256 #ifndef CONFIG_CPU_SH7763 257 EESR_CND = 0x00000800, 258 #endif 259 EESR_DLC = 0x00000400, 260 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 261 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 262 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 263 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 264 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 265 }; 266 267 268 #ifdef CONFIG_CPU_SH7763 269 # define TX_CHECK (EESR_TC1 | EESR_FTC) 270 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 271 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 272 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 273 274 #else 275 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 276 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 277 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 278 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 279 #endif 280 281 /* EESIPR */ 282 enum DMAC_IM_BIT { 283 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 284 DMAC_M_RABT = 0x02000000, 285 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 286 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 287 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 288 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 289 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 290 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 291 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 292 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 293 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 294 DMAC_M_RINT1 = 0x00000001, 295 }; 296 297 /* Receive descriptor bit */ 298 enum RD_STS_BIT { 299 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 300 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 301 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 302 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 303 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 304 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 305 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 306 RD_RFS1 = 0x00000001, 307 }; 308 #define RDF1ST RD_RFP1 309 #define RDFEND RD_RFP0 310 #define RD_RFP (RD_RFP1|RD_RFP0) 311 312 /* RDFFR*/ 313 enum RDFFR_BIT { 314 RDFFR_RDLF = 0x01, 315 }; 316 317 /* FCFTR */ 318 enum FCFTR_BIT { 319 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 320 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 321 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 322 }; 323 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 324 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 325 326 /* Transfer descriptor bit */ 327 enum TD_STS_BIT { 328 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) 329 TD_TACT = 0x80000000, 330 #else 331 TD_TACT = 0x7fffffff, 332 #endif 333 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 334 TD_TFP0 = 0x10000000, 335 }; 336 #define TDF1ST TD_TFP1 337 #define TDFEND TD_TFP0 338 #define TD_TFP (TD_TFP1|TD_TFP0) 339 340 /* RMCR */ 341 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 342 /* ECMR */ 343 enum FELIC_MODE_BIT { 344 #ifdef CONFIG_CPU_SH7763 345 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, 346 ECMR_RZPF = 0x00100000, 347 #endif 348 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 349 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 350 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 351 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 352 ECMR_PRM = 0x00000001, 353 }; 354 355 #ifdef CONFIG_CPU_SH7763 356 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ 357 ECMR_TXF | ECMR_MCT) 358 #elif CONFIG_CPU_SH7757 359 #define ECMR_CHG_DM (ECMR_ZPF) 360 #else 361 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 362 #endif 363 364 /* ECSR */ 365 enum ECSR_STATUS_BIT { 366 #ifndef CONFIG_CPU_SH7763 367 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 368 #endif 369 ECSR_LCHNG = 0x04, 370 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 371 }; 372 373 #ifdef CONFIG_CPU_SH7763 374 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 375 #else 376 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 377 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 378 #endif 379 380 /* ECSIPR */ 381 enum ECSIPR_STATUS_MASK_BIT { 382 #ifndef CONFIG_CPU_SH7763 383 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, 384 #endif 385 ECSIPR_LCHNGIP = 0x04, 386 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, 387 }; 388 389 #ifdef CONFIG_CPU_SH7763 390 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 391 #else 392 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 393 ECSIPR_ICDIP | ECSIPR_MPDIP) 394 #endif 395 396 /* APR */ 397 enum APR_BIT { 398 #ifdef CONFIG_CPU_SH7757 399 APR_AP = 0x00000001, 400 #else 401 APR_AP = 0x00000004, 402 #endif 403 }; 404 405 /* MPR */ 406 enum MPR_BIT { 407 #ifdef CONFIG_CPU_SH7757 408 MPR_MP = 0x00000001, 409 #else 410 MPR_MP = 0x00000006, 411 #endif 412 }; 413 414 /* TRSCER */ 415 enum DESC_I_BIT { 416 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 417 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 418 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 419 DESC_I_RINT1 = 0x0001, 420 }; 421 422 /* RPADIR */ 423 enum RPADIR_BIT { 424 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 425 RPADIR_PADR = 0x0003f, 426 }; 427 428 #ifdef CONFIG_CPU_SH7763 429 # define RPADIR_INIT (0x00) 430 #else 431 # define RPADIR_INIT (RPADIR_PADS1) 432 #endif 433 434 /* FDR */ 435 enum FIFO_SIZE_BIT { 436 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 437 }; 438