1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controller. 3 * 4 * Copyright (C) 2008 - 2012 Renesas Solutions Corp. 5 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <netdev.h> 12 #include <asm/types.h> 13 14 #define SHETHER_NAME "sh_eth" 15 16 #if defined(CONFIG_SH) 17 /* Malloc returns addresses in the P1 area (cacheable). However we need to 18 use area P2 (non-cacheable) */ 19 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 20 21 /* The ethernet controller needs to use physical addresses */ 22 #if defined(CONFIG_SH_32BIT) 23 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 24 #else 25 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 26 #endif 27 #elif defined(CONFIG_ARM) 28 #define inl readl 29 #define outl writel 30 #define ADDR_TO_PHY(addr) ((int)(addr)) 31 #define ADDR_TO_P2(addr) (addr) 32 #endif /* defined(CONFIG_SH) */ 33 34 /* base padding size is 16 */ 35 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE 36 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16 37 #endif 38 39 /* Number of supported ports */ 40 #define MAX_PORT_NUM 2 41 42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 43 buffers must be a multiple of 32 bytes */ 44 #define MAX_BUF_SIZE (48 * 32) 45 46 /* The number of tx descriptors must be large enough to point to 5 or more 47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 48 We use one descriptor per frame */ 49 #define NUM_TX_DESC 8 50 51 /* The size of the tx descriptor is determined by how much padding is used. 52 4, 20, or 52 bytes of padding can be used */ 53 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) 54 55 /* Tx descriptor. We always use 3 bytes of padding */ 56 struct tx_desc_s { 57 volatile u32 td0; 58 u32 td1; 59 u32 td2; /* Buffer start */ 60 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ 61 }; 62 63 /* There is no limitation in the number of rx descriptors */ 64 #define NUM_RX_DESC 8 65 66 /* The size of the rx descriptor is determined by how much padding is used. 67 4, 20, or 52 bytes of padding can be used */ 68 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) 69 /* aligned cache line size */ 70 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) 71 72 /* Rx descriptor. We always use 4 bytes of padding */ 73 struct rx_desc_s { 74 volatile u32 rd0; 75 volatile u32 rd1; 76 u32 rd2; /* Buffer start */ 77 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ 78 }; 79 80 struct sh_eth_info { 81 struct tx_desc_s *tx_desc_alloc; 82 struct tx_desc_s *tx_desc_base; 83 struct tx_desc_s *tx_desc_cur; 84 struct rx_desc_s *rx_desc_alloc; 85 struct rx_desc_s *rx_desc_base; 86 struct rx_desc_s *rx_desc_cur; 87 u8 *rx_buf_alloc; 88 u8 *rx_buf_base; 89 u8 mac_addr[6]; 90 u8 phy_addr; 91 struct eth_device *dev; 92 struct phy_device *phydev; 93 }; 94 95 struct sh_eth_dev { 96 int port; 97 struct sh_eth_info port_info[MAX_PORT_NUM]; 98 }; 99 100 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */ 101 enum { 102 /* E-DMAC registers */ 103 EDSR = 0, 104 EDMR, 105 EDTRR, 106 EDRRR, 107 EESR, 108 EESIPR, 109 TDLAR, 110 TDFAR, 111 TDFXR, 112 TDFFR, 113 RDLAR, 114 RDFAR, 115 RDFXR, 116 RDFFR, 117 TRSCER, 118 RMFCR, 119 TFTR, 120 FDR, 121 RMCR, 122 EDOCR, 123 TFUCR, 124 RFOCR, 125 FCFTR, 126 RPADIR, 127 TRIMD, 128 RBWAR, 129 TBRAR, 130 131 /* Ether registers */ 132 ECMR, 133 ECSR, 134 ECSIPR, 135 PIR, 136 PSR, 137 RDMLR, 138 PIPR, 139 RFLR, 140 IPGR, 141 APR, 142 MPR, 143 PFTCR, 144 PFRCR, 145 RFCR, 146 RFCF, 147 TPAUSER, 148 TPAUSECR, 149 BCFR, 150 BCFRR, 151 GECMR, 152 BCULR, 153 MAHR, 154 MALR, 155 TROCR, 156 CDCR, 157 LCCR, 158 CNDCR, 159 CEFCR, 160 FRECR, 161 TSFRCR, 162 TLFRCR, 163 CERCR, 164 CEECR, 165 RMIIMR, /* R8A7790 */ 166 MAFCR, 167 RTRATE, 168 CSMR, 169 RMII_MII, 170 171 /* This value must be written at last. */ 172 SH_ETH_MAX_REGISTER_OFFSET, 173 }; 174 175 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 176 [EDSR] = 0x0000, 177 [EDMR] = 0x0400, 178 [EDTRR] = 0x0408, 179 [EDRRR] = 0x0410, 180 [EESR] = 0x0428, 181 [EESIPR] = 0x0430, 182 [TDLAR] = 0x0010, 183 [TDFAR] = 0x0014, 184 [TDFXR] = 0x0018, 185 [TDFFR] = 0x001c, 186 [RDLAR] = 0x0030, 187 [RDFAR] = 0x0034, 188 [RDFXR] = 0x0038, 189 [RDFFR] = 0x003c, 190 [TRSCER] = 0x0438, 191 [RMFCR] = 0x0440, 192 [TFTR] = 0x0448, 193 [FDR] = 0x0450, 194 [RMCR] = 0x0458, 195 [RPADIR] = 0x0460, 196 [FCFTR] = 0x0468, 197 [CSMR] = 0x04E4, 198 199 [ECMR] = 0x0500, 200 [ECSR] = 0x0510, 201 [ECSIPR] = 0x0518, 202 [PIR] = 0x0520, 203 [PSR] = 0x0528, 204 [PIPR] = 0x052c, 205 [RFLR] = 0x0508, 206 [APR] = 0x0554, 207 [MPR] = 0x0558, 208 [PFTCR] = 0x055c, 209 [PFRCR] = 0x0560, 210 [TPAUSER] = 0x0564, 211 [GECMR] = 0x05b0, 212 [BCULR] = 0x05b4, 213 [MAHR] = 0x05c0, 214 [MALR] = 0x05c8, 215 [TROCR] = 0x0700, 216 [CDCR] = 0x0708, 217 [LCCR] = 0x0710, 218 [CEFCR] = 0x0740, 219 [FRECR] = 0x0748, 220 [TSFRCR] = 0x0750, 221 [TLFRCR] = 0x0758, 222 [RFCR] = 0x0760, 223 [CERCR] = 0x0768, 224 [CEECR] = 0x0770, 225 [MAFCR] = 0x0778, 226 [RMII_MII] = 0x0790, 227 }; 228 229 #if defined(SH_ETH_TYPE_RZ) 230 static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 231 [EDSR] = 0x0000, 232 [EDMR] = 0x0400, 233 [EDTRR] = 0x0408, 234 [EDRRR] = 0x0410, 235 [EESR] = 0x0428, 236 [EESIPR] = 0x0430, 237 [TDLAR] = 0x0010, 238 [TDFAR] = 0x0014, 239 [TDFXR] = 0x0018, 240 [TDFFR] = 0x001c, 241 [RDLAR] = 0x0030, 242 [RDFAR] = 0x0034, 243 [RDFXR] = 0x0038, 244 [RDFFR] = 0x003c, 245 [TRSCER] = 0x0438, 246 [RMFCR] = 0x0440, 247 [TFTR] = 0x0448, 248 [FDR] = 0x0450, 249 [RMCR] = 0x0458, 250 [RPADIR] = 0x0460, 251 [FCFTR] = 0x0468, 252 [CSMR] = 0x04E4, 253 254 [ECMR] = 0x0500, 255 [ECSR] = 0x0510, 256 [ECSIPR] = 0x0518, 257 [PSR] = 0x0528, 258 [PIPR] = 0x052c, 259 [RFLR] = 0x0508, 260 [APR] = 0x0554, 261 [MPR] = 0x0558, 262 [PFTCR] = 0x055c, 263 [PFRCR] = 0x0560, 264 [TPAUSER] = 0x0564, 265 [GECMR] = 0x05b0, 266 [BCULR] = 0x05b4, 267 [MAHR] = 0x05c0, 268 [MALR] = 0x05c8, 269 [TROCR] = 0x0700, 270 [CDCR] = 0x0708, 271 [LCCR] = 0x0710, 272 [CEFCR] = 0x0740, 273 [FRECR] = 0x0748, 274 [TSFRCR] = 0x0750, 275 [TLFRCR] = 0x0758, 276 [RFCR] = 0x0760, 277 [CERCR] = 0x0768, 278 [CEECR] = 0x0770, 279 [MAFCR] = 0x0778, 280 [RMII_MII] = 0x0790, 281 }; 282 #endif 283 284 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 285 [ECMR] = 0x0100, 286 [RFLR] = 0x0108, 287 [ECSR] = 0x0110, 288 [ECSIPR] = 0x0118, 289 [PIR] = 0x0120, 290 [PSR] = 0x0128, 291 [RDMLR] = 0x0140, 292 [IPGR] = 0x0150, 293 [APR] = 0x0154, 294 [MPR] = 0x0158, 295 [TPAUSER] = 0x0164, 296 [RFCF] = 0x0160, 297 [TPAUSECR] = 0x0168, 298 [BCFRR] = 0x016c, 299 [MAHR] = 0x01c0, 300 [MALR] = 0x01c8, 301 [TROCR] = 0x01d0, 302 [CDCR] = 0x01d4, 303 [LCCR] = 0x01d8, 304 [CNDCR] = 0x01dc, 305 [CEFCR] = 0x01e4, 306 [FRECR] = 0x01e8, 307 [TSFRCR] = 0x01ec, 308 [TLFRCR] = 0x01f0, 309 [RFCR] = 0x01f4, 310 [MAFCR] = 0x01f8, 311 [RTRATE] = 0x01fc, 312 313 [EDMR] = 0x0000, 314 [EDTRR] = 0x0008, 315 [EDRRR] = 0x0010, 316 [TDLAR] = 0x0018, 317 [RDLAR] = 0x0020, 318 [EESR] = 0x0028, 319 [EESIPR] = 0x0030, 320 [TRSCER] = 0x0038, 321 [RMFCR] = 0x0040, 322 [TFTR] = 0x0048, 323 [FDR] = 0x0050, 324 [RMCR] = 0x0058, 325 [TFUCR] = 0x0064, 326 [RFOCR] = 0x0068, 327 [RMIIMR] = 0x006C, 328 [FCFTR] = 0x0070, 329 [RPADIR] = 0x0078, 330 [TRIMD] = 0x007c, 331 [RBWAR] = 0x00c8, 332 [RDFAR] = 0x00cc, 333 [TBRAR] = 0x00d4, 334 [TDFAR] = 0x00d8, 335 }; 336 337 /* Register Address */ 338 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 339 #define SH_ETH_TYPE_GETHER 340 #define BASE_IO_ADDR 0xfee00000 341 #elif defined(CONFIG_CPU_SH7757) || \ 342 defined(CONFIG_CPU_SH7752) || \ 343 defined(CONFIG_CPU_SH7753) 344 #if defined(CONFIG_SH_ETHER_USE_GETHER) 345 #define SH_ETH_TYPE_GETHER 346 #define BASE_IO_ADDR 0xfee00000 347 #else 348 #define SH_ETH_TYPE_ETHER 349 #define BASE_IO_ADDR 0xfef00000 350 #endif 351 #elif defined(CONFIG_CPU_SH7724) 352 #define SH_ETH_TYPE_ETHER 353 #define BASE_IO_ADDR 0xA4600000 354 #elif defined(CONFIG_R8A7740) 355 #define SH_ETH_TYPE_GETHER 356 #define BASE_IO_ADDR 0xE9A00000 357 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 358 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 359 #define SH_ETH_TYPE_ETHER 360 #define BASE_IO_ADDR 0xEE700200 361 #elif defined(CONFIG_R7S72100) 362 #define SH_ETH_TYPE_RZ 363 #define BASE_IO_ADDR 0xE8203000 364 #endif 365 366 /* 367 * Register's bits 368 * Copy from Linux driver source code 369 */ 370 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 371 /* EDSR */ 372 enum EDSR_BIT { 373 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 374 }; 375 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 376 #endif 377 378 /* EDMR */ 379 enum DMAC_M_BIT { 380 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 381 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 382 EDMR_SRST = 0x03, /* Receive/Send reset */ 383 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 384 EDMR_EL = 0x40, /* Litte endian */ 385 #elif defined(SH_ETH_TYPE_ETHER) 386 EDMR_SRST = 0x01, 387 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 388 EDMR_EL = 0x40, /* Litte endian */ 389 #else 390 EDMR_SRST = 0x01, 391 #endif 392 }; 393 394 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 395 # define EMDR_DESC EDMR_DL1 396 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 397 # define EMDR_DESC EDMR_DL0 398 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ 399 # define EMDR_DESC 0 400 #endif 401 402 /* RFLR */ 403 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 404 405 /* EDTRR */ 406 enum DMAC_T_BIT { 407 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 408 EDTRR_TRNS = 0x03, 409 #else 410 EDTRR_TRNS = 0x01, 411 #endif 412 }; 413 414 /* GECMR */ 415 enum GECMR_BIT { 416 #if defined(CONFIG_CPU_SH7757) || \ 417 defined(CONFIG_CPU_SH7752) || \ 418 defined(CONFIG_CPU_SH7753) 419 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, 420 #else 421 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 422 #endif 423 }; 424 425 /* EDRRR*/ 426 enum EDRRR_R_BIT { 427 EDRRR_R = 0x01, 428 }; 429 430 /* TPAUSER */ 431 enum TPAUSER_BIT { 432 TPAUSER_TPAUSE = 0x0000ffff, 433 TPAUSER_UNLIMITED = 0, 434 }; 435 436 /* BCFR */ 437 enum BCFR_BIT { 438 BCFR_RPAUSE = 0x0000ffff, 439 BCFR_UNLIMITED = 0, 440 }; 441 442 /* PIR */ 443 enum PIR_BIT { 444 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 445 }; 446 447 /* PSR */ 448 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 449 450 /* EESR */ 451 enum EESR_BIT { 452 #if defined(SH_ETH_TYPE_ETHER) 453 EESR_TWB = 0x40000000, 454 #else 455 EESR_TWB = 0xC0000000, 456 EESR_TC1 = 0x20000000, 457 EESR_TUC = 0x10000000, 458 EESR_ROC = 0x80000000, 459 #endif 460 EESR_TABT = 0x04000000, 461 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 462 #if defined(SH_ETH_TYPE_ETHER) 463 EESR_ADE = 0x00800000, 464 #endif 465 EESR_ECI = 0x00400000, 466 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 467 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 468 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 469 #if defined(SH_ETH_TYPE_ETHER) 470 EESR_CND = 0x00000800, 471 #endif 472 EESR_DLC = 0x00000400, 473 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 474 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 475 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 476 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 477 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 478 }; 479 480 481 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 482 # define TX_CHECK (EESR_TC1 | EESR_FTC) 483 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 484 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 485 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 486 487 #else 488 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 489 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 490 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 491 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 492 #endif 493 494 /* EESIPR */ 495 enum DMAC_IM_BIT { 496 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 497 DMAC_M_RABT = 0x02000000, 498 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 499 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 500 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 501 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 502 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 503 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 504 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 505 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 506 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 507 DMAC_M_RINT1 = 0x00000001, 508 }; 509 510 /* Receive descriptor bit */ 511 enum RD_STS_BIT { 512 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 513 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 514 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 515 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 516 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 517 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 518 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 519 RD_RFS1 = 0x00000001, 520 }; 521 #define RDF1ST RD_RFP1 522 #define RDFEND RD_RFP0 523 #define RD_RFP (RD_RFP1|RD_RFP0) 524 525 /* RDFFR*/ 526 enum RDFFR_BIT { 527 RDFFR_RDLF = 0x01, 528 }; 529 530 /* FCFTR */ 531 enum FCFTR_BIT { 532 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 533 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 534 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 535 }; 536 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 537 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 538 539 /* Transfer descriptor bit */ 540 enum TD_STS_BIT { 541 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \ 542 defined(SH_ETH_TYPE_RZ) 543 TD_TACT = 0x80000000, 544 #else 545 TD_TACT = 0x7fffffff, 546 #endif 547 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 548 TD_TFP0 = 0x10000000, 549 }; 550 #define TDF1ST TD_TFP1 551 #define TDFEND TD_TFP0 552 #define TD_TFP (TD_TFP1|TD_TFP0) 553 554 /* RMCR */ 555 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 556 /* ECMR */ 557 enum FELIC_MODE_BIT { 558 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 559 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, 560 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, 561 #endif 562 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 563 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 564 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 565 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 566 ECMR_PRM = 0x00000001, 567 #ifdef CONFIG_CPU_SH7724 568 ECMR_RTM = 0x00000010, 569 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 570 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 571 ECMR_RTM = 0x00000004, 572 #endif 573 574 }; 575 576 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 577 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \ 578 ECMR_RXF | ECMR_TXF | ECMR_MCT) 579 #elif defined(SH_ETH_TYPE_ETHER) 580 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) 581 #else 582 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 583 #endif 584 585 /* ECSR */ 586 enum ECSR_STATUS_BIT { 587 #if defined(SH_ETH_TYPE_ETHER) 588 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 589 #endif 590 ECSR_LCHNG = 0x04, 591 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 592 }; 593 594 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 595 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 596 #else 597 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 598 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 599 #endif 600 601 /* ECSIPR */ 602 enum ECSIPR_STATUS_MASK_BIT { 603 #if defined(SH_ETH_TYPE_ETHER) 604 ECSIPR_BRCRXIP = 0x20, 605 ECSIPR_PSRTOIP = 0x10, 606 #elif defined(SH_ETY_TYPE_GETHER) 607 ECSIPR_PSRTOIP = 0x10, 608 ECSIPR_PHYIP = 0x08, 609 #endif 610 ECSIPR_LCHNGIP = 0x04, 611 ECSIPR_MPDIP = 0x02, 612 ECSIPR_ICDIP = 0x01, 613 }; 614 615 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 616 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 617 #else 618 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 619 ECSIPR_ICDIP | ECSIPR_MPDIP) 620 #endif 621 622 /* APR */ 623 enum APR_BIT { 624 APR_AP = 0x00000004, 625 }; 626 627 /* MPR */ 628 enum MPR_BIT { 629 MPR_MP = 0x00000006, 630 }; 631 632 /* TRSCER */ 633 enum DESC_I_BIT { 634 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 635 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 636 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 637 DESC_I_RINT1 = 0x0001, 638 }; 639 640 /* RPADIR */ 641 enum RPADIR_BIT { 642 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 643 RPADIR_PADR = 0x0003f, 644 }; 645 646 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 647 # define RPADIR_INIT (0x00) 648 #else 649 # define RPADIR_INIT (RPADIR_PADS1) 650 #endif 651 652 /* FDR */ 653 enum FIFO_SIZE_BIT { 654 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 655 }; 656 657 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, 658 int enum_index) 659 { 660 #if defined(SH_ETH_TYPE_GETHER) 661 const u16 *reg_offset = sh_eth_offset_gigabit; 662 #elif defined(SH_ETH_TYPE_ETHER) 663 const u16 *reg_offset = sh_eth_offset_fast_sh4; 664 #elif defined(SH_ETH_TYPE_RZ) 665 const u16 *reg_offset = sh_eth_offset_rz; 666 #else 667 #error 668 #endif 669 return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; 670 } 671 672 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data, 673 int enum_index) 674 { 675 outl(data, sh_eth_reg_addr(eth, enum_index)); 676 } 677 678 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth, 679 int enum_index) 680 { 681 return inl(sh_eth_reg_addr(eth, enum_index)); 682 } 683