1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controler. 3 * 4 * Copyright (C) 2008 - 2012 Renesas Solutions Corp. 5 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <netdev.h> 12 #include <asm/types.h> 13 14 #define SHETHER_NAME "sh_eth" 15 16 #if defined(CONFIG_SH) 17 /* Malloc returns addresses in the P1 area (cacheable). However we need to 18 use area P2 (non-cacheable) */ 19 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 20 21 /* The ethernet controller needs to use physical addresses */ 22 #if defined(CONFIG_SH_32BIT) 23 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 24 #else 25 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 26 #endif 27 #elif defined(CONFIG_ARM) 28 #define inl readl 29 #define outl writel 30 #define ADDR_TO_PHY(addr) ((int)(addr)) 31 #define ADDR_TO_P2(addr) (addr) 32 #endif /* defined(CONFIG_SH) */ 33 34 /* base padding size is 16 */ 35 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE 36 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16 37 #endif 38 39 /* Number of supported ports */ 40 #define MAX_PORT_NUM 2 41 42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 43 buffers must be a multiple of 32 bytes */ 44 #define MAX_BUF_SIZE (48 * 32) 45 46 /* The number of tx descriptors must be large enough to point to 5 or more 47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 48 We use one descriptor per frame */ 49 #define NUM_TX_DESC 8 50 51 /* The size of the tx descriptor is determined by how much padding is used. 52 4, 20, or 52 bytes of padding can be used */ 53 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) 54 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */ 55 #define TX_DESC_SIZE (12 + TX_DESC_PADDING) 56 57 /* Tx descriptor. We always use 3 bytes of padding */ 58 struct tx_desc_s { 59 volatile u32 td0; 60 u32 td1; 61 u32 td2; /* Buffer start */ 62 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ 63 }; 64 65 /* There is no limitation in the number of rx descriptors */ 66 #define NUM_RX_DESC 8 67 68 /* The size of the rx descriptor is determined by how much padding is used. 69 4, 20, or 52 bytes of padding can be used */ 70 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) 71 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */ 72 #define RX_DESC_SIZE (12 + RX_DESC_PADDING) 73 /* aligned cache line size */ 74 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) 75 76 /* Rx descriptor. We always use 4 bytes of padding */ 77 struct rx_desc_s { 78 volatile u32 rd0; 79 volatile u32 rd1; 80 u32 rd2; /* Buffer start */ 81 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ 82 }; 83 84 struct sh_eth_info { 85 struct tx_desc_s *tx_desc_malloc; 86 struct tx_desc_s *tx_desc_base; 87 struct tx_desc_s *tx_desc_cur; 88 struct rx_desc_s *rx_desc_malloc; 89 struct rx_desc_s *rx_desc_base; 90 struct rx_desc_s *rx_desc_cur; 91 u8 *rx_buf_malloc; 92 u8 *rx_buf_base; 93 u8 mac_addr[6]; 94 u8 phy_addr; 95 struct eth_device *dev; 96 struct phy_device *phydev; 97 }; 98 99 struct sh_eth_dev { 100 int port; 101 struct sh_eth_info port_info[MAX_PORT_NUM]; 102 }; 103 104 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */ 105 enum { 106 /* E-DMAC registers */ 107 EDSR = 0, 108 EDMR, 109 EDTRR, 110 EDRRR, 111 EESR, 112 EESIPR, 113 TDLAR, 114 TDFAR, 115 TDFXR, 116 TDFFR, 117 RDLAR, 118 RDFAR, 119 RDFXR, 120 RDFFR, 121 TRSCER, 122 RMFCR, 123 TFTR, 124 FDR, 125 RMCR, 126 EDOCR, 127 TFUCR, 128 RFOCR, 129 FCFTR, 130 RPADIR, 131 TRIMD, 132 RBWAR, 133 TBRAR, 134 135 /* Ether registers */ 136 ECMR, 137 ECSR, 138 ECSIPR, 139 PIR, 140 PSR, 141 RDMLR, 142 PIPR, 143 RFLR, 144 IPGR, 145 APR, 146 MPR, 147 PFTCR, 148 PFRCR, 149 RFCR, 150 RFCF, 151 TPAUSER, 152 TPAUSECR, 153 BCFR, 154 BCFRR, 155 GECMR, 156 BCULR, 157 MAHR, 158 MALR, 159 TROCR, 160 CDCR, 161 LCCR, 162 CNDCR, 163 CEFCR, 164 FRECR, 165 TSFRCR, 166 TLFRCR, 167 CERCR, 168 CEECR, 169 RMIIMR, /* R8A7790 */ 170 MAFCR, 171 RTRATE, 172 CSMR, 173 RMII_MII, 174 175 /* This value must be written at last. */ 176 SH_ETH_MAX_REGISTER_OFFSET, 177 }; 178 179 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 180 [EDSR] = 0x0000, 181 [EDMR] = 0x0400, 182 [EDTRR] = 0x0408, 183 [EDRRR] = 0x0410, 184 [EESR] = 0x0428, 185 [EESIPR] = 0x0430, 186 [TDLAR] = 0x0010, 187 [TDFAR] = 0x0014, 188 [TDFXR] = 0x0018, 189 [TDFFR] = 0x001c, 190 [RDLAR] = 0x0030, 191 [RDFAR] = 0x0034, 192 [RDFXR] = 0x0038, 193 [RDFFR] = 0x003c, 194 [TRSCER] = 0x0438, 195 [RMFCR] = 0x0440, 196 [TFTR] = 0x0448, 197 [FDR] = 0x0450, 198 [RMCR] = 0x0458, 199 [RPADIR] = 0x0460, 200 [FCFTR] = 0x0468, 201 [CSMR] = 0x04E4, 202 203 [ECMR] = 0x0500, 204 [ECSR] = 0x0510, 205 [ECSIPR] = 0x0518, 206 [PIR] = 0x0520, 207 [PSR] = 0x0528, 208 [PIPR] = 0x052c, 209 [RFLR] = 0x0508, 210 [APR] = 0x0554, 211 [MPR] = 0x0558, 212 [PFTCR] = 0x055c, 213 [PFRCR] = 0x0560, 214 [TPAUSER] = 0x0564, 215 [GECMR] = 0x05b0, 216 [BCULR] = 0x05b4, 217 [MAHR] = 0x05c0, 218 [MALR] = 0x05c8, 219 [TROCR] = 0x0700, 220 [CDCR] = 0x0708, 221 [LCCR] = 0x0710, 222 [CEFCR] = 0x0740, 223 [FRECR] = 0x0748, 224 [TSFRCR] = 0x0750, 225 [TLFRCR] = 0x0758, 226 [RFCR] = 0x0760, 227 [CERCR] = 0x0768, 228 [CEECR] = 0x0770, 229 [MAFCR] = 0x0778, 230 [RMII_MII] = 0x0790, 231 }; 232 233 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 234 [ECMR] = 0x0100, 235 [RFLR] = 0x0108, 236 [ECSR] = 0x0110, 237 [ECSIPR] = 0x0118, 238 [PIR] = 0x0120, 239 [PSR] = 0x0128, 240 [RDMLR] = 0x0140, 241 [IPGR] = 0x0150, 242 [APR] = 0x0154, 243 [MPR] = 0x0158, 244 [TPAUSER] = 0x0164, 245 [RFCF] = 0x0160, 246 [TPAUSECR] = 0x0168, 247 [BCFRR] = 0x016c, 248 [MAHR] = 0x01c0, 249 [MALR] = 0x01c8, 250 [TROCR] = 0x01d0, 251 [CDCR] = 0x01d4, 252 [LCCR] = 0x01d8, 253 [CNDCR] = 0x01dc, 254 [CEFCR] = 0x01e4, 255 [FRECR] = 0x01e8, 256 [TSFRCR] = 0x01ec, 257 [TLFRCR] = 0x01f0, 258 [RFCR] = 0x01f4, 259 [MAFCR] = 0x01f8, 260 [RTRATE] = 0x01fc, 261 262 [EDMR] = 0x0000, 263 [EDTRR] = 0x0008, 264 [EDRRR] = 0x0010, 265 [TDLAR] = 0x0018, 266 [RDLAR] = 0x0020, 267 [EESR] = 0x0028, 268 [EESIPR] = 0x0030, 269 [TRSCER] = 0x0038, 270 [RMFCR] = 0x0040, 271 [TFTR] = 0x0048, 272 [FDR] = 0x0050, 273 [RMCR] = 0x0058, 274 [TFUCR] = 0x0064, 275 [RFOCR] = 0x0068, 276 [RMIIMR] = 0x006C, 277 [FCFTR] = 0x0070, 278 [RPADIR] = 0x0078, 279 [TRIMD] = 0x007c, 280 [RBWAR] = 0x00c8, 281 [RDFAR] = 0x00cc, 282 [TBRAR] = 0x00d4, 283 [TDFAR] = 0x00d8, 284 }; 285 286 /* Register Address */ 287 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 288 #define SH_ETH_TYPE_GETHER 289 #define BASE_IO_ADDR 0xfee00000 290 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 291 #if defined(CONFIG_SH_ETHER_USE_GETHER) 292 #define SH_ETH_TYPE_GETHER 293 #define BASE_IO_ADDR 0xfee00000 294 #else 295 #define SH_ETH_TYPE_ETHER 296 #define BASE_IO_ADDR 0xfef00000 297 #endif 298 #elif defined(CONFIG_CPU_SH7724) 299 #define SH_ETH_TYPE_ETHER 300 #define BASE_IO_ADDR 0xA4600000 301 #elif defined(CONFIG_R8A7740) 302 #define SH_ETH_TYPE_GETHER 303 #define BASE_IO_ADDR 0xE9A00000 304 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) 305 #define SH_ETH_TYPE_ETHER 306 #define BASE_IO_ADDR 0xEE700200 307 #endif 308 309 /* 310 * Register's bits 311 * Copy from Linux driver source code 312 */ 313 #if defined(SH_ETH_TYPE_GETHER) 314 /* EDSR */ 315 enum EDSR_BIT { 316 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 317 }; 318 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 319 #endif 320 321 /* EDMR */ 322 enum DMAC_M_BIT { 323 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 324 #if defined(SH_ETH_TYPE_GETHER) 325 EDMR_SRST = 0x03, /* Receive/Send reset */ 326 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 327 EDMR_EL = 0x40, /* Litte endian */ 328 #elif defined(SH_ETH_TYPE_ETHER) 329 EDMR_SRST = 0x01, 330 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 331 EDMR_EL = 0x40, /* Litte endian */ 332 #else 333 EDMR_SRST = 0x01, 334 #endif 335 }; 336 337 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 338 # define EMDR_DESC EDMR_DL1 339 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 340 # define EMDR_DESC EDMR_DL0 341 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ 342 # define EMDR_DESC 0 343 #endif 344 345 /* RFLR */ 346 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 347 348 /* EDTRR */ 349 enum DMAC_T_BIT { 350 #if defined(SH_ETH_TYPE_GETHER) 351 EDTRR_TRNS = 0x03, 352 #else 353 EDTRR_TRNS = 0x01, 354 #endif 355 }; 356 357 /* GECMR */ 358 enum GECMR_BIT { 359 #if defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 360 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, 361 #else 362 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 363 #endif 364 }; 365 366 /* EDRRR*/ 367 enum EDRRR_R_BIT { 368 EDRRR_R = 0x01, 369 }; 370 371 /* TPAUSER */ 372 enum TPAUSER_BIT { 373 TPAUSER_TPAUSE = 0x0000ffff, 374 TPAUSER_UNLIMITED = 0, 375 }; 376 377 /* BCFR */ 378 enum BCFR_BIT { 379 BCFR_RPAUSE = 0x0000ffff, 380 BCFR_UNLIMITED = 0, 381 }; 382 383 /* PIR */ 384 enum PIR_BIT { 385 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 386 }; 387 388 /* PSR */ 389 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 390 391 /* EESR */ 392 enum EESR_BIT { 393 394 #if defined(SH_ETH_TYPE_ETHER) 395 EESR_TWB = 0x40000000, 396 #else 397 EESR_TWB = 0xC0000000, 398 EESR_TC1 = 0x20000000, 399 EESR_TUC = 0x10000000, 400 EESR_ROC = 0x80000000, 401 #endif 402 EESR_TABT = 0x04000000, 403 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 404 #if defined(SH_ETH_TYPE_ETHER) 405 EESR_ADE = 0x00800000, 406 #endif 407 EESR_ECI = 0x00400000, 408 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 409 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 410 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 411 #if defined(SH_ETH_TYPE_ETHER) 412 EESR_CND = 0x00000800, 413 #endif 414 EESR_DLC = 0x00000400, 415 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 416 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 417 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 418 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 419 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 420 }; 421 422 423 #if defined(SH_ETH_TYPE_GETHER) 424 # define TX_CHECK (EESR_TC1 | EESR_FTC) 425 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 426 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 427 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 428 429 #else 430 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 431 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 432 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 433 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 434 #endif 435 436 /* EESIPR */ 437 enum DMAC_IM_BIT { 438 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 439 DMAC_M_RABT = 0x02000000, 440 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 441 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 442 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 443 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 444 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 445 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 446 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 447 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 448 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 449 DMAC_M_RINT1 = 0x00000001, 450 }; 451 452 /* Receive descriptor bit */ 453 enum RD_STS_BIT { 454 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 455 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 456 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 457 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 458 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 459 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 460 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 461 RD_RFS1 = 0x00000001, 462 }; 463 #define RDF1ST RD_RFP1 464 #define RDFEND RD_RFP0 465 #define RD_RFP (RD_RFP1|RD_RFP0) 466 467 /* RDFFR*/ 468 enum RDFFR_BIT { 469 RDFFR_RDLF = 0x01, 470 }; 471 472 /* FCFTR */ 473 enum FCFTR_BIT { 474 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 475 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 476 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 477 }; 478 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 479 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 480 481 /* Transfer descriptor bit */ 482 enum TD_STS_BIT { 483 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) 484 TD_TACT = 0x80000000, 485 #else 486 TD_TACT = 0x7fffffff, 487 #endif 488 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 489 TD_TFP0 = 0x10000000, 490 }; 491 #define TDF1ST TD_TFP1 492 #define TDFEND TD_TFP0 493 #define TD_TFP (TD_TFP1|TD_TFP0) 494 495 /* RMCR */ 496 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 497 /* ECMR */ 498 enum FELIC_MODE_BIT { 499 #if defined(SH_ETH_TYPE_GETHER) 500 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, 501 ECMR_RZPF = 0x00100000, 502 #endif 503 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 504 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 505 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 506 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 507 ECMR_PRM = 0x00000001, 508 #ifdef CONFIG_CPU_SH7724 509 ECMR_RTM = 0x00000010, 510 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) 511 ECMR_RTM = 0x00000004, 512 #endif 513 514 }; 515 516 #if defined(SH_ETH_TYPE_GETHER) 517 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ 518 ECMR_TXF | ECMR_MCT) 519 #elif defined(SH_ETH_TYPE_ETHER) 520 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) 521 #else 522 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 523 #endif 524 525 /* ECSR */ 526 enum ECSR_STATUS_BIT { 527 #if defined(SH_ETH_TYPE_ETHER) 528 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 529 #endif 530 ECSR_LCHNG = 0x04, 531 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 532 }; 533 534 #if defined(SH_ETH_TYPE_GETHER) 535 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 536 #else 537 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 538 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 539 #endif 540 541 /* ECSIPR */ 542 enum ECSIPR_STATUS_MASK_BIT { 543 #if defined(SH_ETH_TYPE_ETHER) 544 ECSIPR_BRCRXIP = 0x20, 545 ECSIPR_PSRTOIP = 0x10, 546 #elif defined(SH_ETY_TYPE_GETHER) 547 ECSIPR_PSRTOIP = 0x10, 548 ECSIPR_PHYIP = 0x08, 549 #endif 550 ECSIPR_LCHNGIP = 0x04, 551 ECSIPR_MPDIP = 0x02, 552 ECSIPR_ICDIP = 0x01, 553 }; 554 555 #if defined(SH_ETH_TYPE_GETHER) 556 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 557 #else 558 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 559 ECSIPR_ICDIP | ECSIPR_MPDIP) 560 #endif 561 562 /* APR */ 563 enum APR_BIT { 564 APR_AP = 0x00000004, 565 }; 566 567 /* MPR */ 568 enum MPR_BIT { 569 MPR_MP = 0x00000006, 570 }; 571 572 /* TRSCER */ 573 enum DESC_I_BIT { 574 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 575 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 576 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 577 DESC_I_RINT1 = 0x0001, 578 }; 579 580 /* RPADIR */ 581 enum RPADIR_BIT { 582 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 583 RPADIR_PADR = 0x0003f, 584 }; 585 586 #if defined(SH_ETH_TYPE_GETHER) 587 # define RPADIR_INIT (0x00) 588 #else 589 # define RPADIR_INIT (RPADIR_PADS1) 590 #endif 591 592 /* FDR */ 593 enum FIFO_SIZE_BIT { 594 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 595 }; 596 597 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, 598 int enum_index) 599 { 600 #if defined(SH_ETH_TYPE_GETHER) 601 const u16 *reg_offset = sh_eth_offset_gigabit; 602 #elif defined(SH_ETH_TYPE_ETHER) 603 const u16 *reg_offset = sh_eth_offset_fast_sh4; 604 #else 605 #error 606 #endif 607 return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; 608 } 609 610 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data, 611 int enum_index) 612 { 613 outl(data, sh_eth_reg_addr(eth, enum_index)); 614 } 615 616 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth, 617 int enum_index) 618 { 619 return inl(sh_eth_reg_addr(eth, enum_index)); 620 } 621