1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controler. 3 * 4 * Copyright (C) 2008 - 2012 Renesas Solutions Corp. 5 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <netdev.h> 12 #include <asm/types.h> 13 14 #define SHETHER_NAME "sh_eth" 15 16 #if defined(CONFIG_SH) 17 /* Malloc returns addresses in the P1 area (cacheable). However we need to 18 use area P2 (non-cacheable) */ 19 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 20 21 /* The ethernet controller needs to use physical addresses */ 22 #if defined(CONFIG_SH_32BIT) 23 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 24 #else 25 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 26 #endif 27 #elif defined(CONFIG_ARM) 28 #define inl readl 29 #define outl writel 30 #define ADDR_TO_PHY(addr) ((int)(addr)) 31 #define ADDR_TO_P2(addr) (addr) 32 #endif /* defined(CONFIG_SH) */ 33 34 /* Number of supported ports */ 35 #define MAX_PORT_NUM 2 36 37 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 38 buffers must be a multiple of 32 bytes */ 39 #define MAX_BUF_SIZE (48 * 32) 40 41 /* The number of tx descriptors must be large enough to point to 5 or more 42 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 43 We use one descriptor per frame */ 44 #define NUM_TX_DESC 8 45 46 /* The size of the tx descriptor is determined by how much padding is used. 47 4, 20, or 52 bytes of padding can be used */ 48 #define TX_DESC_PADDING 4 49 #define TX_DESC_SIZE (12 + TX_DESC_PADDING) 50 51 /* Tx descriptor. We always use 3 bytes of padding */ 52 struct tx_desc_s { 53 volatile u32 td0; 54 u32 td1; 55 u32 td2; /* Buffer start */ 56 u32 padding; 57 }; 58 59 /* There is no limitation in the number of rx descriptors */ 60 #define NUM_RX_DESC 8 61 62 /* The size of the rx descriptor is determined by how much padding is used. 63 4, 20, or 52 bytes of padding can be used */ 64 #define RX_DESC_PADDING 4 65 #define RX_DESC_SIZE (12 + RX_DESC_PADDING) 66 67 /* Rx descriptor. We always use 4 bytes of padding */ 68 struct rx_desc_s { 69 volatile u32 rd0; 70 volatile u32 rd1; 71 u32 rd2; /* Buffer start */ 72 u32 padding; 73 }; 74 75 struct sh_eth_info { 76 struct tx_desc_s *tx_desc_malloc; 77 struct tx_desc_s *tx_desc_base; 78 struct tx_desc_s *tx_desc_cur; 79 struct rx_desc_s *rx_desc_malloc; 80 struct rx_desc_s *rx_desc_base; 81 struct rx_desc_s *rx_desc_cur; 82 u8 *rx_buf_malloc; 83 u8 *rx_buf_base; 84 u8 mac_addr[6]; 85 u8 phy_addr; 86 struct eth_device *dev; 87 struct phy_device *phydev; 88 }; 89 90 struct sh_eth_dev { 91 int port; 92 struct sh_eth_info port_info[MAX_PORT_NUM]; 93 }; 94 95 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */ 96 enum { 97 /* E-DMAC registers */ 98 EDSR = 0, 99 EDMR, 100 EDTRR, 101 EDRRR, 102 EESR, 103 EESIPR, 104 TDLAR, 105 TDFAR, 106 TDFXR, 107 TDFFR, 108 RDLAR, 109 RDFAR, 110 RDFXR, 111 RDFFR, 112 TRSCER, 113 RMFCR, 114 TFTR, 115 FDR, 116 RMCR, 117 EDOCR, 118 TFUCR, 119 RFOCR, 120 FCFTR, 121 RPADIR, 122 TRIMD, 123 RBWAR, 124 TBRAR, 125 126 /* Ether registers */ 127 ECMR, 128 ECSR, 129 ECSIPR, 130 PIR, 131 PSR, 132 RDMLR, 133 PIPR, 134 RFLR, 135 IPGR, 136 APR, 137 MPR, 138 PFTCR, 139 PFRCR, 140 RFCR, 141 RFCF, 142 TPAUSER, 143 TPAUSECR, 144 BCFR, 145 BCFRR, 146 GECMR, 147 BCULR, 148 MAHR, 149 MALR, 150 TROCR, 151 CDCR, 152 LCCR, 153 CNDCR, 154 CEFCR, 155 FRECR, 156 TSFRCR, 157 TLFRCR, 158 CERCR, 159 CEECR, 160 MAFCR, 161 RTRATE, 162 CSMR, 163 RMII_MII, 164 165 /* This value must be written at last. */ 166 SH_ETH_MAX_REGISTER_OFFSET, 167 }; 168 169 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 170 [EDSR] = 0x0000, 171 [EDMR] = 0x0400, 172 [EDTRR] = 0x0408, 173 [EDRRR] = 0x0410, 174 [EESR] = 0x0428, 175 [EESIPR] = 0x0430, 176 [TDLAR] = 0x0010, 177 [TDFAR] = 0x0014, 178 [TDFXR] = 0x0018, 179 [TDFFR] = 0x001c, 180 [RDLAR] = 0x0030, 181 [RDFAR] = 0x0034, 182 [RDFXR] = 0x0038, 183 [RDFFR] = 0x003c, 184 [TRSCER] = 0x0438, 185 [RMFCR] = 0x0440, 186 [TFTR] = 0x0448, 187 [FDR] = 0x0450, 188 [RMCR] = 0x0458, 189 [RPADIR] = 0x0460, 190 [FCFTR] = 0x0468, 191 [CSMR] = 0x04E4, 192 193 [ECMR] = 0x0500, 194 [ECSR] = 0x0510, 195 [ECSIPR] = 0x0518, 196 [PIR] = 0x0520, 197 [PSR] = 0x0528, 198 [PIPR] = 0x052c, 199 [RFLR] = 0x0508, 200 [APR] = 0x0554, 201 [MPR] = 0x0558, 202 [PFTCR] = 0x055c, 203 [PFRCR] = 0x0560, 204 [TPAUSER] = 0x0564, 205 [GECMR] = 0x05b0, 206 [BCULR] = 0x05b4, 207 [MAHR] = 0x05c0, 208 [MALR] = 0x05c8, 209 [TROCR] = 0x0700, 210 [CDCR] = 0x0708, 211 [LCCR] = 0x0710, 212 [CEFCR] = 0x0740, 213 [FRECR] = 0x0748, 214 [TSFRCR] = 0x0750, 215 [TLFRCR] = 0x0758, 216 [RFCR] = 0x0760, 217 [CERCR] = 0x0768, 218 [CEECR] = 0x0770, 219 [MAFCR] = 0x0778, 220 [RMII_MII] = 0x0790, 221 }; 222 223 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 224 [ECMR] = 0x0100, 225 [RFLR] = 0x0108, 226 [ECSR] = 0x0110, 227 [ECSIPR] = 0x0118, 228 [PIR] = 0x0120, 229 [PSR] = 0x0128, 230 [RDMLR] = 0x0140, 231 [IPGR] = 0x0150, 232 [APR] = 0x0154, 233 [MPR] = 0x0158, 234 [TPAUSER] = 0x0164, 235 [RFCF] = 0x0160, 236 [TPAUSECR] = 0x0168, 237 [BCFRR] = 0x016c, 238 [MAHR] = 0x01c0, 239 [MALR] = 0x01c8, 240 [TROCR] = 0x01d0, 241 [CDCR] = 0x01d4, 242 [LCCR] = 0x01d8, 243 [CNDCR] = 0x01dc, 244 [CEFCR] = 0x01e4, 245 [FRECR] = 0x01e8, 246 [TSFRCR] = 0x01ec, 247 [TLFRCR] = 0x01f0, 248 [RFCR] = 0x01f4, 249 [MAFCR] = 0x01f8, 250 [RTRATE] = 0x01fc, 251 252 [EDMR] = 0x0000, 253 [EDTRR] = 0x0008, 254 [EDRRR] = 0x0010, 255 [TDLAR] = 0x0018, 256 [RDLAR] = 0x0020, 257 [EESR] = 0x0028, 258 [EESIPR] = 0x0030, 259 [TRSCER] = 0x0038, 260 [RMFCR] = 0x0040, 261 [TFTR] = 0x0048, 262 [FDR] = 0x0050, 263 [RMCR] = 0x0058, 264 [TFUCR] = 0x0064, 265 [RFOCR] = 0x0068, 266 [FCFTR] = 0x0070, 267 [RPADIR] = 0x0078, 268 [TRIMD] = 0x007c, 269 [RBWAR] = 0x00c8, 270 [RDFAR] = 0x00cc, 271 [TBRAR] = 0x00d4, 272 [TDFAR] = 0x00d8, 273 }; 274 275 /* Register Address */ 276 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 277 #define SH_ETH_TYPE_GETHER 278 #define BASE_IO_ADDR 0xfee00000 279 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 280 #if defined(CONFIG_SH_ETHER_USE_GETHER) 281 #define SH_ETH_TYPE_GETHER 282 #define BASE_IO_ADDR 0xfee00000 283 #else 284 #define SH_ETH_TYPE_ETHER 285 #define BASE_IO_ADDR 0xfef00000 286 #endif 287 #elif defined(CONFIG_CPU_SH7724) 288 #define SH_ETH_TYPE_ETHER 289 #define BASE_IO_ADDR 0xA4600000 290 #elif defined(CONFIG_R8A7740) 291 #define SH_ETH_TYPE_GETHER 292 #define BASE_IO_ADDR 0xE9A00000 293 #endif 294 295 /* 296 * Register's bits 297 * Copy from Linux driver source code 298 */ 299 #if defined(SH_ETH_TYPE_GETHER) 300 /* EDSR */ 301 enum EDSR_BIT { 302 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 303 }; 304 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 305 #endif 306 307 /* EDMR */ 308 enum DMAC_M_BIT { 309 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 310 #if defined(SH_ETH_TYPE_GETHER) 311 EDMR_SRST = 0x03, /* Receive/Send reset */ 312 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 313 EDMR_EL = 0x40, /* Litte endian */ 314 #elif defined(SH_ETH_TYPE_ETHER) 315 EDMR_SRST = 0x01, 316 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 317 EDMR_EL = 0x40, /* Litte endian */ 318 #else 319 EDMR_SRST = 0x01, 320 #endif 321 }; 322 323 /* RFLR */ 324 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 325 326 /* EDTRR */ 327 enum DMAC_T_BIT { 328 #if defined(SH_ETH_TYPE_GETHER) 329 EDTRR_TRNS = 0x03, 330 #else 331 EDTRR_TRNS = 0x01, 332 #endif 333 }; 334 335 /* GECMR */ 336 enum GECMR_BIT { 337 #if defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 338 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, 339 #else 340 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 341 #endif 342 }; 343 344 /* EDRRR*/ 345 enum EDRRR_R_BIT { 346 EDRRR_R = 0x01, 347 }; 348 349 /* TPAUSER */ 350 enum TPAUSER_BIT { 351 TPAUSER_TPAUSE = 0x0000ffff, 352 TPAUSER_UNLIMITED = 0, 353 }; 354 355 /* BCFR */ 356 enum BCFR_BIT { 357 BCFR_RPAUSE = 0x0000ffff, 358 BCFR_UNLIMITED = 0, 359 }; 360 361 /* PIR */ 362 enum PIR_BIT { 363 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 364 }; 365 366 /* PSR */ 367 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 368 369 /* EESR */ 370 enum EESR_BIT { 371 372 #if defined(SH_ETH_TYPE_ETHER) 373 EESR_TWB = 0x40000000, 374 #else 375 EESR_TWB = 0xC0000000, 376 EESR_TC1 = 0x20000000, 377 EESR_TUC = 0x10000000, 378 EESR_ROC = 0x80000000, 379 #endif 380 EESR_TABT = 0x04000000, 381 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 382 #if defined(SH_ETH_TYPE_ETHER) 383 EESR_ADE = 0x00800000, 384 #endif 385 EESR_ECI = 0x00400000, 386 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 387 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 388 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 389 #if defined(SH_ETH_TYPE_ETHER) 390 EESR_CND = 0x00000800, 391 #endif 392 EESR_DLC = 0x00000400, 393 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 394 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 395 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 396 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 397 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 398 }; 399 400 401 #if defined(SH_ETH_TYPE_GETHER) 402 # define TX_CHECK (EESR_TC1 | EESR_FTC) 403 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 404 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 405 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 406 407 #else 408 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 409 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 410 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 411 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 412 #endif 413 414 /* EESIPR */ 415 enum DMAC_IM_BIT { 416 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 417 DMAC_M_RABT = 0x02000000, 418 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 419 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 420 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 421 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 422 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 423 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 424 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 425 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 426 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 427 DMAC_M_RINT1 = 0x00000001, 428 }; 429 430 /* Receive descriptor bit */ 431 enum RD_STS_BIT { 432 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 433 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 434 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 435 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 436 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 437 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 438 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 439 RD_RFS1 = 0x00000001, 440 }; 441 #define RDF1ST RD_RFP1 442 #define RDFEND RD_RFP0 443 #define RD_RFP (RD_RFP1|RD_RFP0) 444 445 /* RDFFR*/ 446 enum RDFFR_BIT { 447 RDFFR_RDLF = 0x01, 448 }; 449 450 /* FCFTR */ 451 enum FCFTR_BIT { 452 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 453 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 454 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 455 }; 456 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 457 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 458 459 /* Transfer descriptor bit */ 460 enum TD_STS_BIT { 461 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) 462 TD_TACT = 0x80000000, 463 #else 464 TD_TACT = 0x7fffffff, 465 #endif 466 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 467 TD_TFP0 = 0x10000000, 468 }; 469 #define TDF1ST TD_TFP1 470 #define TDFEND TD_TFP0 471 #define TD_TFP (TD_TFP1|TD_TFP0) 472 473 /* RMCR */ 474 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 475 /* ECMR */ 476 enum FELIC_MODE_BIT { 477 #if defined(SH_ETH_TYPE_GETHER) 478 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, 479 ECMR_RZPF = 0x00100000, 480 #endif 481 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 482 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 483 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 484 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 485 ECMR_PRM = 0x00000001, 486 #ifdef CONFIG_CPU_SH7724 487 ECMR_RTM = 0x00000010, 488 #endif 489 490 }; 491 492 #if defined(SH_ETH_TYPE_GETHER) 493 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ 494 ECMR_TXF | ECMR_MCT) 495 #elif defined(SH_ETH_TYPE_ETHER) 496 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) 497 #else 498 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 499 #endif 500 501 /* ECSR */ 502 enum ECSR_STATUS_BIT { 503 #if defined(SH_ETH_TYPE_ETHER) 504 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 505 #endif 506 ECSR_LCHNG = 0x04, 507 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 508 }; 509 510 #if defined(SH_ETH_TYPE_GETHER) 511 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 512 #else 513 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 514 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 515 #endif 516 517 /* ECSIPR */ 518 enum ECSIPR_STATUS_MASK_BIT { 519 #if defined(SH_ETH_TYPE_ETHER) 520 ECSIPR_BRCRXIP = 0x20, 521 ECSIPR_PSRTOIP = 0x10, 522 #elif defined(SH_ETY_TYPE_GETHER) 523 ECSIPR_PSRTOIP = 0x10, 524 ECSIPR_PHYIP = 0x08, 525 #endif 526 ECSIPR_LCHNGIP = 0x04, 527 ECSIPR_MPDIP = 0x02, 528 ECSIPR_ICDIP = 0x01, 529 }; 530 531 #if defined(SH_ETH_TYPE_GETHER) 532 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 533 #else 534 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 535 ECSIPR_ICDIP | ECSIPR_MPDIP) 536 #endif 537 538 /* APR */ 539 enum APR_BIT { 540 APR_AP = 0x00000004, 541 }; 542 543 /* MPR */ 544 enum MPR_BIT { 545 MPR_MP = 0x00000006, 546 }; 547 548 /* TRSCER */ 549 enum DESC_I_BIT { 550 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 551 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 552 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 553 DESC_I_RINT1 = 0x0001, 554 }; 555 556 /* RPADIR */ 557 enum RPADIR_BIT { 558 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 559 RPADIR_PADR = 0x0003f, 560 }; 561 562 #if defined(SH_ETH_TYPE_GETHER) 563 # define RPADIR_INIT (0x00) 564 #else 565 # define RPADIR_INIT (RPADIR_PADS1) 566 #endif 567 568 /* FDR */ 569 enum FIFO_SIZE_BIT { 570 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 571 }; 572 573 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, 574 int enum_index) 575 { 576 #if defined(SH_ETH_TYPE_GETHER) 577 const u16 *reg_offset = sh_eth_offset_gigabit; 578 #elif defined(SH_ETH_TYPE_ETHER) 579 const u16 *reg_offset = sh_eth_offset_fast_sh4; 580 #else 581 #error 582 #endif 583 return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; 584 } 585 586 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data, 587 int enum_index) 588 { 589 outl(data, sh_eth_reg_addr(eth, enum_index)); 590 } 591 592 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth, 593 int enum_index) 594 { 595 return inl(sh_eth_reg_addr(eth, enum_index)); 596 } 597