1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controller. 3 * 4 * Copyright (C) 2008 - 2012 Renesas Solutions Corp. 5 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <netdev.h> 12 #include <asm/types.h> 13 14 #define SHETHER_NAME "sh_eth" 15 16 #if defined(CONFIG_SH) 17 /* Malloc returns addresses in the P1 area (cacheable). However we need to 18 use area P2 (non-cacheable) */ 19 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 20 21 /* The ethernet controller needs to use physical addresses */ 22 #if defined(CONFIG_SH_32BIT) 23 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 24 #else 25 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 26 #endif 27 #elif defined(CONFIG_ARM) 28 #ifndef inl 29 #define inl readl 30 #define outl writel 31 #endif 32 #define ADDR_TO_PHY(addr) ((int)(addr)) 33 #define ADDR_TO_P2(addr) (addr) 34 #endif /* defined(CONFIG_SH) */ 35 36 /* base padding size is 16 */ 37 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE 38 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16 39 #endif 40 41 /* Number of supported ports */ 42 #define MAX_PORT_NUM 2 43 44 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 45 buffers must be a multiple of 32 bytes */ 46 #define MAX_BUF_SIZE (48 * 32) 47 48 /* The number of tx descriptors must be large enough to point to 5 or more 49 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 50 We use one descriptor per frame */ 51 #define NUM_TX_DESC 8 52 53 /* The size of the tx descriptor is determined by how much padding is used. 54 4, 20, or 52 bytes of padding can be used */ 55 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) 56 57 /* Tx descriptor. We always use 3 bytes of padding */ 58 struct tx_desc_s { 59 volatile u32 td0; 60 u32 td1; 61 u32 td2; /* Buffer start */ 62 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ 63 }; 64 65 /* There is no limitation in the number of rx descriptors */ 66 #define NUM_RX_DESC 8 67 68 /* The size of the rx descriptor is determined by how much padding is used. 69 4, 20, or 52 bytes of padding can be used */ 70 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) 71 /* aligned cache line size */ 72 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) 73 74 /* Rx descriptor. We always use 4 bytes of padding */ 75 struct rx_desc_s { 76 volatile u32 rd0; 77 volatile u32 rd1; 78 u32 rd2; /* Buffer start */ 79 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ 80 }; 81 82 struct sh_eth_info { 83 struct tx_desc_s *tx_desc_alloc; 84 struct tx_desc_s *tx_desc_base; 85 struct tx_desc_s *tx_desc_cur; 86 struct rx_desc_s *rx_desc_alloc; 87 struct rx_desc_s *rx_desc_base; 88 struct rx_desc_s *rx_desc_cur; 89 u8 *rx_buf_alloc; 90 u8 *rx_buf_base; 91 u8 mac_addr[6]; 92 u8 phy_addr; 93 struct eth_device *dev; 94 struct phy_device *phydev; 95 void __iomem *iobase; 96 }; 97 98 struct sh_eth_dev { 99 int port; 100 struct sh_eth_info port_info[MAX_PORT_NUM]; 101 }; 102 103 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */ 104 enum { 105 /* E-DMAC registers */ 106 EDSR = 0, 107 EDMR, 108 EDTRR, 109 EDRRR, 110 EESR, 111 EESIPR, 112 TDLAR, 113 TDFAR, 114 TDFXR, 115 TDFFR, 116 RDLAR, 117 RDFAR, 118 RDFXR, 119 RDFFR, 120 TRSCER, 121 RMFCR, 122 TFTR, 123 FDR, 124 RMCR, 125 EDOCR, 126 TFUCR, 127 RFOCR, 128 FCFTR, 129 RPADIR, 130 TRIMD, 131 RBWAR, 132 TBRAR, 133 134 /* Ether registers */ 135 ECMR, 136 ECSR, 137 ECSIPR, 138 PIR, 139 PSR, 140 RDMLR, 141 PIPR, 142 RFLR, 143 IPGR, 144 APR, 145 MPR, 146 PFTCR, 147 PFRCR, 148 RFCR, 149 RFCF, 150 TPAUSER, 151 TPAUSECR, 152 BCFR, 153 BCFRR, 154 GECMR, 155 BCULR, 156 MAHR, 157 MALR, 158 TROCR, 159 CDCR, 160 LCCR, 161 CNDCR, 162 CEFCR, 163 FRECR, 164 TSFRCR, 165 TLFRCR, 166 CERCR, 167 CEECR, 168 RMIIMR, /* R8A7790 */ 169 MAFCR, 170 RTRATE, 171 CSMR, 172 RMII_MII, 173 174 /* This value must be written at last. */ 175 SH_ETH_MAX_REGISTER_OFFSET, 176 }; 177 178 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 179 [EDSR] = 0x0000, 180 [EDMR] = 0x0400, 181 [EDTRR] = 0x0408, 182 [EDRRR] = 0x0410, 183 [EESR] = 0x0428, 184 [EESIPR] = 0x0430, 185 [TDLAR] = 0x0010, 186 [TDFAR] = 0x0014, 187 [TDFXR] = 0x0018, 188 [TDFFR] = 0x001c, 189 [RDLAR] = 0x0030, 190 [RDFAR] = 0x0034, 191 [RDFXR] = 0x0038, 192 [RDFFR] = 0x003c, 193 [TRSCER] = 0x0438, 194 [RMFCR] = 0x0440, 195 [TFTR] = 0x0448, 196 [FDR] = 0x0450, 197 [RMCR] = 0x0458, 198 [RPADIR] = 0x0460, 199 [FCFTR] = 0x0468, 200 [CSMR] = 0x04E4, 201 202 [ECMR] = 0x0500, 203 [ECSR] = 0x0510, 204 [ECSIPR] = 0x0518, 205 [PIR] = 0x0520, 206 [PSR] = 0x0528, 207 [PIPR] = 0x052c, 208 [RFLR] = 0x0508, 209 [APR] = 0x0554, 210 [MPR] = 0x0558, 211 [PFTCR] = 0x055c, 212 [PFRCR] = 0x0560, 213 [TPAUSER] = 0x0564, 214 [GECMR] = 0x05b0, 215 [BCULR] = 0x05b4, 216 [MAHR] = 0x05c0, 217 [MALR] = 0x05c8, 218 [TROCR] = 0x0700, 219 [CDCR] = 0x0708, 220 [LCCR] = 0x0710, 221 [CEFCR] = 0x0740, 222 [FRECR] = 0x0748, 223 [TSFRCR] = 0x0750, 224 [TLFRCR] = 0x0758, 225 [RFCR] = 0x0760, 226 [CERCR] = 0x0768, 227 [CEECR] = 0x0770, 228 [MAFCR] = 0x0778, 229 [RMII_MII] = 0x0790, 230 }; 231 232 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 233 [ECMR] = 0x0100, 234 [RFLR] = 0x0108, 235 [ECSR] = 0x0110, 236 [ECSIPR] = 0x0118, 237 [PIR] = 0x0120, 238 [PSR] = 0x0128, 239 [RDMLR] = 0x0140, 240 [IPGR] = 0x0150, 241 [APR] = 0x0154, 242 [MPR] = 0x0158, 243 [TPAUSER] = 0x0164, 244 [RFCF] = 0x0160, 245 [TPAUSECR] = 0x0168, 246 [BCFRR] = 0x016c, 247 [MAHR] = 0x01c0, 248 [MALR] = 0x01c8, 249 [TROCR] = 0x01d0, 250 [CDCR] = 0x01d4, 251 [LCCR] = 0x01d8, 252 [CNDCR] = 0x01dc, 253 [CEFCR] = 0x01e4, 254 [FRECR] = 0x01e8, 255 [TSFRCR] = 0x01ec, 256 [TLFRCR] = 0x01f0, 257 [RFCR] = 0x01f4, 258 [MAFCR] = 0x01f8, 259 [RTRATE] = 0x01fc, 260 261 [EDMR] = 0x0000, 262 [EDTRR] = 0x0008, 263 [EDRRR] = 0x0010, 264 [TDLAR] = 0x0018, 265 [RDLAR] = 0x0020, 266 [EESR] = 0x0028, 267 [EESIPR] = 0x0030, 268 [TRSCER] = 0x0038, 269 [RMFCR] = 0x0040, 270 [TFTR] = 0x0048, 271 [FDR] = 0x0050, 272 [RMCR] = 0x0058, 273 [TFUCR] = 0x0064, 274 [RFOCR] = 0x0068, 275 [RMIIMR] = 0x006C, 276 [FCFTR] = 0x0070, 277 [RPADIR] = 0x0078, 278 [TRIMD] = 0x007c, 279 [RBWAR] = 0x00c8, 280 [RDFAR] = 0x00cc, 281 [TBRAR] = 0x00d4, 282 [TDFAR] = 0x00d8, 283 }; 284 285 /* Register Address */ 286 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 287 #define SH_ETH_TYPE_GETHER 288 #define BASE_IO_ADDR 0xfee00000 289 #elif defined(CONFIG_CPU_SH7757) || \ 290 defined(CONFIG_CPU_SH7752) || \ 291 defined(CONFIG_CPU_SH7753) 292 #if defined(CONFIG_SH_ETHER_USE_GETHER) 293 #define SH_ETH_TYPE_GETHER 294 #define BASE_IO_ADDR 0xfee00000 295 #else 296 #define SH_ETH_TYPE_ETHER 297 #define BASE_IO_ADDR 0xfef00000 298 #endif 299 #elif defined(CONFIG_CPU_SH7724) 300 #define SH_ETH_TYPE_ETHER 301 #define BASE_IO_ADDR 0xA4600000 302 #elif defined(CONFIG_R8A7740) 303 #define SH_ETH_TYPE_GETHER 304 #define BASE_IO_ADDR 0xE9A00000 305 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 306 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 307 #define SH_ETH_TYPE_ETHER 308 #define BASE_IO_ADDR 0xEE700200 309 #elif defined(CONFIG_R7S72100) 310 #define SH_ETH_TYPE_RZ 311 #define BASE_IO_ADDR 0xE8203000 312 #endif 313 314 /* 315 * Register's bits 316 * Copy from Linux driver source code 317 */ 318 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 319 /* EDSR */ 320 enum EDSR_BIT { 321 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 322 }; 323 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 324 #endif 325 326 /* EDMR */ 327 enum DMAC_M_BIT { 328 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 329 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 330 EDMR_SRST = 0x03, /* Receive/Send reset */ 331 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 332 EDMR_EL = 0x40, /* Litte endian */ 333 #elif defined(SH_ETH_TYPE_ETHER) 334 EDMR_SRST = 0x01, 335 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 336 EDMR_EL = 0x40, /* Litte endian */ 337 #else 338 EDMR_SRST = 0x01, 339 #endif 340 }; 341 342 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 343 # define EMDR_DESC EDMR_DL1 344 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 345 # define EMDR_DESC EDMR_DL0 346 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ 347 # define EMDR_DESC 0 348 #endif 349 350 /* RFLR */ 351 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 352 353 /* EDTRR */ 354 enum DMAC_T_BIT { 355 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 356 EDTRR_TRNS = 0x03, 357 #else 358 EDTRR_TRNS = 0x01, 359 #endif 360 }; 361 362 /* GECMR */ 363 enum GECMR_BIT { 364 #if defined(CONFIG_CPU_SH7757) || \ 365 defined(CONFIG_CPU_SH7752) || \ 366 defined(CONFIG_CPU_SH7753) 367 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, 368 #else 369 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 370 #endif 371 }; 372 373 /* EDRRR*/ 374 enum EDRRR_R_BIT { 375 EDRRR_R = 0x01, 376 }; 377 378 /* TPAUSER */ 379 enum TPAUSER_BIT { 380 TPAUSER_TPAUSE = 0x0000ffff, 381 TPAUSER_UNLIMITED = 0, 382 }; 383 384 /* BCFR */ 385 enum BCFR_BIT { 386 BCFR_RPAUSE = 0x0000ffff, 387 BCFR_UNLIMITED = 0, 388 }; 389 390 /* PIR */ 391 enum PIR_BIT { 392 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 393 }; 394 395 /* PSR */ 396 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 397 398 /* EESR */ 399 enum EESR_BIT { 400 #if defined(SH_ETH_TYPE_ETHER) 401 EESR_TWB = 0x40000000, 402 #else 403 EESR_TWB = 0xC0000000, 404 EESR_TC1 = 0x20000000, 405 EESR_TUC = 0x10000000, 406 EESR_ROC = 0x80000000, 407 #endif 408 EESR_TABT = 0x04000000, 409 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 410 #if defined(SH_ETH_TYPE_ETHER) 411 EESR_ADE = 0x00800000, 412 #endif 413 EESR_ECI = 0x00400000, 414 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 415 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 416 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 417 #if defined(SH_ETH_TYPE_ETHER) 418 EESR_CND = 0x00000800, 419 #endif 420 EESR_DLC = 0x00000400, 421 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 422 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 423 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 424 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 425 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 426 }; 427 428 429 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 430 # define TX_CHECK (EESR_TC1 | EESR_FTC) 431 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 432 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 433 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 434 435 #else 436 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 437 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 438 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 439 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 440 #endif 441 442 /* EESIPR */ 443 enum DMAC_IM_BIT { 444 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 445 DMAC_M_RABT = 0x02000000, 446 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 447 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 448 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 449 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 450 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 451 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 452 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 453 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 454 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 455 DMAC_M_RINT1 = 0x00000001, 456 }; 457 458 /* Receive descriptor bit */ 459 enum RD_STS_BIT { 460 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 461 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 462 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 463 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 464 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 465 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 466 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 467 RD_RFS1 = 0x00000001, 468 }; 469 #define RDF1ST RD_RFP1 470 #define RDFEND RD_RFP0 471 #define RD_RFP (RD_RFP1|RD_RFP0) 472 473 /* RDFFR*/ 474 enum RDFFR_BIT { 475 RDFFR_RDLF = 0x01, 476 }; 477 478 /* FCFTR */ 479 enum FCFTR_BIT { 480 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 481 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 482 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 483 }; 484 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 485 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 486 487 /* Transfer descriptor bit */ 488 enum TD_STS_BIT { 489 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \ 490 defined(SH_ETH_TYPE_RZ) 491 TD_TACT = 0x80000000, 492 #else 493 TD_TACT = 0x7fffffff, 494 #endif 495 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 496 TD_TFP0 = 0x10000000, 497 }; 498 #define TDF1ST TD_TFP1 499 #define TDFEND TD_TFP0 500 #define TD_TFP (TD_TFP1|TD_TFP0) 501 502 /* RMCR */ 503 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 504 /* ECMR */ 505 enum FELIC_MODE_BIT { 506 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 507 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000, 508 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000, 509 #endif 510 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 511 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 512 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 513 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 514 ECMR_PRM = 0x00000001, 515 #ifdef CONFIG_CPU_SH7724 516 ECMR_RTM = 0x00000010, 517 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ 518 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) 519 ECMR_RTM = 0x00000004, 520 #endif 521 522 }; 523 524 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 525 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \ 526 ECMR_RXF | ECMR_TXF | ECMR_MCT) 527 #elif defined(SH_ETH_TYPE_ETHER) 528 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) 529 #else 530 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 531 #endif 532 533 /* ECSR */ 534 enum ECSR_STATUS_BIT { 535 #if defined(SH_ETH_TYPE_ETHER) 536 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 537 #endif 538 ECSR_LCHNG = 0x04, 539 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 540 }; 541 542 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 543 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 544 #else 545 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 546 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 547 #endif 548 549 /* ECSIPR */ 550 enum ECSIPR_STATUS_MASK_BIT { 551 #if defined(SH_ETH_TYPE_ETHER) 552 ECSIPR_BRCRXIP = 0x20, 553 ECSIPR_PSRTOIP = 0x10, 554 #elif defined(SH_ETY_TYPE_GETHER) 555 ECSIPR_PSRTOIP = 0x10, 556 ECSIPR_PHYIP = 0x08, 557 #endif 558 ECSIPR_LCHNGIP = 0x04, 559 ECSIPR_MPDIP = 0x02, 560 ECSIPR_ICDIP = 0x01, 561 }; 562 563 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 564 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 565 #else 566 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 567 ECSIPR_ICDIP | ECSIPR_MPDIP) 568 #endif 569 570 /* APR */ 571 enum APR_BIT { 572 APR_AP = 0x00000004, 573 }; 574 575 /* MPR */ 576 enum MPR_BIT { 577 MPR_MP = 0x00000006, 578 }; 579 580 /* TRSCER */ 581 enum DESC_I_BIT { 582 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 583 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 584 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 585 DESC_I_RINT1 = 0x0001, 586 }; 587 588 /* RPADIR */ 589 enum RPADIR_BIT { 590 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 591 RPADIR_PADR = 0x0003f, 592 }; 593 594 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 595 # define RPADIR_INIT (0x00) 596 #else 597 # define RPADIR_INIT (RPADIR_PADS1) 598 #endif 599 600 /* FDR */ 601 enum FIFO_SIZE_BIT { 602 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 603 }; 604 605 static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port, 606 int enum_index) 607 { 608 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 609 const u16 *reg_offset = sh_eth_offset_gigabit; 610 #elif defined(SH_ETH_TYPE_ETHER) 611 const u16 *reg_offset = sh_eth_offset_fast_sh4; 612 #else 613 #error 614 #endif 615 return (unsigned long)port->iobase + reg_offset[enum_index]; 616 } 617 618 static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data, 619 int enum_index) 620 { 621 outl(data, sh_eth_reg_addr(port, enum_index)); 622 } 623 624 static inline unsigned long sh_eth_read(struct sh_eth_info *port, 625 int enum_index) 626 { 627 return inl(sh_eth_reg_addr(port, enum_index)); 628 } 629