1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controler. 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (c) 2008 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <netdev.h> 24 #include <asm/types.h> 25 26 #define SHETHER_NAME "sh_eth" 27 28 /* Malloc returns addresses in the P1 area (cacheable). However we need to 29 use area P2 (non-cacheable) */ 30 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 31 32 /* The ethernet controller needs to use physical addresses */ 33 #if defined(CONFIG_SH_32BIT) 34 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 35 #else 36 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 37 #endif 38 39 /* Number of supported ports */ 40 #define MAX_PORT_NUM 2 41 42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 43 buffers must be a multiple of 32 bytes */ 44 #define MAX_BUF_SIZE (48 * 32) 45 46 /* The number of tx descriptors must be large enough to point to 5 or more 47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 48 We use one descriptor per frame */ 49 #define NUM_TX_DESC 8 50 51 /* The size of the tx descriptor is determined by how much padding is used. 52 4, 20, or 52 bytes of padding can be used */ 53 #define TX_DESC_PADDING 4 54 #define TX_DESC_SIZE (12 + TX_DESC_PADDING) 55 56 /* Tx descriptor. We always use 3 bytes of padding */ 57 struct tx_desc_s { 58 volatile u32 td0; 59 u32 td1; 60 u32 td2; /* Buffer start */ 61 u32 padding; 62 }; 63 64 /* There is no limitation in the number of rx descriptors */ 65 #define NUM_RX_DESC 8 66 67 /* The size of the rx descriptor is determined by how much padding is used. 68 4, 20, or 52 bytes of padding can be used */ 69 #define RX_DESC_PADDING 4 70 #define RX_DESC_SIZE (12 + RX_DESC_PADDING) 71 72 /* Rx descriptor. We always use 4 bytes of padding */ 73 struct rx_desc_s { 74 volatile u32 rd0; 75 volatile u32 rd1; 76 u32 rd2; /* Buffer start */ 77 u32 padding; 78 }; 79 80 struct sh_eth_info { 81 struct tx_desc_s *tx_desc_malloc; 82 struct tx_desc_s *tx_desc_base; 83 struct tx_desc_s *tx_desc_cur; 84 struct rx_desc_s *rx_desc_malloc; 85 struct rx_desc_s *rx_desc_base; 86 struct rx_desc_s *rx_desc_cur; 87 u8 *rx_buf_malloc; 88 u8 *rx_buf_base; 89 u8 mac_addr[6]; 90 u8 phy_addr; 91 struct eth_device *dev; 92 }; 93 94 struct sh_eth_dev { 95 int port; 96 struct sh_eth_info port_info[MAX_PORT_NUM]; 97 }; 98 99 /* Register Address */ 100 #ifdef CONFIG_CPU_SH7763 101 #define BASE_IO_ADDR 0xfee00000 102 103 #define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) 104 105 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) 106 #define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014) 107 #define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) 108 #define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c) 109 110 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) 111 #define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034) 112 #define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) 113 #define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c) 114 115 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400) 116 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408) 117 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410) 118 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428) 119 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430) 120 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438) 121 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448) 122 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450) 123 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458) 124 #define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460) 125 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468) 126 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500) 127 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508) 128 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518) 129 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520) 130 #define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c) 131 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554) 132 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558) 133 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564) 134 #define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0) 135 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) 136 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) 137 138 #elif defined(CONFIG_CPU_SH7757) 139 #define BASE_IO_ADDR 0xfef00000 140 141 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) 142 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020) 143 144 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) 145 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008) 146 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) 147 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028) 148 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) 149 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) 150 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048) 151 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050) 152 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058) 153 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070) 154 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100) 155 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108) 156 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118) 157 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120) 158 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154) 159 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158) 160 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164) 161 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0) 162 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8) 163 #define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc) 164 #endif 165 166 /* 167 * Register's bits 168 * Copy from Linux driver source code 169 */ 170 #ifdef CONFIG_CPU_SH7763 171 /* EDSR */ 172 enum EDSR_BIT { 173 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 174 }; 175 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 176 #endif 177 178 /* EDMR */ 179 enum DMAC_M_BIT { 180 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 181 #ifdef CONFIG_CPU_SH7763 182 EDMR_SRST = 0x03, 183 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 184 EDMR_EL = 0x40, /* Litte endian */ 185 #elif defined CONFIG_CPU_SH7757 186 EDMR_SRST = 0x01, 187 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 188 EDMR_EL = 0x40, /* Litte endian */ 189 #else /* CONFIG_CPU_SH7763 */ 190 EDMR_SRST = 0x01, 191 #endif 192 }; 193 194 /* RFLR */ 195 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 196 197 /* EDTRR */ 198 enum DMAC_T_BIT { 199 #ifdef CONFIG_CPU_SH7763 200 EDTRR_TRNS = 0x03, 201 #else 202 EDTRR_TRNS = 0x01, 203 #endif 204 }; 205 206 /* GECMR */ 207 enum GECMR_BIT { 208 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 209 }; 210 211 /* EDRRR*/ 212 enum EDRRR_R_BIT { 213 EDRRR_R = 0x01, 214 }; 215 216 /* TPAUSER */ 217 enum TPAUSER_BIT { 218 TPAUSER_TPAUSE = 0x0000ffff, 219 TPAUSER_UNLIMITED = 0, 220 }; 221 222 /* BCFR */ 223 enum BCFR_BIT { 224 BCFR_RPAUSE = 0x0000ffff, 225 BCFR_UNLIMITED = 0, 226 }; 227 228 /* PIR */ 229 enum PIR_BIT { 230 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 231 }; 232 233 /* PSR */ 234 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 235 236 /* EESR */ 237 enum EESR_BIT { 238 #ifndef CONFIG_CPU_SH7763 239 EESR_TWB = 0x40000000, 240 #else 241 EESR_TWB = 0xC0000000, 242 EESR_TC1 = 0x20000000, 243 EESR_TUC = 0x10000000, 244 EESR_ROC = 0x80000000, 245 #endif 246 EESR_TABT = 0x04000000, 247 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 248 #ifndef CONFIG_CPU_SH7763 249 EESR_ADE = 0x00800000, 250 #endif 251 EESR_ECI = 0x00400000, 252 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 253 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 254 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 255 #ifndef CONFIG_CPU_SH7763 256 EESR_CND = 0x00000800, 257 #endif 258 EESR_DLC = 0x00000400, 259 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 260 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 261 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 262 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 263 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 264 }; 265 266 267 #ifdef CONFIG_CPU_SH7763 268 # define TX_CHECK (EESR_TC1 | EESR_FTC) 269 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 270 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 271 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 272 273 #else 274 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 275 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 276 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 277 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 278 #endif 279 280 /* EESIPR */ 281 enum DMAC_IM_BIT { 282 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 283 DMAC_M_RABT = 0x02000000, 284 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 285 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 286 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 287 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 288 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 289 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 290 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 291 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 292 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 293 DMAC_M_RINT1 = 0x00000001, 294 }; 295 296 /* Receive descriptor bit */ 297 enum RD_STS_BIT { 298 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 299 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 300 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 301 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 302 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 303 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 304 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 305 RD_RFS1 = 0x00000001, 306 }; 307 #define RDF1ST RD_RFP1 308 #define RDFEND RD_RFP0 309 #define RD_RFP (RD_RFP1|RD_RFP0) 310 311 /* RDFFR*/ 312 enum RDFFR_BIT { 313 RDFFR_RDLF = 0x01, 314 }; 315 316 /* FCFTR */ 317 enum FCFTR_BIT { 318 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 319 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 320 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 321 }; 322 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 323 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 324 325 /* Transfer descriptor bit */ 326 enum TD_STS_BIT { 327 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) 328 TD_TACT = 0x80000000, 329 #else 330 TD_TACT = 0x7fffffff, 331 #endif 332 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 333 TD_TFP0 = 0x10000000, 334 }; 335 #define TDF1ST TD_TFP1 336 #define TDFEND TD_TFP0 337 #define TD_TFP (TD_TFP1|TD_TFP0) 338 339 /* RMCR */ 340 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 341 /* ECMR */ 342 enum FELIC_MODE_BIT { 343 #ifdef CONFIG_CPU_SH7763 344 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, 345 ECMR_RZPF = 0x00100000, 346 #endif 347 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 348 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 349 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 350 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 351 ECMR_PRM = 0x00000001, 352 }; 353 354 #ifdef CONFIG_CPU_SH7763 355 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ 356 ECMR_TXF | ECMR_MCT) 357 #elif CONFIG_CPU_SH7757 358 #define ECMR_CHG_DM (ECMR_ZPF) 359 #else 360 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 361 #endif 362 363 /* ECSR */ 364 enum ECSR_STATUS_BIT { 365 #ifndef CONFIG_CPU_SH7763 366 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 367 #endif 368 ECSR_LCHNG = 0x04, 369 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 370 }; 371 372 #ifdef CONFIG_CPU_SH7763 373 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 374 #else 375 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 376 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 377 #endif 378 379 /* ECSIPR */ 380 enum ECSIPR_STATUS_MASK_BIT { 381 #ifndef CONFIG_CPU_SH7763 382 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, 383 #endif 384 ECSIPR_LCHNGIP = 0x04, 385 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, 386 }; 387 388 #ifdef CONFIG_CPU_SH7763 389 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 390 #else 391 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 392 ECSIPR_ICDIP | ECSIPR_MPDIP) 393 #endif 394 395 /* APR */ 396 enum APR_BIT { 397 #ifdef CONFIG_CPU_SH7757 398 APR_AP = 0x00000001, 399 #else 400 APR_AP = 0x00000004, 401 #endif 402 }; 403 404 /* MPR */ 405 enum MPR_BIT { 406 #ifdef CONFIG_CPU_SH7757 407 MPR_MP = 0x00000001, 408 #else 409 MPR_MP = 0x00000006, 410 #endif 411 }; 412 413 /* TRSCER */ 414 enum DESC_I_BIT { 415 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 416 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 417 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 418 DESC_I_RINT1 = 0x0001, 419 }; 420 421 /* RPADIR */ 422 enum RPADIR_BIT { 423 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 424 RPADIR_PADR = 0x0003f, 425 }; 426 427 #ifdef CONFIG_CPU_SH7763 428 # define RPADIR_INIT (0x00) 429 #else 430 # define RPADIR_INIT (RPADIR_PADS1) 431 #endif 432 433 /* FDR */ 434 enum FIFO_SIZE_BIT { 435 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 436 }; 437 438 enum PHY_OFFSETS { 439 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, 440 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6, 441 PHY_16 = 16, 442 }; 443 444 /* PHY_CTRL */ 445 enum PHY_CTRL_BIT { 446 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000, 447 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400, 448 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080, 449 }; 450 #define DM9161_PHY_C_ANEGEN 0 /* auto nego special */ 451 452 /* PHY_STAT */ 453 enum PHY_STAT_BIT { 454 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000, 455 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020, 456 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004, 457 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001, 458 }; 459 460 /* PHY_ANA */ 461 enum PHY_ANA_BIT { 462 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000, 463 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100, 464 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020, 465 PHY_A_SEL = 0x001e, 466 PHY_A_EXT = 0x0001, 467 }; 468 469 /* PHY_ANL */ 470 enum PHY_ANL_BIT { 471 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000, 472 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100, 473 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020, 474 PHY_L_SEL = 0x001f, 475 }; 476 477 /* PHY_ANE */ 478 enum PHY_ANE_BIT { 479 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004, 480 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001, 481 }; 482 483 /* DM9161 */ 484 enum PHY_16_BIT { 485 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000, 486 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800, 487 PHY_16_TXselect = 0x0400, 488 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100, 489 PHY_16_Force100LNK = 0x0080, 490 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020, 491 PHY_16_RPDCTR_EN = 0x0010, 492 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004, 493 PHY_16_Sleepmode = 0x0002, 494 PHY_16_RemoteLoopOut = 0x0001, 495 }; 496