1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controler. 3 * 4 * Copyright (C) 2008, 2011 Renesas Solutions Corp. 5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <netdev.h> 24 #include <asm/types.h> 25 26 #define SHETHER_NAME "sh_eth" 27 28 /* Malloc returns addresses in the P1 area (cacheable). However we need to 29 use area P2 (non-cacheable) */ 30 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 31 32 /* The ethernet controller needs to use physical addresses */ 33 #if defined(CONFIG_SH_32BIT) 34 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 35 #else 36 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 37 #endif 38 39 /* Number of supported ports */ 40 #define MAX_PORT_NUM 2 41 42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 43 buffers must be a multiple of 32 bytes */ 44 #define MAX_BUF_SIZE (48 * 32) 45 46 /* The number of tx descriptors must be large enough to point to 5 or more 47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 48 We use one descriptor per frame */ 49 #define NUM_TX_DESC 8 50 51 /* The size of the tx descriptor is determined by how much padding is used. 52 4, 20, or 52 bytes of padding can be used */ 53 #define TX_DESC_PADDING 4 54 #define TX_DESC_SIZE (12 + TX_DESC_PADDING) 55 56 /* Tx descriptor. We always use 3 bytes of padding */ 57 struct tx_desc_s { 58 volatile u32 td0; 59 u32 td1; 60 u32 td2; /* Buffer start */ 61 u32 padding; 62 }; 63 64 /* There is no limitation in the number of rx descriptors */ 65 #define NUM_RX_DESC 8 66 67 /* The size of the rx descriptor is determined by how much padding is used. 68 4, 20, or 52 bytes of padding can be used */ 69 #define RX_DESC_PADDING 4 70 #define RX_DESC_SIZE (12 + RX_DESC_PADDING) 71 72 /* Rx descriptor. We always use 4 bytes of padding */ 73 struct rx_desc_s { 74 volatile u32 rd0; 75 volatile u32 rd1; 76 u32 rd2; /* Buffer start */ 77 u32 padding; 78 }; 79 80 struct sh_eth_info { 81 struct tx_desc_s *tx_desc_malloc; 82 struct tx_desc_s *tx_desc_base; 83 struct tx_desc_s *tx_desc_cur; 84 struct rx_desc_s *rx_desc_malloc; 85 struct rx_desc_s *rx_desc_base; 86 struct rx_desc_s *rx_desc_cur; 87 u8 *rx_buf_malloc; 88 u8 *rx_buf_base; 89 u8 mac_addr[6]; 90 u8 phy_addr; 91 struct eth_device *dev; 92 struct phy_device *phydev; 93 }; 94 95 struct sh_eth_dev { 96 int port; 97 struct sh_eth_info port_info[MAX_PORT_NUM]; 98 }; 99 100 /* Register Address */ 101 #ifdef CONFIG_CPU_SH7763 102 #define SH_ETH_TYPE_GETHER 103 #define BASE_IO_ADDR 0xfee00000 104 105 #define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) 106 107 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) 108 #define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014) 109 #define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) 110 #define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c) 111 112 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) 113 #define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034) 114 #define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) 115 #define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c) 116 117 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400) 118 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408) 119 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410) 120 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428) 121 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430) 122 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438) 123 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448) 124 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450) 125 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458) 126 #define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460) 127 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468) 128 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500) 129 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508) 130 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518) 131 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520) 132 #define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c) 133 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554) 134 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558) 135 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564) 136 #define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0) 137 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) 138 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) 139 140 #elif defined(CONFIG_CPU_SH7757) 141 #define SH_ETH_TYPE_ETHER 142 #define BASE_IO_ADDR 0xfef00000 143 144 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) 145 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020) 146 147 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) 148 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008) 149 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) 150 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028) 151 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) 152 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) 153 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048) 154 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050) 155 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058) 156 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070) 157 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100) 158 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108) 159 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118) 160 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120) 161 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154) 162 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158) 163 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164) 164 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0) 165 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8) 166 #define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc) 167 168 #elif defined(CONFIG_CPU_SH7724) 169 #define SH_ETH_TYPE_ETHER 170 #define BASE_IO_ADDR 0xA4600000 171 172 #define TDLAR(port) (BASE_IO_ADDR + 0x0018) 173 #define RDLAR(port) (BASE_IO_ADDR + 0x0020) 174 175 #define EDMR(port) (BASE_IO_ADDR + 0x0000) 176 #define EDTRR(port) (BASE_IO_ADDR + 0x0008) 177 #define EDRRR(port) (BASE_IO_ADDR + 0x0010) 178 #define EESR(port) (BASE_IO_ADDR + 0x0028) 179 #define EESIPR(port) (BASE_IO_ADDR + 0x0030) 180 #define TRSCER(port) (BASE_IO_ADDR + 0x0038) 181 #define TFTR(port) (BASE_IO_ADDR + 0x0048) 182 #define FDR(port) (BASE_IO_ADDR + 0x0050) 183 #define RMCR(port) (BASE_IO_ADDR + 0x0058) 184 #define FCFTR(port) (BASE_IO_ADDR + 0x0070) 185 #define ECMR(port) (BASE_IO_ADDR + 0x0100) 186 #define RFLR(port) (BASE_IO_ADDR + 0x0108) 187 #define ECSIPR(port) (BASE_IO_ADDR + 0x0118) 188 #define PIR(port) (BASE_IO_ADDR + 0x0120) 189 #define APR(port) (BASE_IO_ADDR + 0x0154) 190 #define MPR(port) (BASE_IO_ADDR + 0x0158) 191 #define TPAUSER(port) (BASE_IO_ADDR + 0x0164) 192 #define MAHR(port) (BASE_IO_ADDR + 0x01c0) 193 #define MALR(port) (BASE_IO_ADDR + 0x01c8) 194 195 #elif defined(CONFIG_CPU_SH7734) 196 #define SH_ETH_TYPE_GETHER 197 #define BASE_IO_ADDR 0xFEE00000 198 199 #define EDSR(port) (BASE_IO_ADDR) 200 201 #define TDLAR(port) (BASE_IO_ADDR + 0x0010) 202 #define TDFAR(port) (BASE_IO_ADDR + 0x0014) 203 #define TDFXR(port) (BASE_IO_ADDR + 0x0018) 204 #define TDFFR(port) (BASE_IO_ADDR + 0x001c) 205 #define RDLAR(port) (BASE_IO_ADDR + 0x0030) 206 #define RDFAR(port) (BASE_IO_ADDR + 0x0034) 207 #define RDFXR(port) (BASE_IO_ADDR + 0x0038) 208 #define RDFFR(port) (BASE_IO_ADDR + 0x003c) 209 210 #define EDMR(port) (BASE_IO_ADDR + 0x0400) 211 #define EDTRR(port) (BASE_IO_ADDR + 0x0408) 212 #define EDRRR(port) (BASE_IO_ADDR + 0x0410) 213 #define EESR(port) (BASE_IO_ADDR + 0x0428) 214 #define EESIPR(port) (BASE_IO_ADDR + 0x0430) 215 #define TRSCER(port) (BASE_IO_ADDR + 0x0438) 216 #define TFTR(port) (BASE_IO_ADDR + 0x0448) 217 #define FDR(port) (BASE_IO_ADDR + 0x0450) 218 #define RMCR(port) (BASE_IO_ADDR + 0x0458) 219 #define RPADIR(port) (BASE_IO_ADDR + 0x0460) 220 #define FCFTR(port) (BASE_IO_ADDR + 0x0468) 221 #define ECMR(port) (BASE_IO_ADDR + 0x0500) 222 #define RFLR(port) (BASE_IO_ADDR + 0x0508) 223 #define ECSIPR(port) (BASE_IO_ADDR + 0x0518) 224 #define PIR(port) (BASE_IO_ADDR + 0x0520) 225 #define PIPR(port) (BASE_IO_ADDR + 0x052c) 226 #define APR(port) (BASE_IO_ADDR + 0x0554) 227 #define MPR(port) (BASE_IO_ADDR + 0x0558) 228 #define TPAUSER(port) (BASE_IO_ADDR + 0x0564) 229 #define GECMR(port) (BASE_IO_ADDR + 0x05b0) 230 #define MAHR(port) (BASE_IO_ADDR + 0x05C0) 231 #define MALR(port) (BASE_IO_ADDR + 0x05C8) 232 #define RMII_MII(port) (BASE_IO_ADDR + 0x0790) 233 234 #endif 235 236 /* 237 * Register's bits 238 * Copy from Linux driver source code 239 */ 240 #if defined(SH_ETH_TYPE_GETHER) 241 /* EDSR */ 242 enum EDSR_BIT { 243 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 244 }; 245 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 246 #endif 247 248 /* EDMR */ 249 enum DMAC_M_BIT { 250 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 251 #if defined(SH_ETH_TYPE_GETHER) 252 EDMR_SRST = 0x03, /* Receive/Send reset */ 253 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 254 EDMR_EL = 0x40, /* Litte endian */ 255 #elif defined(SH_ETH_TYPE_ETHER) 256 EDMR_SRST = 0x01, 257 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 258 EDMR_EL = 0x40, /* Litte endian */ 259 #else 260 EDMR_SRST = 0x01, 261 #endif 262 }; 263 264 /* RFLR */ 265 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 266 267 /* EDTRR */ 268 enum DMAC_T_BIT { 269 #if defined(SH_ETH_TYPE_GETHER) 270 EDTRR_TRNS = 0x03, 271 #else 272 EDTRR_TRNS = 0x01, 273 #endif 274 }; 275 276 /* GECMR */ 277 enum GECMR_BIT { 278 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 279 }; 280 281 /* EDRRR*/ 282 enum EDRRR_R_BIT { 283 EDRRR_R = 0x01, 284 }; 285 286 /* TPAUSER */ 287 enum TPAUSER_BIT { 288 TPAUSER_TPAUSE = 0x0000ffff, 289 TPAUSER_UNLIMITED = 0, 290 }; 291 292 /* BCFR */ 293 enum BCFR_BIT { 294 BCFR_RPAUSE = 0x0000ffff, 295 BCFR_UNLIMITED = 0, 296 }; 297 298 /* PIR */ 299 enum PIR_BIT { 300 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 301 }; 302 303 /* PSR */ 304 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 305 306 /* EESR */ 307 enum EESR_BIT { 308 309 #if defined(SH_ETH_TYPE_ETHER) 310 EESR_TWB = 0x40000000, 311 #else 312 EESR_TWB = 0xC0000000, 313 EESR_TC1 = 0x20000000, 314 EESR_TUC = 0x10000000, 315 EESR_ROC = 0x80000000, 316 #endif 317 EESR_TABT = 0x04000000, 318 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 319 #if defined(SH_ETH_TYPE_ETHER) 320 EESR_ADE = 0x00800000, 321 #endif 322 EESR_ECI = 0x00400000, 323 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 324 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 325 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 326 #if defined(SH_ETH_TYPE_ETHER) 327 EESR_CND = 0x00000800, 328 #endif 329 EESR_DLC = 0x00000400, 330 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 331 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 332 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 333 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 334 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 335 }; 336 337 338 #if defined(SH_ETH_TYPE_GETHER) 339 # define TX_CHECK (EESR_TC1 | EESR_FTC) 340 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 341 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 342 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 343 344 #else 345 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 346 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 347 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 348 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 349 #endif 350 351 /* EESIPR */ 352 enum DMAC_IM_BIT { 353 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 354 DMAC_M_RABT = 0x02000000, 355 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 356 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 357 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 358 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 359 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 360 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 361 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 362 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 363 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 364 DMAC_M_RINT1 = 0x00000001, 365 }; 366 367 /* Receive descriptor bit */ 368 enum RD_STS_BIT { 369 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 370 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 371 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 372 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 373 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 374 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 375 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 376 RD_RFS1 = 0x00000001, 377 }; 378 #define RDF1ST RD_RFP1 379 #define RDFEND RD_RFP0 380 #define RD_RFP (RD_RFP1|RD_RFP0) 381 382 /* RDFFR*/ 383 enum RDFFR_BIT { 384 RDFFR_RDLF = 0x01, 385 }; 386 387 /* FCFTR */ 388 enum FCFTR_BIT { 389 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 390 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 391 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 392 }; 393 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 394 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 395 396 /* Transfer descriptor bit */ 397 enum TD_STS_BIT { 398 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) 399 TD_TACT = 0x80000000, 400 #else 401 TD_TACT = 0x7fffffff, 402 #endif 403 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 404 TD_TFP0 = 0x10000000, 405 }; 406 #define TDF1ST TD_TFP1 407 #define TDFEND TD_TFP0 408 #define TD_TFP (TD_TFP1|TD_TFP0) 409 410 /* RMCR */ 411 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 412 /* ECMR */ 413 enum FELIC_MODE_BIT { 414 #if defined(SH_ETH_TYPE_GETHER) 415 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, 416 ECMR_RZPF = 0x00100000, 417 #endif 418 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 419 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 420 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 421 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 422 ECMR_PRM = 0x00000001, 423 #ifdef CONFIG_CPU_SH7724 424 ECMR_RTM = 0x00000010, 425 #endif 426 427 }; 428 429 #if defined(SH_ETH_TYPE_GETHER) 430 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ 431 ECMR_TXF | ECMR_MCT) 432 #elif defined(SH_ETH_TYPE_ETHER) 433 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) 434 #else 435 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 436 #endif 437 438 /* ECSR */ 439 enum ECSR_STATUS_BIT { 440 #if defined(SH_ETH_TYPE_ETHER) 441 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 442 #endif 443 ECSR_LCHNG = 0x04, 444 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 445 }; 446 447 #if defined(SH_ETH_TYPE_GETHER) 448 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 449 #else 450 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 451 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 452 #endif 453 454 /* ECSIPR */ 455 enum ECSIPR_STATUS_MASK_BIT { 456 #if defined(SH_ETH_TYPE_ETHER) 457 ECSIPR_BRCRXIP = 0x20, 458 ECSIPR_PSRTOIP = 0x10, 459 #elif defined(SH_ETY_TYPE_GETHER) 460 ECSIPR_PSRTOIP = 0x10, 461 ECSIPR_PHYIP = 0x08, 462 #endif 463 ECSIPR_LCHNGIP = 0x04, 464 ECSIPR_MPDIP = 0x02, 465 ECSIPR_ICDIP = 0x01, 466 }; 467 468 #if defined(SH_ETH_TYPE_GETHER) 469 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 470 #else 471 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 472 ECSIPR_ICDIP | ECSIPR_MPDIP) 473 #endif 474 475 /* APR */ 476 enum APR_BIT { 477 APR_AP = 0x00000004, 478 }; 479 480 /* MPR */ 481 enum MPR_BIT { 482 MPR_MP = 0x00000006, 483 }; 484 485 /* TRSCER */ 486 enum DESC_I_BIT { 487 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 488 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 489 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 490 DESC_I_RINT1 = 0x0001, 491 }; 492 493 /* RPADIR */ 494 enum RPADIR_BIT { 495 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 496 RPADIR_PADR = 0x0003f, 497 }; 498 499 #if defined(SH_ETH_TYPE_GETHER) 500 # define RPADIR_INIT (0x00) 501 #else 502 # define RPADIR_INIT (RPADIR_PADS1) 503 #endif 504 505 /* FDR */ 506 enum FIFO_SIZE_BIT { 507 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 508 }; 509