1 /* 2 * sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler. 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (c) 2008 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <asm/types.h> 24 25 #define SHETHER_NAME "sh_eth" 26 27 /* Malloc returns addresses in the P1 area (cacheable). However we need to 28 use area P2 (non-cacheable) */ 29 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 30 31 /* The ethernet controller needs to use physical addresses */ 32 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 33 34 /* Number of supported ports */ 35 #define MAX_PORT_NUM 2 36 37 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 38 buffers must be a multiple of 32 bytes */ 39 #define MAX_BUF_SIZE (48 * 32) 40 41 /* The number of tx descriptors must be large enough to point to 5 or more 42 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 43 We use one descriptor per frame */ 44 #define NUM_TX_DESC 8 45 46 /* The size of the tx descriptor is determined by how much padding is used. 47 4, 20, or 52 bytes of padding can be used */ 48 #define TX_DESC_PADDING 4 49 #define TX_DESC_SIZE (12 + TX_DESC_PADDING) 50 51 /* Tx descriptor. We always use 4 bytes of padding */ 52 struct tx_desc_s { 53 volatile u32 td0; 54 u32 td1; 55 u32 td2; /* Buffer start */ 56 u32 padding; 57 }; 58 59 /* There is no limitation in the number of rx descriptors */ 60 #define NUM_RX_DESC 8 61 62 /* The size of the rx descriptor is determined by how much padding is used. 63 4, 20, or 52 bytes of padding can be used */ 64 #define RX_DESC_PADDING 4 65 #define RX_DESC_SIZE (12 + RX_DESC_PADDING) 66 67 /* Rx descriptor. We always use 4 bytes of padding */ 68 struct rx_desc_s { 69 volatile u32 rd0; 70 volatile u32 rd1; 71 u32 rd2; /* Buffer start */ 72 u32 padding; 73 }; 74 75 struct port_info_s { 76 struct tx_desc_s *tx_desc_malloc; 77 struct tx_desc_s *tx_desc_base; 78 struct tx_desc_s *tx_desc_cur; 79 struct rx_desc_s *rx_desc_malloc; 80 struct rx_desc_s *rx_desc_base; 81 struct rx_desc_s *rx_desc_cur; 82 u8 *rx_buf_malloc; 83 u8 *rx_buf_base; 84 u8 mac_addr[6]; 85 u8 phy_addr; 86 }; 87 88 struct dev_info_s { 89 int port; 90 struct port_info_s port_info[MAX_PORT_NUM]; 91 }; 92 93 /* Register Address */ 94 #define BASE_IO_ADDR 0xfee00000 95 96 #define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) 97 98 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) 99 #define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014) 100 #define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) 101 #define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c) 102 103 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) 104 #define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034) 105 #define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) 106 #define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c) 107 108 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400) 109 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408) 110 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410) 111 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428) 112 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430) 113 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438) 114 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448) 115 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450) 116 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458) 117 #define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460) 118 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468) 119 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500) 120 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508) 121 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518) 122 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520) 123 #define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c) 124 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554) 125 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558) 126 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564) 127 #define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0) 128 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) 129 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) 130 131 /* 132 * Register's bits 133 * Copy from Linux driver source code 134 */ 135 #ifdef CONFIG_CPU_SH7763 136 /* EDSR */ 137 enum EDSR_BIT { 138 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 139 }; 140 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 141 #endif 142 143 /* EDMR */ 144 enum DMAC_M_BIT { 145 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 146 #ifdef CONFIG_CPU_SH7763 147 EDMR_SRST = 0x03, 148 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 149 EDMR_EL = 0x40, /* Litte endian */ 150 #else /* CONFIG_CPU_SH7763 */ 151 EDMR_SRST = 0x01, 152 #endif 153 }; 154 155 /* RFLR */ 156 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 157 158 /* EDTRR */ 159 enum DMAC_T_BIT { 160 #ifdef CONFIG_CPU_SH7763 161 EDTRR_TRNS = 0x03, 162 #else 163 EDTRR_TRNS = 0x01, 164 #endif 165 }; 166 167 /* GECMR */ 168 enum GECMR_BIT { 169 GECMR_1000B = 0x01, GECMR_100B = 0x40, GECMR_10B = 0x00, 170 }; 171 172 /* EDRRR*/ 173 enum EDRRR_R_BIT { 174 EDRRR_R = 0x01, 175 }; 176 177 /* TPAUSER */ 178 enum TPAUSER_BIT { 179 TPAUSER_TPAUSE = 0x0000ffff, 180 TPAUSER_UNLIMITED = 0, 181 }; 182 183 /* BCFR */ 184 enum BCFR_BIT { 185 BCFR_RPAUSE = 0x0000ffff, 186 BCFR_UNLIMITED = 0, 187 }; 188 189 /* PIR */ 190 enum PIR_BIT { 191 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 192 }; 193 194 /* PSR */ 195 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 196 197 /* EESR */ 198 enum EESR_BIT { 199 #ifndef CONFIG_CPU_SH7763 200 EESR_TWB = 0x40000000, 201 #else 202 EESR_TWB = 0xC0000000, 203 EESR_TC1 = 0x20000000, 204 EESR_TUC = 0x10000000, 205 EESR_ROC = 0x80000000, 206 #endif 207 EESR_TABT = 0x04000000, 208 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 209 #ifndef CONFIG_CPU_SH7763 210 EESR_ADE = 0x00800000, 211 #endif 212 EESR_ECI = 0x00400000, 213 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 214 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 215 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 216 #ifndef CONFIG_CPU_SH7763 217 EESR_CND = 0x00000800, 218 #endif 219 EESR_DLC = 0x00000400, 220 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 221 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 222 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 223 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 224 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 225 }; 226 227 228 #ifdef CONFIG_CPU_SH7763 229 # define TX_CHECK (EESR_TC1 | EESR_FTC) 230 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 231 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 232 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 233 234 #else 235 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 236 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 237 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 238 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 239 #endif 240 241 /* EESIPR */ 242 enum DMAC_IM_BIT { 243 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 244 DMAC_M_RABT = 0x02000000, 245 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 246 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 247 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 248 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 249 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 250 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 251 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 252 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 253 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 254 DMAC_M_RINT1 = 0x00000001, 255 }; 256 257 /* Receive descriptor bit */ 258 enum RD_STS_BIT { 259 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 260 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 261 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 262 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 263 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 264 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 265 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 266 RD_RFS1 = 0x00000001, 267 }; 268 #define RDF1ST RD_RFP1 269 #define RDFEND RD_RFP0 270 #define RD_RFP (RD_RFP1|RD_RFP0) 271 272 /* RDFFR*/ 273 enum RDFFR_BIT { 274 RDFFR_RDLF = 0x01, 275 }; 276 277 /* FCFTR */ 278 enum FCFTR_BIT { 279 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 280 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 281 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 282 }; 283 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 284 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 285 286 /* Transfer descriptor bit */ 287 enum TD_STS_BIT { 288 #ifdef CONFIG_CPU_SH7763 289 TD_TACT = 0x80000000, 290 #else 291 TD_TACT = 0x7fffffff, 292 #endif 293 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 294 TD_TFP0 = 0x10000000, 295 }; 296 #define TDF1ST TD_TFP1 297 #define TDFEND TD_TFP0 298 #define TD_TFP (TD_TFP1|TD_TFP0) 299 300 /* RMCR */ 301 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 302 /* ECMR */ 303 enum FELIC_MODE_BIT { 304 #ifdef CONFIG_CPU_SH7763 305 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, 306 ECMR_RZPF = 0x00100000, 307 #endif 308 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 309 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 310 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 311 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 312 ECMR_PRM = 0x00000001, 313 }; 314 315 #ifdef CONFIG_CPU_SH7763 316 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ 317 ECMR_TXF | ECMR_MCT) 318 #else 319 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT) 320 #endif 321 322 /* ECSR */ 323 enum ECSR_STATUS_BIT { 324 #ifndef CONFIG_CPU_SH7763 325 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 326 #endif 327 ECSR_LCHNG = 0x04, 328 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 329 }; 330 331 #ifdef CONFIG_CPU_SH7763 332 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 333 #else 334 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 335 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 336 #endif 337 338 /* ECSIPR */ 339 enum ECSIPR_STATUS_MASK_BIT { 340 #ifndef CONFIG_CPU_SH7763 341 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, 342 #endif 343 ECSIPR_LCHNGIP = 0x04, 344 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, 345 }; 346 347 #ifdef CONFIG_CPU_SH7763 348 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 349 #else 350 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 351 ECSIPR_ICDIP | ECSIPR_MPDIP) 352 #endif 353 354 /* APR */ 355 enum APR_BIT { 356 APR_AP = 0x00000004, 357 }; 358 359 /* MPR */ 360 enum MPR_BIT { 361 MPR_MP = 0x00000006, 362 }; 363 364 /* TRSCER */ 365 enum DESC_I_BIT { 366 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 367 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 368 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 369 DESC_I_RINT1 = 0x0001, 370 }; 371 372 /* RPADIR */ 373 enum RPADIR_BIT { 374 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 375 RPADIR_PADR = 0x0003f, 376 }; 377 378 #ifdef CONFIG_CPU_SH7763 379 # define RPADIR_INIT (0x00) 380 #else 381 # define RPADIR_INIT (RPADIR_PADS1) 382 #endif 383 384 /* FDR */ 385 enum FIFO_SIZE_BIT { 386 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 387 }; 388 389 enum PHY_OFFSETS { 390 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, 391 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6, 392 PHY_16 = 16, 393 }; 394 395 /* PHY_CTRL */ 396 enum PHY_CTRL_BIT { 397 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000, 398 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400, 399 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080, 400 }; 401 #define DM9161_PHY_C_ANEGEN 0 /* auto nego special */ 402 403 /* PHY_STAT */ 404 enum PHY_STAT_BIT { 405 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000, 406 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020, 407 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004, 408 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001, 409 }; 410 411 /* PHY_ANA */ 412 enum PHY_ANA_BIT { 413 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000, 414 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100, 415 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020, 416 PHY_A_SEL = 0x001e, 417 PHY_A_EXT = 0x0001, 418 }; 419 420 /* PHY_ANL */ 421 enum PHY_ANL_BIT { 422 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000, 423 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100, 424 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020, 425 PHY_L_SEL = 0x001f, 426 }; 427 428 /* PHY_ANE */ 429 enum PHY_ANE_BIT { 430 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004, 431 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001, 432 }; 433 434 /* DM9161 */ 435 enum PHY_16_BIT { 436 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000, 437 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800, 438 PHY_16_TXselect = 0x0400, 439 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100, 440 PHY_16_Force100LNK = 0x0080, 441 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020, 442 PHY_16_RPDCTR_EN = 0x0010, 443 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004, 444 PHY_16_Sleepmode = 0x0002, 445 PHY_16_RemoteLoopOut = 0x0001, 446 }; 447