1 /* 2 * sh_eth.h - Driver for Renesas SuperH ethernet controler. 3 * 4 * Copyright (C) 2008, 2011 Renesas Solutions Corp. 5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <netdev.h> 24 #include <asm/types.h> 25 26 #define SHETHER_NAME "sh_eth" 27 28 /* Malloc returns addresses in the P1 area (cacheable). However we need to 29 use area P2 (non-cacheable) */ 30 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) 31 32 /* The ethernet controller needs to use physical addresses */ 33 #if defined(CONFIG_SH_32BIT) 34 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) 35 #else 36 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) 37 #endif 38 39 /* Number of supported ports */ 40 #define MAX_PORT_NUM 2 41 42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx 43 buffers must be a multiple of 32 bytes */ 44 #define MAX_BUF_SIZE (48 * 32) 45 46 /* The number of tx descriptors must be large enough to point to 5 or more 47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed. 48 We use one descriptor per frame */ 49 #define NUM_TX_DESC 8 50 51 /* The size of the tx descriptor is determined by how much padding is used. 52 4, 20, or 52 bytes of padding can be used */ 53 #define TX_DESC_PADDING 4 54 #define TX_DESC_SIZE (12 + TX_DESC_PADDING) 55 56 /* Tx descriptor. We always use 3 bytes of padding */ 57 struct tx_desc_s { 58 volatile u32 td0; 59 u32 td1; 60 u32 td2; /* Buffer start */ 61 u32 padding; 62 }; 63 64 /* There is no limitation in the number of rx descriptors */ 65 #define NUM_RX_DESC 8 66 67 /* The size of the rx descriptor is determined by how much padding is used. 68 4, 20, or 52 bytes of padding can be used */ 69 #define RX_DESC_PADDING 4 70 #define RX_DESC_SIZE (12 + RX_DESC_PADDING) 71 72 /* Rx descriptor. We always use 4 bytes of padding */ 73 struct rx_desc_s { 74 volatile u32 rd0; 75 volatile u32 rd1; 76 u32 rd2; /* Buffer start */ 77 u32 padding; 78 }; 79 80 struct sh_eth_info { 81 struct tx_desc_s *tx_desc_malloc; 82 struct tx_desc_s *tx_desc_base; 83 struct tx_desc_s *tx_desc_cur; 84 struct rx_desc_s *rx_desc_malloc; 85 struct rx_desc_s *rx_desc_base; 86 struct rx_desc_s *rx_desc_cur; 87 u8 *rx_buf_malloc; 88 u8 *rx_buf_base; 89 u8 mac_addr[6]; 90 u8 phy_addr; 91 struct eth_device *dev; 92 struct phy_device *phydev; 93 }; 94 95 struct sh_eth_dev { 96 int port; 97 struct sh_eth_info port_info[MAX_PORT_NUM]; 98 }; 99 100 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */ 101 enum { 102 /* E-DMAC registers */ 103 EDSR = 0, 104 EDMR, 105 EDTRR, 106 EDRRR, 107 EESR, 108 EESIPR, 109 TDLAR, 110 TDFAR, 111 TDFXR, 112 TDFFR, 113 RDLAR, 114 RDFAR, 115 RDFXR, 116 RDFFR, 117 TRSCER, 118 RMFCR, 119 TFTR, 120 FDR, 121 RMCR, 122 EDOCR, 123 TFUCR, 124 RFOCR, 125 FCFTR, 126 RPADIR, 127 TRIMD, 128 RBWAR, 129 TBRAR, 130 131 /* Ether registers */ 132 ECMR, 133 ECSR, 134 ECSIPR, 135 PIR, 136 PSR, 137 RDMLR, 138 PIPR, 139 RFLR, 140 IPGR, 141 APR, 142 MPR, 143 PFTCR, 144 PFRCR, 145 RFCR, 146 RFCF, 147 TPAUSER, 148 TPAUSECR, 149 BCFR, 150 BCFRR, 151 GECMR, 152 BCULR, 153 MAHR, 154 MALR, 155 TROCR, 156 CDCR, 157 LCCR, 158 CNDCR, 159 CEFCR, 160 FRECR, 161 TSFRCR, 162 TLFRCR, 163 CERCR, 164 CEECR, 165 MAFCR, 166 RTRATE, 167 CSMR, 168 RMII_MII, 169 170 /* This value must be written at last. */ 171 SH_ETH_MAX_REGISTER_OFFSET, 172 }; 173 174 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 175 [EDSR] = 0x0000, 176 [EDMR] = 0x0400, 177 [EDTRR] = 0x0408, 178 [EDRRR] = 0x0410, 179 [EESR] = 0x0428, 180 [EESIPR] = 0x0430, 181 [TDLAR] = 0x0010, 182 [TDFAR] = 0x0014, 183 [TDFXR] = 0x0018, 184 [TDFFR] = 0x001c, 185 [RDLAR] = 0x0030, 186 [RDFAR] = 0x0034, 187 [RDFXR] = 0x0038, 188 [RDFFR] = 0x003c, 189 [TRSCER] = 0x0438, 190 [RMFCR] = 0x0440, 191 [TFTR] = 0x0448, 192 [FDR] = 0x0450, 193 [RMCR] = 0x0458, 194 [RPADIR] = 0x0460, 195 [FCFTR] = 0x0468, 196 [CSMR] = 0x04E4, 197 198 [ECMR] = 0x0500, 199 [ECSR] = 0x0510, 200 [ECSIPR] = 0x0518, 201 [PIR] = 0x0520, 202 [PSR] = 0x0528, 203 [PIPR] = 0x052c, 204 [RFLR] = 0x0508, 205 [APR] = 0x0554, 206 [MPR] = 0x0558, 207 [PFTCR] = 0x055c, 208 [PFRCR] = 0x0560, 209 [TPAUSER] = 0x0564, 210 [GECMR] = 0x05b0, 211 [BCULR] = 0x05b4, 212 [MAHR] = 0x05c0, 213 [MALR] = 0x05c8, 214 [TROCR] = 0x0700, 215 [CDCR] = 0x0708, 216 [LCCR] = 0x0710, 217 [CEFCR] = 0x0740, 218 [FRECR] = 0x0748, 219 [TSFRCR] = 0x0750, 220 [TLFRCR] = 0x0758, 221 [RFCR] = 0x0760, 222 [CERCR] = 0x0768, 223 [CEECR] = 0x0770, 224 [MAFCR] = 0x0778, 225 [RMII_MII] = 0x0790, 226 }; 227 228 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 229 [ECMR] = 0x0100, 230 [RFLR] = 0x0108, 231 [ECSR] = 0x0110, 232 [ECSIPR] = 0x0118, 233 [PIR] = 0x0120, 234 [PSR] = 0x0128, 235 [RDMLR] = 0x0140, 236 [IPGR] = 0x0150, 237 [APR] = 0x0154, 238 [MPR] = 0x0158, 239 [TPAUSER] = 0x0164, 240 [RFCF] = 0x0160, 241 [TPAUSECR] = 0x0168, 242 [BCFRR] = 0x016c, 243 [MAHR] = 0x01c0, 244 [MALR] = 0x01c8, 245 [TROCR] = 0x01d0, 246 [CDCR] = 0x01d4, 247 [LCCR] = 0x01d8, 248 [CNDCR] = 0x01dc, 249 [CEFCR] = 0x01e4, 250 [FRECR] = 0x01e8, 251 [TSFRCR] = 0x01ec, 252 [TLFRCR] = 0x01f0, 253 [RFCR] = 0x01f4, 254 [MAFCR] = 0x01f8, 255 [RTRATE] = 0x01fc, 256 257 [EDMR] = 0x0000, 258 [EDTRR] = 0x0008, 259 [EDRRR] = 0x0010, 260 [TDLAR] = 0x0018, 261 [RDLAR] = 0x0020, 262 [EESR] = 0x0028, 263 [EESIPR] = 0x0030, 264 [TRSCER] = 0x0038, 265 [RMFCR] = 0x0040, 266 [TFTR] = 0x0048, 267 [FDR] = 0x0050, 268 [RMCR] = 0x0058, 269 [TFUCR] = 0x0064, 270 [RFOCR] = 0x0068, 271 [FCFTR] = 0x0070, 272 [RPADIR] = 0x0078, 273 [TRIMD] = 0x007c, 274 [RBWAR] = 0x00c8, 275 [RDFAR] = 0x00cc, 276 [TBRAR] = 0x00d4, 277 [TDFAR] = 0x00d8, 278 }; 279 280 /* Register Address */ 281 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) 282 #define SH_ETH_TYPE_GETHER 283 #define BASE_IO_ADDR 0xfee00000 284 #elif defined(CONFIG_CPU_SH7757) 285 #if defined(CONFIG_SH_ETHER_USE_GETHER) 286 #define SH_ETH_TYPE_GETHER 287 #define BASE_IO_ADDR 0xfee00000 288 #else 289 #define SH_ETH_TYPE_ETHER 290 #define BASE_IO_ADDR 0xfef00000 291 #endif 292 #elif defined(CONFIG_CPU_SH7724) 293 #define SH_ETH_TYPE_ETHER 294 #define BASE_IO_ADDR 0xA4600000 295 #endif 296 297 /* 298 * Register's bits 299 * Copy from Linux driver source code 300 */ 301 #if defined(SH_ETH_TYPE_GETHER) 302 /* EDSR */ 303 enum EDSR_BIT { 304 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 305 }; 306 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR) 307 #endif 308 309 /* EDMR */ 310 enum DMAC_M_BIT { 311 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, 312 #if defined(SH_ETH_TYPE_GETHER) 313 EDMR_SRST = 0x03, /* Receive/Send reset */ 314 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 315 EDMR_EL = 0x40, /* Litte endian */ 316 #elif defined(SH_ETH_TYPE_ETHER) 317 EDMR_SRST = 0x01, 318 EMDR_DESC_R = 0x30, /* Descriptor reserve size */ 319 EDMR_EL = 0x40, /* Litte endian */ 320 #else 321 EDMR_SRST = 0x01, 322 #endif 323 }; 324 325 /* RFLR */ 326 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ 327 328 /* EDTRR */ 329 enum DMAC_T_BIT { 330 #if defined(SH_ETH_TYPE_GETHER) 331 EDTRR_TRNS = 0x03, 332 #else 333 EDTRR_TRNS = 0x01, 334 #endif 335 }; 336 337 /* GECMR */ 338 enum GECMR_BIT { 339 #if defined(CONFIG_CPU_SH7757) 340 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, 341 #else 342 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, 343 #endif 344 }; 345 346 /* EDRRR*/ 347 enum EDRRR_R_BIT { 348 EDRRR_R = 0x01, 349 }; 350 351 /* TPAUSER */ 352 enum TPAUSER_BIT { 353 TPAUSER_TPAUSE = 0x0000ffff, 354 TPAUSER_UNLIMITED = 0, 355 }; 356 357 /* BCFR */ 358 enum BCFR_BIT { 359 BCFR_RPAUSE = 0x0000ffff, 360 BCFR_UNLIMITED = 0, 361 }; 362 363 /* PIR */ 364 enum PIR_BIT { 365 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01, 366 }; 367 368 /* PSR */ 369 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; 370 371 /* EESR */ 372 enum EESR_BIT { 373 374 #if defined(SH_ETH_TYPE_ETHER) 375 EESR_TWB = 0x40000000, 376 #else 377 EESR_TWB = 0xC0000000, 378 EESR_TC1 = 0x20000000, 379 EESR_TUC = 0x10000000, 380 EESR_ROC = 0x80000000, 381 #endif 382 EESR_TABT = 0x04000000, 383 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 384 #if defined(SH_ETH_TYPE_ETHER) 385 EESR_ADE = 0x00800000, 386 #endif 387 EESR_ECI = 0x00400000, 388 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 389 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 390 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 391 #if defined(SH_ETH_TYPE_ETHER) 392 EESR_CND = 0x00000800, 393 #endif 394 EESR_DLC = 0x00000400, 395 EESR_CD = 0x00000200, EESR_RTO = 0x00000100, 396 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040, 397 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010, 398 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004, 399 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, 400 }; 401 402 403 #if defined(SH_ETH_TYPE_GETHER) 404 # define TX_CHECK (EESR_TC1 | EESR_FTC) 405 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 406 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) 407 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE) 408 409 #else 410 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO) 411 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 412 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 413 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE) 414 #endif 415 416 /* EESIPR */ 417 enum DMAC_IM_BIT { 418 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000, 419 DMAC_M_RABT = 0x02000000, 420 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000, 421 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000, 422 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000, 423 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000, 424 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800, 425 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200, 426 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080, 427 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008, 428 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002, 429 DMAC_M_RINT1 = 0x00000001, 430 }; 431 432 /* Receive descriptor bit */ 433 enum RD_STS_BIT { 434 RD_RACT = 0x80000000, RD_RDLE = 0x40000000, 435 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000, 436 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 437 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 438 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 439 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008, 440 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 441 RD_RFS1 = 0x00000001, 442 }; 443 #define RDF1ST RD_RFP1 444 #define RDFEND RD_RFP0 445 #define RD_RFP (RD_RFP1|RD_RFP0) 446 447 /* RDFFR*/ 448 enum RDFFR_BIT { 449 RDFFR_RDLF = 0x01, 450 }; 451 452 /* FCFTR */ 453 enum FCFTR_BIT { 454 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, 455 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004, 456 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001, 457 }; 458 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0) 459 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0) 460 461 /* Transfer descriptor bit */ 462 enum TD_STS_BIT { 463 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) 464 TD_TACT = 0x80000000, 465 #else 466 TD_TACT = 0x7fffffff, 467 #endif 468 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 469 TD_TFP0 = 0x10000000, 470 }; 471 #define TDF1ST TD_TFP1 472 #define TDFEND TD_TFP0 473 #define TD_TFP (TD_TFP1|TD_TFP0) 474 475 /* RMCR */ 476 enum RECV_RST_BIT { RMCR_RST = 0x01, }; 477 /* ECMR */ 478 enum FELIC_MODE_BIT { 479 #if defined(SH_ETH_TYPE_GETHER) 480 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, 481 ECMR_RZPF = 0x00100000, 482 #endif 483 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 484 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 485 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 486 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002, 487 ECMR_PRM = 0x00000001, 488 #ifdef CONFIG_CPU_SH7724 489 ECMR_RTM = 0x00000010, 490 #endif 491 492 }; 493 494 #if defined(SH_ETH_TYPE_GETHER) 495 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ 496 ECMR_TXF | ECMR_MCT) 497 #elif defined(SH_ETH_TYPE_ETHER) 498 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) 499 #else 500 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) 501 #endif 502 503 /* ECSR */ 504 enum ECSR_STATUS_BIT { 505 #if defined(SH_ETH_TYPE_ETHER) 506 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, 507 #endif 508 ECSR_LCHNG = 0x04, 509 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 510 }; 511 512 #if defined(SH_ETH_TYPE_GETHER) 513 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) 514 #else 515 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ 516 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP) 517 #endif 518 519 /* ECSIPR */ 520 enum ECSIPR_STATUS_MASK_BIT { 521 #if defined(SH_ETH_TYPE_ETHER) 522 ECSIPR_BRCRXIP = 0x20, 523 ECSIPR_PSRTOIP = 0x10, 524 #elif defined(SH_ETY_TYPE_GETHER) 525 ECSIPR_PSRTOIP = 0x10, 526 ECSIPR_PHYIP = 0x08, 527 #endif 528 ECSIPR_LCHNGIP = 0x04, 529 ECSIPR_MPDIP = 0x02, 530 ECSIPR_ICDIP = 0x01, 531 }; 532 533 #if defined(SH_ETH_TYPE_GETHER) 534 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) 535 #else 536 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ 537 ECSIPR_ICDIP | ECSIPR_MPDIP) 538 #endif 539 540 /* APR */ 541 enum APR_BIT { 542 APR_AP = 0x00000004, 543 }; 544 545 /* MPR */ 546 enum MPR_BIT { 547 MPR_MP = 0x00000006, 548 }; 549 550 /* TRSCER */ 551 enum DESC_I_BIT { 552 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200, 553 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010, 554 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002, 555 DESC_I_RINT1 = 0x0001, 556 }; 557 558 /* RPADIR */ 559 enum RPADIR_BIT { 560 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000, 561 RPADIR_PADR = 0x0003f, 562 }; 563 564 #if defined(SH_ETH_TYPE_GETHER) 565 # define RPADIR_INIT (0x00) 566 #else 567 # define RPADIR_INIT (RPADIR_PADS1) 568 #endif 569 570 /* FDR */ 571 enum FIFO_SIZE_BIT { 572 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 573 }; 574 575 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, 576 int enum_index) 577 { 578 #if defined(SH_ETH_TYPE_GETHER) 579 const u16 *reg_offset = sh_eth_offset_gigabit; 580 #elif defined(SH_ETH_TYPE_ETHER) 581 const u16 *reg_offset = sh_eth_offset_fast_sh4; 582 #else 583 #error 584 #endif 585 return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; 586 } 587 588 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data, 589 int enum_index) 590 { 591 outl(data, sh_eth_reg_addr(eth, enum_index)); 592 } 593 594 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth, 595 int enum_index) 596 { 597 return inl(sh_eth_reg_addr(eth, enum_index)); 598 } 599