1 /* 2 * sh_eth.c - Driver for Renesas SH7763's ethernet controler. 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (c) 2008 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <config.h> 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <asm/errno.h> 29 #include <asm/io.h> 30 31 #include "sh_eth.h" 32 33 #ifndef CONFIG_SH_ETHER_USE_PORT 34 # error "Please define CONFIG_SH_ETHER_USE_PORT" 35 #endif 36 #ifndef CONFIG_SH_ETHER_PHY_ADDR 37 # error "Please define CONFIG_SH_ETHER_PHY_ADDR" 38 #endif 39 #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK 40 #define flush_cache_wback(addr, len) \ 41 dcache_wback_range((u32)addr, (u32)(addr + len - 1)) 42 #else 43 #define flush_cache_wback(...) 44 #endif 45 46 #define SH_ETH_PHY_DELAY 50000 47 48 /* 49 * Bits are written to the PHY serially using the 50 * PIR register, just like a bit banger. 51 */ 52 static void sh_eth_mii_write_phy_bits(int port, u32 val, int len) 53 { 54 int i; 55 u32 pir; 56 57 /* Bit positions is 1 less than the number of bits */ 58 for (i = len - 1; i >= 0; i--) { 59 /* Write direction, bit to write, clock is low */ 60 pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); 61 outl(pir, PIR(port)); 62 udelay(1); 63 /* Write direction, bit to write, clock is high */ 64 pir = 3 | ((val & 1 << i) ? 1 << 2 : 0); 65 outl(pir, PIR(port)); 66 udelay(1); 67 /* Write direction, bit to write, clock is low */ 68 pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); 69 outl(pir, PIR(port)); 70 udelay(1); 71 } 72 } 73 74 static void sh_eth_mii_bus_release(int port) 75 { 76 /* Read direction, clock is low */ 77 outl(0, PIR(port)); 78 udelay(1); 79 /* Read direction, clock is high */ 80 outl(1, PIR(port)); 81 udelay(1); 82 /* Read direction, clock is low */ 83 outl(0, PIR(port)); 84 udelay(1); 85 } 86 87 static void sh_eth_mii_ind_bus_release(int port) 88 { 89 /* Read direction, clock is low */ 90 outl(0, PIR(port)); 91 udelay(1); 92 } 93 94 static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len) 95 { 96 int i; 97 u32 pir; 98 99 *val = 0; 100 for (i = len - 1; i >= 0; i--) { 101 /* Read direction, clock is high */ 102 outl(1, PIR(port)); 103 udelay(1); 104 /* Read bit */ 105 pir = inl(PIR(port)); 106 *val |= (pir & 8) ? 1 << i : 0; 107 /* Read direction, clock is low */ 108 outl(0, PIR(port)); 109 udelay(1); 110 } 111 } 112 113 #define PHY_INIT 0xFFFFFFFF 114 #define PHY_READ 0x02 115 #define PHY_WRITE 0x01 116 /* 117 * To read a phy register, mii managements frames are sent to the phy. 118 * The frames look like this: 119 * pre (32 bits): 0xffff ffff 120 * st (2 bits): 01 121 * op (2bits): 10: read 01: write 122 * phyad (5 bits): xxxxx 123 * regad (5 bits): xxxxx 124 * ta (Bus release): 125 * data (16 bits): read data 126 */ 127 static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg) 128 { 129 u32 val; 130 131 /* Sent mii management frame */ 132 /* pre */ 133 sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); 134 /* st (start of frame) */ 135 sh_eth_mii_write_phy_bits(port, 0x1, 2); 136 /* op (code) */ 137 sh_eth_mii_write_phy_bits(port, PHY_READ, 2); 138 /* phy address */ 139 sh_eth_mii_write_phy_bits(port, phy_addr, 5); 140 /* Register to read */ 141 sh_eth_mii_write_phy_bits(port, reg, 5); 142 143 /* Bus release */ 144 sh_eth_mii_bus_release(port); 145 146 /* Read register */ 147 sh_eth_mii_read_phy_bits(port, &val, 16); 148 149 return val; 150 } 151 152 /* 153 * To write a phy register, mii managements frames are sent to the phy. 154 * The frames look like this: 155 * pre (32 bits): 0xffff ffff 156 * st (2 bits): 01 157 * op (2bits): 10: read 01: write 158 * phyad (5 bits): xxxxx 159 * regad (5 bits): xxxxx 160 * ta (2 bits): 10 161 * data (16 bits): write data 162 * idle (Independent bus release) 163 */ 164 static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val) 165 { 166 /* Sent mii management frame */ 167 /* pre */ 168 sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); 169 /* st (start of frame) */ 170 sh_eth_mii_write_phy_bits(port, 0x1, 2); 171 /* op (code) */ 172 sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2); 173 /* phy address */ 174 sh_eth_mii_write_phy_bits(port, phy_addr, 5); 175 /* Register to read */ 176 sh_eth_mii_write_phy_bits(port, reg, 5); 177 /* ta */ 178 sh_eth_mii_write_phy_bits(port, PHY_READ, 2); 179 /* Write register data */ 180 sh_eth_mii_write_phy_bits(port, val, 16); 181 182 /* Independent bus release */ 183 sh_eth_mii_ind_bus_release(port); 184 } 185 186 int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) 187 { 188 struct sh_eth_dev *eth = dev->priv; 189 int port = eth->port, ret = 0, timeout; 190 struct sh_eth_info *port_info = ð->port_info[port]; 191 192 if (!packet || len > 0xffff) { 193 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); 194 ret = -EINVAL; 195 goto err; 196 } 197 198 /* packet must be a 4 byte boundary */ 199 if ((int)packet & (4 - 1)) { 200 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); 201 ret = -EFAULT; 202 goto err; 203 } 204 205 /* Update tx descriptor */ 206 flush_cache_wback(packet, len); 207 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); 208 port_info->tx_desc_cur->td1 = len << 16; 209 /* Must preserve the end of descriptor list indication */ 210 if (port_info->tx_desc_cur->td0 & TD_TDLE) 211 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; 212 else 213 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; 214 215 /* Restart the transmitter if disabled */ 216 if (!(inl(EDTRR(port)) & EDTRR_TRNS)) 217 outl(EDTRR_TRNS, EDTRR(port)); 218 219 /* Wait until packet is transmitted */ 220 timeout = 1000; 221 while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) 222 udelay(100); 223 224 if (timeout < 0) { 225 printf(SHETHER_NAME ": transmit timeout\n"); 226 ret = -ETIMEDOUT; 227 goto err; 228 } 229 230 port_info->tx_desc_cur++; 231 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) 232 port_info->tx_desc_cur = port_info->tx_desc_base; 233 234 return ret; 235 err: 236 return ret; 237 } 238 239 int sh_eth_recv(struct eth_device *dev) 240 { 241 struct sh_eth_dev *eth = dev->priv; 242 int port = eth->port, len = 0; 243 struct sh_eth_info *port_info = ð->port_info[port]; 244 volatile u8 *packet; 245 246 /* Check if the rx descriptor is ready */ 247 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { 248 /* Check for errors */ 249 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { 250 len = port_info->rx_desc_cur->rd1 & 0xffff; 251 packet = (volatile u8 *) 252 ADDR_TO_P2(port_info->rx_desc_cur->rd2); 253 NetReceive(packet, len); 254 } 255 256 /* Make current descriptor available again */ 257 if (port_info->rx_desc_cur->rd0 & RD_RDLE) 258 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; 259 else 260 port_info->rx_desc_cur->rd0 = RD_RACT; 261 262 /* Point to the next descriptor */ 263 port_info->rx_desc_cur++; 264 if (port_info->rx_desc_cur >= 265 port_info->rx_desc_base + NUM_RX_DESC) 266 port_info->rx_desc_cur = port_info->rx_desc_base; 267 } 268 269 /* Restart the receiver if disabled */ 270 if (!(inl(EDRRR(port)) & EDRRR_R)) 271 outl(EDRRR_R, EDRRR(port)); 272 273 return len; 274 } 275 276 #define EDMR_INIT_CNT 1000 277 static int sh_eth_reset(struct sh_eth_dev *eth) 278 { 279 int port = eth->port; 280 int ret = 0, i; 281 282 /* Start e-dmac transmitter and receiver */ 283 outl(EDSR_ENALL, EDSR(port)); 284 285 /* Perform a software reset and wait for it to complete */ 286 outl(EDMR_SRST, EDMR(port)); 287 for (i = 0; i < EDMR_INIT_CNT; i++) { 288 if (!(inl(EDMR(port)) & EDMR_SRST)) 289 break; 290 udelay(1000); 291 } 292 293 if (i == EDMR_INIT_CNT) { 294 printf(SHETHER_NAME ": Software reset timeout\n"); 295 ret = -EIO; 296 } 297 298 return ret; 299 } 300 301 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) 302 { 303 int port = eth->port, i, ret = 0; 304 u32 tmp_addr; 305 struct sh_eth_info *port_info = ð->port_info[port]; 306 struct tx_desc_s *cur_tx_desc; 307 308 /* 309 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned 310 */ 311 port_info->tx_desc_malloc = malloc(NUM_TX_DESC * 312 sizeof(struct tx_desc_s) + 313 TX_DESC_SIZE - 1); 314 if (!port_info->tx_desc_malloc) { 315 printf(SHETHER_NAME ": malloc failed\n"); 316 ret = -ENOMEM; 317 goto err; 318 } 319 320 tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & 321 ~(TX_DESC_SIZE - 1)); 322 flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); 323 /* Make sure we use a P2 address (non-cacheable) */ 324 port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); 325 port_info->tx_desc_cur = port_info->tx_desc_base; 326 327 /* Initialize all descriptors */ 328 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; 329 cur_tx_desc++, i++) { 330 cur_tx_desc->td0 = 0x00; 331 cur_tx_desc->td1 = 0x00; 332 cur_tx_desc->td2 = 0x00; 333 } 334 335 /* Mark the end of the descriptors */ 336 cur_tx_desc--; 337 cur_tx_desc->td0 |= TD_TDLE; 338 339 /* Point the controller to the tx descriptor list. Must use physical 340 addresses */ 341 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); 342 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); 343 outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); 344 outl(0x01, TDFFR(port));/* Last discriptor bit */ 345 346 err: 347 return ret; 348 } 349 350 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) 351 { 352 int port = eth->port, i , ret = 0; 353 struct sh_eth_info *port_info = ð->port_info[port]; 354 struct rx_desc_s *cur_rx_desc; 355 u32 tmp_addr; 356 u8 *rx_buf; 357 358 /* 359 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned 360 */ 361 port_info->rx_desc_malloc = malloc(NUM_RX_DESC * 362 sizeof(struct rx_desc_s) + 363 RX_DESC_SIZE - 1); 364 if (!port_info->rx_desc_malloc) { 365 printf(SHETHER_NAME ": malloc failed\n"); 366 ret = -ENOMEM; 367 goto err; 368 } 369 370 tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & 371 ~(RX_DESC_SIZE - 1)); 372 flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); 373 /* Make sure we use a P2 address (non-cacheable) */ 374 port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); 375 376 port_info->rx_desc_cur = port_info->rx_desc_base; 377 378 /* 379 * Allocate rx data buffers. They must be 32 bytes aligned and in 380 * P2 area 381 */ 382 port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); 383 if (!port_info->rx_buf_malloc) { 384 printf(SHETHER_NAME ": malloc failed\n"); 385 ret = -ENOMEM; 386 goto err_buf_malloc; 387 } 388 389 tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & 390 ~(32 - 1)); 391 port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); 392 393 /* Initialize all descriptors */ 394 for (cur_rx_desc = port_info->rx_desc_base, 395 rx_buf = port_info->rx_buf_base, i = 0; 396 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { 397 cur_rx_desc->rd0 = RD_RACT; 398 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; 399 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); 400 } 401 402 /* Mark the end of the descriptors */ 403 cur_rx_desc--; 404 cur_rx_desc->rd0 |= RD_RDLE; 405 406 /* Point the controller to the rx descriptor list */ 407 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); 408 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); 409 outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); 410 outl(RDFFR_RDLF, RDFFR(port)); 411 412 return ret; 413 414 err_buf_malloc: 415 free(port_info->rx_desc_malloc); 416 port_info->rx_desc_malloc = NULL; 417 418 err: 419 return ret; 420 } 421 422 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) 423 { 424 int port = eth->port; 425 struct sh_eth_info *port_info = ð->port_info[port]; 426 427 if (port_info->tx_desc_malloc) { 428 free(port_info->tx_desc_malloc); 429 port_info->tx_desc_malloc = NULL; 430 } 431 } 432 433 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) 434 { 435 int port = eth->port; 436 struct sh_eth_info *port_info = ð->port_info[port]; 437 438 if (port_info->rx_desc_malloc) { 439 free(port_info->rx_desc_malloc); 440 port_info->rx_desc_malloc = NULL; 441 } 442 443 if (port_info->rx_buf_malloc) { 444 free(port_info->rx_buf_malloc); 445 port_info->rx_buf_malloc = NULL; 446 } 447 } 448 449 static int sh_eth_desc_init(struct sh_eth_dev *eth) 450 { 451 int ret = 0; 452 453 ret = sh_eth_tx_desc_init(eth); 454 if (ret) 455 goto err_tx_init; 456 457 ret = sh_eth_rx_desc_init(eth); 458 if (ret) 459 goto err_rx_init; 460 461 return ret; 462 err_rx_init: 463 sh_eth_tx_desc_free(eth); 464 465 err_tx_init: 466 return ret; 467 } 468 469 static int sh_eth_phy_config(struct sh_eth_dev *eth) 470 { 471 int port = eth->port, timeout, ret = 0; 472 struct sh_eth_info *port_info = ð->port_info[port]; 473 u32 val; 474 475 /* Reset phy */ 476 sh_eth_mii_write_phy_reg 477 (port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET); 478 timeout = 10; 479 while (timeout--) { 480 val = sh_eth_mii_read_phy_reg(port, 481 port_info->phy_addr, PHY_CTRL); 482 if (!(val & PHY_C_RESET)) 483 break; 484 udelay(SH_ETH_PHY_DELAY); 485 } 486 487 if (timeout < 0) { 488 printf(SHETHER_NAME ": phy reset timeout\n"); 489 ret = -EIO; 490 goto err_tout; 491 } 492 493 /* Advertise 100/10 baseT full/half duplex */ 494 sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA, 495 (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT)); 496 /* Autonegotiation, normal operation, full duplex, enable tx */ 497 sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, 498 (PHY_C_ANEGEN|PHY_C_RANEG)); 499 /* Wait for autonegotiation to complete */ 500 timeout = 100; 501 while (timeout--) { 502 val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); 503 if (val & PHY_S_ANEGC) 504 break; 505 506 udelay(SH_ETH_PHY_DELAY); 507 } 508 509 if (timeout < 0) { 510 printf(SHETHER_NAME ": phy auto-negotiation failed\n"); 511 ret = -ETIMEDOUT; 512 goto err_tout; 513 } 514 515 return ret; 516 517 err_tout: 518 return ret; 519 } 520 521 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) 522 { 523 int port = eth->port, ret = 0; 524 u32 val, phy_status; 525 struct sh_eth_info *port_info = ð->port_info[port]; 526 struct eth_device *dev = port_info->dev; 527 528 /* Configure e-dmac registers */ 529 outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); 530 outl(0, EESIPR(port)); 531 outl(0, TRSCER(port)); 532 outl(0, TFTR(port)); 533 outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); 534 outl(RMCR_RST, RMCR(port)); 535 outl(0, RPADIR(port)); 536 outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); 537 538 /* Configure e-mac registers */ 539 outl(0, ECSIPR(port)); 540 541 /* Set Mac address */ 542 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | 543 dev->enetaddr[2] << 8 | dev->enetaddr[3]; 544 outl(val, MAHR(port)); 545 546 val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; 547 outl(val, MALR(port)); 548 549 outl(RFLR_RFL_MIN, RFLR(port)); 550 outl(0, PIPR(port)); 551 outl(APR_AP, APR(port)); 552 outl(MPR_MP, MPR(port)); 553 outl(TPAUSER_TPAUSE, TPAUSER(port)); 554 555 /* Configure phy */ 556 ret = sh_eth_phy_config(eth); 557 if (ret) { 558 printf(SHETHER_NAME ": phy config timeout\n"); 559 goto err_phy_cfg; 560 } 561 /* Read phy status to finish configuring the e-mac */ 562 phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); 563 564 /* Set the transfer speed */ 565 if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { 566 printf(SHETHER_NAME ": 100Base/"); 567 outl(GECMR_100B, GECMR(port)); 568 } else { 569 printf(SHETHER_NAME ": 10Base/"); 570 outl(GECMR_10B, GECMR(port)); 571 } 572 573 /* Check if full duplex mode is supported by the phy */ 574 if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { 575 printf("Full\n"); 576 outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); 577 } else { 578 printf("Half\n"); 579 outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); 580 } 581 582 return ret; 583 584 err_phy_cfg: 585 return ret; 586 } 587 588 static void sh_eth_start(struct sh_eth_dev *eth) 589 { 590 /* 591 * Enable the e-dmac receiver only. The transmitter will be enabled when 592 * we have something to transmit 593 */ 594 outl(EDRRR_R, EDRRR(eth->port)); 595 } 596 597 static void sh_eth_stop(struct sh_eth_dev *eth) 598 { 599 outl(~EDRRR_R, EDRRR(eth->port)); 600 } 601 602 int sh_eth_init(struct eth_device *dev, bd_t *bd) 603 { 604 int ret = 0; 605 struct sh_eth_dev *eth = dev->priv; 606 607 ret = sh_eth_reset(eth); 608 if (ret) 609 goto err; 610 611 ret = sh_eth_desc_init(eth); 612 if (ret) 613 goto err; 614 615 ret = sh_eth_config(eth, bd); 616 if (ret) 617 goto err_config; 618 619 sh_eth_start(eth); 620 621 return ret; 622 623 err_config: 624 sh_eth_tx_desc_free(eth); 625 sh_eth_rx_desc_free(eth); 626 627 err: 628 return ret; 629 } 630 631 void sh_eth_halt(struct eth_device *dev) 632 { 633 struct sh_eth_dev *eth = dev->priv; 634 sh_eth_stop(eth); 635 } 636 637 int sh_eth_initialize(bd_t *bd) 638 { 639 int ret = 0; 640 struct sh_eth_dev *eth = NULL; 641 struct eth_device *dev = NULL; 642 643 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); 644 if (!eth) { 645 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 646 ret = -ENOMEM; 647 goto err; 648 } 649 650 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 651 if (!dev) { 652 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 653 ret = -ENOMEM; 654 goto err; 655 } 656 memset(dev, 0, sizeof(struct eth_device)); 657 memset(eth, 0, sizeof(struct sh_eth_dev)); 658 659 eth->port = CONFIG_SH_ETHER_USE_PORT; 660 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 661 662 dev->priv = (void *)eth; 663 dev->iobase = 0; 664 dev->init = sh_eth_init; 665 dev->halt = sh_eth_halt; 666 dev->send = sh_eth_send; 667 dev->recv = sh_eth_recv; 668 eth->port_info[eth->port].dev = dev; 669 670 sprintf(dev->name, SHETHER_NAME); 671 672 /* Register Device to EtherNet subsystem */ 673 eth_register(dev); 674 675 if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) 676 puts("Please set MAC address\n"); 677 678 return ret; 679 680 err: 681 if (dev) 682 free(dev); 683 684 if (eth) 685 free(eth); 686 687 printf(SHETHER_NAME ": Failed\n"); 688 return ret; 689 } 690