1 /* 2 * sh_eth.c - Driver for Renesas ethernet controller. 3 * 4 * Copyright (C) 2008, 2011 Renesas Solutions Corp. 5 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * Copyright (C) 2013, 2014 Renesas Electronics Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <malloc.h> 15 #include <net.h> 16 #include <netdev.h> 17 #include <miiphy.h> 18 #include <linux/errno.h> 19 #include <asm/io.h> 20 21 #ifdef CONFIG_DM_ETH 22 #include <clk.h> 23 #include <dm.h> 24 #include <linux/mii.h> 25 #include <asm/gpio.h> 26 #endif 27 28 #include "sh_eth.h" 29 30 #ifndef CONFIG_SH_ETHER_USE_PORT 31 # error "Please define CONFIG_SH_ETHER_USE_PORT" 32 #endif 33 #ifndef CONFIG_SH_ETHER_PHY_ADDR 34 # error "Please define CONFIG_SH_ETHER_PHY_ADDR" 35 #endif 36 37 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) 38 #define flush_cache_wback(addr, len) \ 39 flush_dcache_range((u32)addr, \ 40 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE))) 41 #else 42 #define flush_cache_wback(...) 43 #endif 44 45 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) 46 #define invalidate_cache(addr, len) \ 47 { \ 48 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ 49 u32 start, end; \ 50 \ 51 start = (u32)addr; \ 52 end = start + len; \ 53 start &= ~(line_size - 1); \ 54 end = ((end + line_size - 1) & ~(line_size - 1)); \ 55 \ 56 invalidate_dcache_range(start, end); \ 57 } 58 #else 59 #define invalidate_cache(...) 60 #endif 61 62 #define TIMEOUT_CNT 1000 63 64 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len) 65 { 66 int ret = 0, timeout; 67 struct sh_eth_info *port_info = ð->port_info[eth->port]; 68 69 if (!packet || len > 0xffff) { 70 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); 71 ret = -EINVAL; 72 goto err; 73 } 74 75 /* packet must be a 4 byte boundary */ 76 if ((int)packet & 3) { 77 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n" 78 , __func__); 79 ret = -EFAULT; 80 goto err; 81 } 82 83 /* Update tx descriptor */ 84 flush_cache_wback(packet, len); 85 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); 86 port_info->tx_desc_cur->td1 = len << 16; 87 /* Must preserve the end of descriptor list indication */ 88 if (port_info->tx_desc_cur->td0 & TD_TDLE) 89 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; 90 else 91 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; 92 93 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s)); 94 95 /* Restart the transmitter if disabled */ 96 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS)) 97 sh_eth_write(port_info, EDTRR_TRNS, EDTRR); 98 99 /* Wait until packet is transmitted */ 100 timeout = TIMEOUT_CNT; 101 do { 102 invalidate_cache(port_info->tx_desc_cur, 103 sizeof(struct tx_desc_s)); 104 udelay(100); 105 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--); 106 107 if (timeout < 0) { 108 printf(SHETHER_NAME ": transmit timeout\n"); 109 ret = -ETIMEDOUT; 110 goto err; 111 } 112 113 port_info->tx_desc_cur++; 114 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) 115 port_info->tx_desc_cur = port_info->tx_desc_base; 116 117 err: 118 return ret; 119 } 120 121 static int sh_eth_recv_start(struct sh_eth_dev *eth) 122 { 123 struct sh_eth_info *port_info = ð->port_info[eth->port]; 124 125 /* Check if the rx descriptor is ready */ 126 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); 127 if (port_info->rx_desc_cur->rd0 & RD_RACT) 128 return -EINVAL; 129 130 /* Check for errors */ 131 if (port_info->rx_desc_cur->rd0 & RD_RFE) 132 return -EINVAL; 133 134 return port_info->rx_desc_cur->rd1 & 0xffff; 135 } 136 137 static void sh_eth_recv_finish(struct sh_eth_dev *eth) 138 { 139 struct sh_eth_info *port_info = ð->port_info[eth->port]; 140 141 /* Make current descriptor available again */ 142 if (port_info->rx_desc_cur->rd0 & RD_RDLE) 143 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; 144 else 145 port_info->rx_desc_cur->rd0 = RD_RACT; 146 147 flush_cache_wback(port_info->rx_desc_cur, 148 sizeof(struct rx_desc_s)); 149 150 /* Point to the next descriptor */ 151 port_info->rx_desc_cur++; 152 if (port_info->rx_desc_cur >= 153 port_info->rx_desc_base + NUM_RX_DESC) 154 port_info->rx_desc_cur = port_info->rx_desc_base; 155 } 156 157 static int sh_eth_reset(struct sh_eth_dev *eth) 158 { 159 struct sh_eth_info *port_info = ð->port_info[eth->port]; 160 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 161 int ret = 0, i; 162 163 /* Start e-dmac transmitter and receiver */ 164 sh_eth_write(port_info, EDSR_ENALL, EDSR); 165 166 /* Perform a software reset and wait for it to complete */ 167 sh_eth_write(port_info, EDMR_SRST, EDMR); 168 for (i = 0; i < TIMEOUT_CNT; i++) { 169 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST)) 170 break; 171 udelay(1000); 172 } 173 174 if (i == TIMEOUT_CNT) { 175 printf(SHETHER_NAME ": Software reset timeout\n"); 176 ret = -EIO; 177 } 178 179 return ret; 180 #else 181 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR); 182 mdelay(3); 183 sh_eth_write(port_info, 184 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR); 185 186 return 0; 187 #endif 188 } 189 190 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) 191 { 192 int i, ret = 0; 193 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); 194 struct sh_eth_info *port_info = ð->port_info[eth->port]; 195 struct tx_desc_s *cur_tx_desc; 196 197 /* 198 * Allocate rx descriptors. They must be aligned to size of struct 199 * tx_desc_s. 200 */ 201 port_info->tx_desc_alloc = 202 memalign(sizeof(struct tx_desc_s), alloc_desc_size); 203 if (!port_info->tx_desc_alloc) { 204 printf(SHETHER_NAME ": memalign failed\n"); 205 ret = -ENOMEM; 206 goto err; 207 } 208 209 flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size); 210 211 /* Make sure we use a P2 address (non-cacheable) */ 212 port_info->tx_desc_base = 213 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc); 214 port_info->tx_desc_cur = port_info->tx_desc_base; 215 216 /* Initialize all descriptors */ 217 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; 218 cur_tx_desc++, i++) { 219 cur_tx_desc->td0 = 0x00; 220 cur_tx_desc->td1 = 0x00; 221 cur_tx_desc->td2 = 0x00; 222 } 223 224 /* Mark the end of the descriptors */ 225 cur_tx_desc--; 226 cur_tx_desc->td0 |= TD_TDLE; 227 228 /* 229 * Point the controller to the tx descriptor list. Must use physical 230 * addresses 231 */ 232 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); 233 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 234 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); 235 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR); 236 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */ 237 #endif 238 239 err: 240 return ret; 241 } 242 243 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) 244 { 245 int i, ret = 0; 246 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); 247 struct sh_eth_info *port_info = ð->port_info[eth->port]; 248 struct rx_desc_s *cur_rx_desc; 249 u8 *rx_buf; 250 251 /* 252 * Allocate rx descriptors. They must be aligned to size of struct 253 * rx_desc_s. 254 */ 255 port_info->rx_desc_alloc = 256 memalign(sizeof(struct rx_desc_s), alloc_desc_size); 257 if (!port_info->rx_desc_alloc) { 258 printf(SHETHER_NAME ": memalign failed\n"); 259 ret = -ENOMEM; 260 goto err; 261 } 262 263 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size); 264 265 /* Make sure we use a P2 address (non-cacheable) */ 266 port_info->rx_desc_base = 267 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc); 268 269 port_info->rx_desc_cur = port_info->rx_desc_base; 270 271 /* 272 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes 273 * aligned and in P2 area. 274 */ 275 port_info->rx_buf_alloc = 276 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE); 277 if (!port_info->rx_buf_alloc) { 278 printf(SHETHER_NAME ": alloc failed\n"); 279 ret = -ENOMEM; 280 goto err_buf_alloc; 281 } 282 283 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc); 284 285 /* Initialize all descriptors */ 286 for (cur_rx_desc = port_info->rx_desc_base, 287 rx_buf = port_info->rx_buf_base, i = 0; 288 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { 289 cur_rx_desc->rd0 = RD_RACT; 290 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; 291 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf); 292 } 293 294 /* Mark the end of the descriptors */ 295 cur_rx_desc--; 296 cur_rx_desc->rd0 |= RD_RDLE; 297 298 /* Point the controller to the rx descriptor list */ 299 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); 300 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 301 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); 302 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR); 303 sh_eth_write(port_info, RDFFR_RDLF, RDFFR); 304 #endif 305 306 return ret; 307 308 err_buf_alloc: 309 free(port_info->rx_desc_alloc); 310 port_info->rx_desc_alloc = NULL; 311 312 err: 313 return ret; 314 } 315 316 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) 317 { 318 struct sh_eth_info *port_info = ð->port_info[eth->port]; 319 320 if (port_info->tx_desc_alloc) { 321 free(port_info->tx_desc_alloc); 322 port_info->tx_desc_alloc = NULL; 323 } 324 } 325 326 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) 327 { 328 struct sh_eth_info *port_info = ð->port_info[eth->port]; 329 330 if (port_info->rx_desc_alloc) { 331 free(port_info->rx_desc_alloc); 332 port_info->rx_desc_alloc = NULL; 333 } 334 335 if (port_info->rx_buf_alloc) { 336 free(port_info->rx_buf_alloc); 337 port_info->rx_buf_alloc = NULL; 338 } 339 } 340 341 static int sh_eth_desc_init(struct sh_eth_dev *eth) 342 { 343 int ret = 0; 344 345 ret = sh_eth_tx_desc_init(eth); 346 if (ret) 347 goto err_tx_init; 348 349 ret = sh_eth_rx_desc_init(eth); 350 if (ret) 351 goto err_rx_init; 352 353 return ret; 354 err_rx_init: 355 sh_eth_tx_desc_free(eth); 356 357 err_tx_init: 358 return ret; 359 } 360 361 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info, 362 unsigned char *mac) 363 { 364 u32 val; 365 366 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 367 sh_eth_write(port_info, val, MAHR); 368 369 val = (mac[4] << 8) | mac[5]; 370 sh_eth_write(port_info, val, MALR); 371 } 372 373 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) 374 { 375 struct sh_eth_info *port_info = ð->port_info[eth->port]; 376 377 /* Configure e-dmac registers */ 378 sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) | 379 (EMDR_DESC | EDMR_EL), EDMR); 380 381 sh_eth_write(port_info, 0, EESIPR); 382 sh_eth_write(port_info, 0, TRSCER); 383 sh_eth_write(port_info, 0, TFTR); 384 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); 385 sh_eth_write(port_info, RMCR_RST, RMCR); 386 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 387 sh_eth_write(port_info, 0, RPADIR); 388 #endif 389 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); 390 391 /* Configure e-mac registers */ 392 sh_eth_write(port_info, 0, ECSIPR); 393 394 /* Set Mac address */ 395 sh_eth_write_hwaddr(port_info, mac); 396 397 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR); 398 #if defined(SH_ETH_TYPE_GETHER) 399 sh_eth_write(port_info, 0, PIPR); 400 #endif 401 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 402 sh_eth_write(port_info, APR_AP, APR); 403 sh_eth_write(port_info, MPR_MP, MPR); 404 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER); 405 #endif 406 407 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) 408 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); 409 #elif defined(CONFIG_RCAR_GEN2) 410 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR); 411 #endif 412 } 413 414 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) 415 { 416 struct sh_eth_info *port_info = ð->port_info[eth->port]; 417 struct phy_device *phy = port_info->phydev; 418 int ret = 0; 419 u32 val = 0; 420 421 /* Set the transfer speed */ 422 if (phy->speed == 100) { 423 printf(SHETHER_NAME ": 100Base/"); 424 #if defined(SH_ETH_TYPE_GETHER) 425 sh_eth_write(port_info, GECMR_100B, GECMR); 426 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 427 sh_eth_write(port_info, 1, RTRATE); 428 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2) 429 val = ECMR_RTM; 430 #endif 431 } else if (phy->speed == 10) { 432 printf(SHETHER_NAME ": 10Base/"); 433 #if defined(SH_ETH_TYPE_GETHER) 434 sh_eth_write(port_info, GECMR_10B, GECMR); 435 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 436 sh_eth_write(port_info, 0, RTRATE); 437 #endif 438 } 439 #if defined(SH_ETH_TYPE_GETHER) 440 else if (phy->speed == 1000) { 441 printf(SHETHER_NAME ": 1000Base/"); 442 sh_eth_write(port_info, GECMR_1000B, GECMR); 443 } 444 #endif 445 446 /* Check if full duplex mode is supported by the phy */ 447 if (phy->duplex) { 448 printf("Full\n"); 449 sh_eth_write(port_info, 450 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM), 451 ECMR); 452 } else { 453 printf("Half\n"); 454 sh_eth_write(port_info, 455 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE), 456 ECMR); 457 } 458 459 return ret; 460 } 461 462 static void sh_eth_start(struct sh_eth_dev *eth) 463 { 464 struct sh_eth_info *port_info = ð->port_info[eth->port]; 465 466 /* 467 * Enable the e-dmac receiver only. The transmitter will be enabled when 468 * we have something to transmit 469 */ 470 sh_eth_write(port_info, EDRRR_R, EDRRR); 471 } 472 473 static void sh_eth_stop(struct sh_eth_dev *eth) 474 { 475 struct sh_eth_info *port_info = ð->port_info[eth->port]; 476 477 sh_eth_write(port_info, ~EDRRR_R, EDRRR); 478 } 479 480 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac) 481 { 482 int ret = 0; 483 484 ret = sh_eth_reset(eth); 485 if (ret) 486 return ret; 487 488 ret = sh_eth_desc_init(eth); 489 if (ret) 490 return ret; 491 492 sh_eth_mac_regs_config(eth, mac); 493 494 return 0; 495 } 496 497 static int sh_eth_start_common(struct sh_eth_dev *eth) 498 { 499 struct sh_eth_info *port_info = ð->port_info[eth->port]; 500 int ret; 501 502 ret = phy_startup(port_info->phydev); 503 if (ret) { 504 printf(SHETHER_NAME ": phy startup failure\n"); 505 return ret; 506 } 507 508 ret = sh_eth_phy_regs_config(eth); 509 if (ret) 510 return ret; 511 512 sh_eth_start(eth); 513 514 return 0; 515 } 516 517 #ifndef CONFIG_DM_ETH 518 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth) 519 { 520 int ret = 0; 521 struct sh_eth_info *port_info = ð->port_info[eth->port]; 522 struct eth_device *dev = port_info->dev; 523 struct phy_device *phydev; 524 525 phydev = phy_connect( 526 miiphy_get_dev_by_name(dev->name), 527 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); 528 port_info->phydev = phydev; 529 phy_config(phydev); 530 531 return ret; 532 } 533 534 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len) 535 { 536 struct sh_eth_dev *eth = dev->priv; 537 538 return sh_eth_send_common(eth, packet, len); 539 } 540 541 static int sh_eth_recv_common(struct sh_eth_dev *eth) 542 { 543 int len = 0; 544 struct sh_eth_info *port_info = ð->port_info[eth->port]; 545 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2); 546 547 len = sh_eth_recv_start(eth); 548 if (len > 0) { 549 invalidate_cache(packet, len); 550 net_process_received_packet(packet, len); 551 sh_eth_recv_finish(eth); 552 } else 553 len = 0; 554 555 /* Restart the receiver if disabled */ 556 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) 557 sh_eth_write(port_info, EDRRR_R, EDRRR); 558 559 return len; 560 } 561 562 static int sh_eth_recv_legacy(struct eth_device *dev) 563 { 564 struct sh_eth_dev *eth = dev->priv; 565 566 return sh_eth_recv_common(eth); 567 } 568 569 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd) 570 { 571 struct sh_eth_dev *eth = dev->priv; 572 int ret; 573 574 ret = sh_eth_init_common(eth, dev->enetaddr); 575 if (ret) 576 return ret; 577 578 ret = sh_eth_phy_config_legacy(eth); 579 if (ret) { 580 printf(SHETHER_NAME ": phy config timeout\n"); 581 goto err_start; 582 } 583 584 ret = sh_eth_start_common(eth); 585 if (ret) 586 goto err_start; 587 588 return 0; 589 590 err_start: 591 sh_eth_tx_desc_free(eth); 592 sh_eth_rx_desc_free(eth); 593 return ret; 594 } 595 596 void sh_eth_halt_legacy(struct eth_device *dev) 597 { 598 struct sh_eth_dev *eth = dev->priv; 599 600 sh_eth_stop(eth); 601 } 602 603 int sh_eth_initialize(bd_t *bd) 604 { 605 int ret = 0; 606 struct sh_eth_dev *eth = NULL; 607 struct eth_device *dev = NULL; 608 struct mii_dev *mdiodev; 609 610 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); 611 if (!eth) { 612 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 613 ret = -ENOMEM; 614 goto err; 615 } 616 617 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 618 if (!dev) { 619 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 620 ret = -ENOMEM; 621 goto err; 622 } 623 memset(dev, 0, sizeof(struct eth_device)); 624 memset(eth, 0, sizeof(struct sh_eth_dev)); 625 626 eth->port = CONFIG_SH_ETHER_USE_PORT; 627 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 628 eth->port_info[eth->port].iobase = 629 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port); 630 631 dev->priv = (void *)eth; 632 dev->iobase = 0; 633 dev->init = sh_eth_init_legacy; 634 dev->halt = sh_eth_halt_legacy; 635 dev->send = sh_eth_send_legacy; 636 dev->recv = sh_eth_recv_legacy; 637 eth->port_info[eth->port].dev = dev; 638 639 strcpy(dev->name, SHETHER_NAME); 640 641 /* Register Device to EtherNet subsystem */ 642 eth_register(dev); 643 644 bb_miiphy_buses[0].priv = eth; 645 mdiodev = mdio_alloc(); 646 if (!mdiodev) 647 return -ENOMEM; 648 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 649 mdiodev->read = bb_miiphy_read; 650 mdiodev->write = bb_miiphy_write; 651 652 ret = mdio_register(mdiodev); 653 if (ret < 0) 654 return ret; 655 656 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr)) 657 puts("Please set MAC address\n"); 658 659 return ret; 660 661 err: 662 if (dev) 663 free(dev); 664 665 if (eth) 666 free(eth); 667 668 printf(SHETHER_NAME ": Failed\n"); 669 return ret; 670 } 671 672 #else /* CONFIG_DM_ETH */ 673 674 struct sh_ether_priv { 675 struct sh_eth_dev shdev; 676 677 struct mii_dev *bus; 678 phys_addr_t iobase; 679 struct clk clk; 680 struct gpio_desc reset_gpio; 681 }; 682 683 static int sh_ether_send(struct udevice *dev, void *packet, int len) 684 { 685 struct sh_ether_priv *priv = dev_get_priv(dev); 686 struct sh_eth_dev *eth = &priv->shdev; 687 688 return sh_eth_send_common(eth, packet, len); 689 } 690 691 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp) 692 { 693 struct sh_ether_priv *priv = dev_get_priv(dev); 694 struct sh_eth_dev *eth = &priv->shdev; 695 struct sh_eth_info *port_info = ð->port_info[eth->port]; 696 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2); 697 int len; 698 699 len = sh_eth_recv_start(eth); 700 if (len > 0) { 701 invalidate_cache(packet, len); 702 *packetp = packet; 703 704 return len; 705 } else { 706 len = 0; 707 708 /* Restart the receiver if disabled */ 709 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) 710 sh_eth_write(port_info, EDRRR_R, EDRRR); 711 712 return -EAGAIN; 713 } 714 } 715 716 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length) 717 { 718 struct sh_ether_priv *priv = dev_get_priv(dev); 719 struct sh_eth_dev *eth = &priv->shdev; 720 struct sh_eth_info *port_info = ð->port_info[eth->port]; 721 722 sh_eth_recv_finish(eth); 723 724 /* Restart the receiver if disabled */ 725 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) 726 sh_eth_write(port_info, EDRRR_R, EDRRR); 727 728 return 0; 729 } 730 731 static int sh_ether_write_hwaddr(struct udevice *dev) 732 { 733 struct sh_ether_priv *priv = dev_get_priv(dev); 734 struct sh_eth_dev *eth = &priv->shdev; 735 struct sh_eth_info *port_info = ð->port_info[eth->port]; 736 struct eth_pdata *pdata = dev_get_platdata(dev); 737 738 sh_eth_write_hwaddr(port_info, pdata->enetaddr); 739 740 return 0; 741 } 742 743 static int sh_eth_phy_config(struct udevice *dev) 744 { 745 struct sh_ether_priv *priv = dev_get_priv(dev); 746 struct eth_pdata *pdata = dev_get_platdata(dev); 747 struct sh_eth_dev *eth = &priv->shdev; 748 int ret = 0; 749 struct sh_eth_info *port_info = ð->port_info[eth->port]; 750 struct phy_device *phydev; 751 int mask = 0xffffffff; 752 753 phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface); 754 if (!phydev) 755 return -ENODEV; 756 757 phy_connect_dev(phydev, dev); 758 759 port_info->phydev = phydev; 760 phy_config(phydev); 761 762 return ret; 763 } 764 765 static int sh_ether_start(struct udevice *dev) 766 { 767 struct sh_ether_priv *priv = dev_get_priv(dev); 768 struct eth_pdata *pdata = dev_get_platdata(dev); 769 struct sh_eth_dev *eth = &priv->shdev; 770 int ret; 771 772 ret = clk_enable(&priv->clk); 773 if (ret) 774 return ret; 775 776 ret = sh_eth_init_common(eth, pdata->enetaddr); 777 if (ret) 778 goto err_clk; 779 780 ret = sh_eth_phy_config(dev); 781 if (ret) { 782 printf(SHETHER_NAME ": phy config timeout\n"); 783 goto err_start; 784 } 785 786 ret = sh_eth_start_common(eth); 787 if (ret) 788 goto err_start; 789 790 return 0; 791 792 err_start: 793 sh_eth_tx_desc_free(eth); 794 sh_eth_rx_desc_free(eth); 795 err_clk: 796 clk_disable(&priv->clk); 797 return ret; 798 } 799 800 static void sh_ether_stop(struct udevice *dev) 801 { 802 struct sh_ether_priv *priv = dev_get_priv(dev); 803 804 sh_eth_stop(&priv->shdev); 805 clk_disable(&priv->clk); 806 } 807 808 static int sh_ether_probe(struct udevice *udev) 809 { 810 struct eth_pdata *pdata = dev_get_platdata(udev); 811 struct sh_ether_priv *priv = dev_get_priv(udev); 812 struct sh_eth_dev *eth = &priv->shdev; 813 struct mii_dev *mdiodev; 814 int ret; 815 816 priv->iobase = pdata->iobase; 817 818 ret = clk_get_by_index(udev, 0, &priv->clk); 819 if (ret < 0) 820 return ret; 821 822 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio, 823 GPIOD_IS_OUT); 824 825 mdiodev = mdio_alloc(); 826 if (!mdiodev) { 827 ret = -ENOMEM; 828 return ret; 829 } 830 831 mdiodev->read = bb_miiphy_read; 832 mdiodev->write = bb_miiphy_write; 833 bb_miiphy_buses[0].priv = eth; 834 snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name); 835 836 ret = mdio_register(mdiodev); 837 if (ret < 0) 838 goto err_mdio_register; 839 840 priv->bus = miiphy_get_dev_by_name(udev->name); 841 842 eth->port = CONFIG_SH_ETHER_USE_PORT; 843 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 844 eth->port_info[eth->port].iobase = 845 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port); 846 847 return 0; 848 849 err_mdio_register: 850 mdio_free(mdiodev); 851 return ret; 852 } 853 854 static int sh_ether_remove(struct udevice *udev) 855 { 856 struct sh_ether_priv *priv = dev_get_priv(udev); 857 struct sh_eth_dev *eth = &priv->shdev; 858 struct sh_eth_info *port_info = ð->port_info[eth->port]; 859 860 free(port_info->phydev); 861 mdio_unregister(priv->bus); 862 mdio_free(priv->bus); 863 864 if (dm_gpio_is_valid(&priv->reset_gpio)) 865 dm_gpio_free(udev, &priv->reset_gpio); 866 867 return 0; 868 } 869 870 static const struct eth_ops sh_ether_ops = { 871 .start = sh_ether_start, 872 .send = sh_ether_send, 873 .recv = sh_ether_recv, 874 .free_pkt = sh_ether_free_pkt, 875 .stop = sh_ether_stop, 876 .write_hwaddr = sh_ether_write_hwaddr, 877 }; 878 879 int sh_ether_ofdata_to_platdata(struct udevice *dev) 880 { 881 struct eth_pdata *pdata = dev_get_platdata(dev); 882 const char *phy_mode; 883 const fdt32_t *cell; 884 int ret = 0; 885 886 pdata->iobase = devfdt_get_addr(dev); 887 pdata->phy_interface = -1; 888 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 889 NULL); 890 if (phy_mode) 891 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 892 if (pdata->phy_interface == -1) { 893 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 894 return -EINVAL; 895 } 896 897 pdata->max_speed = 1000; 898 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); 899 if (cell) 900 pdata->max_speed = fdt32_to_cpu(*cell); 901 902 sprintf(bb_miiphy_buses[0].name, dev->name); 903 904 return ret; 905 } 906 907 static const struct udevice_id sh_ether_ids[] = { 908 { .compatible = "renesas,ether-r8a7791" }, 909 { } 910 }; 911 912 U_BOOT_DRIVER(eth_sh_ether) = { 913 .name = "sh_ether", 914 .id = UCLASS_ETH, 915 .of_match = sh_ether_ids, 916 .ofdata_to_platdata = sh_ether_ofdata_to_platdata, 917 .probe = sh_ether_probe, 918 .remove = sh_ether_remove, 919 .ops = &sh_ether_ops, 920 .priv_auto_alloc_size = sizeof(struct sh_ether_priv), 921 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 922 .flags = DM_FLAG_ALLOC_PRIV_DMA, 923 }; 924 #endif 925 926 /******* for bb_miiphy *******/ 927 static int sh_eth_bb_init(struct bb_miiphy_bus *bus) 928 { 929 return 0; 930 } 931 932 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) 933 { 934 struct sh_eth_dev *eth = bus->priv; 935 struct sh_eth_info *port_info = ð->port_info[eth->port]; 936 937 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR); 938 939 return 0; 940 } 941 942 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) 943 { 944 struct sh_eth_dev *eth = bus->priv; 945 struct sh_eth_info *port_info = ð->port_info[eth->port]; 946 947 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR); 948 949 return 0; 950 } 951 952 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) 953 { 954 struct sh_eth_dev *eth = bus->priv; 955 struct sh_eth_info *port_info = ð->port_info[eth->port]; 956 957 if (v) 958 sh_eth_write(port_info, 959 sh_eth_read(port_info, PIR) | PIR_MDO, PIR); 960 else 961 sh_eth_write(port_info, 962 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR); 963 964 return 0; 965 } 966 967 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) 968 { 969 struct sh_eth_dev *eth = bus->priv; 970 struct sh_eth_info *port_info = ð->port_info[eth->port]; 971 972 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3; 973 974 return 0; 975 } 976 977 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) 978 { 979 struct sh_eth_dev *eth = bus->priv; 980 struct sh_eth_info *port_info = ð->port_info[eth->port]; 981 982 if (v) 983 sh_eth_write(port_info, 984 sh_eth_read(port_info, PIR) | PIR_MDC, PIR); 985 else 986 sh_eth_write(port_info, 987 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR); 988 989 return 0; 990 } 991 992 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) 993 { 994 udelay(10); 995 996 return 0; 997 } 998 999 struct bb_miiphy_bus bb_miiphy_buses[] = { 1000 { 1001 .name = "sh_eth", 1002 .init = sh_eth_bb_init, 1003 .mdio_active = sh_eth_bb_mdio_active, 1004 .mdio_tristate = sh_eth_bb_mdio_tristate, 1005 .set_mdio = sh_eth_bb_set_mdio, 1006 .get_mdio = sh_eth_bb_get_mdio, 1007 .set_mdc = sh_eth_bb_set_mdc, 1008 .delay = sh_eth_bb_delay, 1009 } 1010 }; 1011 1012 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); 1013