1 /* 2 * sh_eth.c - Driver for Renesas ethernet controler. 3 * 4 * Copyright (C) 2008, 2011 Renesas Solutions Corp. 5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <config.h> 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <miiphy.h> 29 #include <asm/errno.h> 30 #include <asm/io.h> 31 32 #include "sh_eth.h" 33 34 #ifndef CONFIG_SH_ETHER_USE_PORT 35 # error "Please define CONFIG_SH_ETHER_USE_PORT" 36 #endif 37 #ifndef CONFIG_SH_ETHER_PHY_ADDR 38 # error "Please define CONFIG_SH_ETHER_PHY_ADDR" 39 #endif 40 #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK 41 #define flush_cache_wback(addr, len) \ 42 dcache_wback_range((u32)addr, (u32)(addr + len - 1)) 43 #else 44 #define flush_cache_wback(...) 45 #endif 46 47 #define TIMEOUT_CNT 1000 48 49 int sh_eth_send(struct eth_device *dev, void *packet, int len) 50 { 51 struct sh_eth_dev *eth = dev->priv; 52 int port = eth->port, ret = 0, timeout; 53 struct sh_eth_info *port_info = ð->port_info[port]; 54 55 if (!packet || len > 0xffff) { 56 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); 57 ret = -EINVAL; 58 goto err; 59 } 60 61 /* packet must be a 4 byte boundary */ 62 if ((int)packet & 3) { 63 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); 64 ret = -EFAULT; 65 goto err; 66 } 67 68 /* Update tx descriptor */ 69 flush_cache_wback(packet, len); 70 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); 71 port_info->tx_desc_cur->td1 = len << 16; 72 /* Must preserve the end of descriptor list indication */ 73 if (port_info->tx_desc_cur->td0 & TD_TDLE) 74 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; 75 else 76 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; 77 78 /* Restart the transmitter if disabled */ 79 if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) 80 sh_eth_write(eth, EDTRR_TRNS, EDTRR); 81 82 /* Wait until packet is transmitted */ 83 timeout = TIMEOUT_CNT; 84 while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) 85 udelay(100); 86 87 if (timeout < 0) { 88 printf(SHETHER_NAME ": transmit timeout\n"); 89 ret = -ETIMEDOUT; 90 goto err; 91 } 92 93 port_info->tx_desc_cur++; 94 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) 95 port_info->tx_desc_cur = port_info->tx_desc_base; 96 97 err: 98 return ret; 99 } 100 101 int sh_eth_recv(struct eth_device *dev) 102 { 103 struct sh_eth_dev *eth = dev->priv; 104 int port = eth->port, len = 0; 105 struct sh_eth_info *port_info = ð->port_info[port]; 106 uchar *packet; 107 108 /* Check if the rx descriptor is ready */ 109 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { 110 /* Check for errors */ 111 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { 112 len = port_info->rx_desc_cur->rd1 & 0xffff; 113 packet = (uchar *) 114 ADDR_TO_P2(port_info->rx_desc_cur->rd2); 115 NetReceive(packet, len); 116 } 117 118 /* Make current descriptor available again */ 119 if (port_info->rx_desc_cur->rd0 & RD_RDLE) 120 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; 121 else 122 port_info->rx_desc_cur->rd0 = RD_RACT; 123 124 /* Point to the next descriptor */ 125 port_info->rx_desc_cur++; 126 if (port_info->rx_desc_cur >= 127 port_info->rx_desc_base + NUM_RX_DESC) 128 port_info->rx_desc_cur = port_info->rx_desc_base; 129 } 130 131 /* Restart the receiver if disabled */ 132 if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) 133 sh_eth_write(eth, EDRRR_R, EDRRR); 134 135 return len; 136 } 137 138 static int sh_eth_reset(struct sh_eth_dev *eth) 139 { 140 #if defined(SH_ETH_TYPE_GETHER) 141 int ret = 0, i; 142 143 /* Start e-dmac transmitter and receiver */ 144 sh_eth_write(eth, EDSR_ENALL, EDSR); 145 146 /* Perform a software reset and wait for it to complete */ 147 sh_eth_write(eth, EDMR_SRST, EDMR); 148 for (i = 0; i < TIMEOUT_CNT ; i++) { 149 if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) 150 break; 151 udelay(1000); 152 } 153 154 if (i == TIMEOUT_CNT) { 155 printf(SHETHER_NAME ": Software reset timeout\n"); 156 ret = -EIO; 157 } 158 159 return ret; 160 #else 161 sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR); 162 udelay(3000); 163 sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR); 164 165 return 0; 166 #endif 167 } 168 169 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) 170 { 171 int port = eth->port, i, ret = 0; 172 u32 tmp_addr; 173 struct sh_eth_info *port_info = ð->port_info[port]; 174 struct tx_desc_s *cur_tx_desc; 175 176 /* 177 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned 178 */ 179 port_info->tx_desc_malloc = malloc(NUM_TX_DESC * 180 sizeof(struct tx_desc_s) + 181 TX_DESC_SIZE - 1); 182 if (!port_info->tx_desc_malloc) { 183 printf(SHETHER_NAME ": malloc failed\n"); 184 ret = -ENOMEM; 185 goto err; 186 } 187 188 tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & 189 ~(TX_DESC_SIZE - 1)); 190 flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); 191 /* Make sure we use a P2 address (non-cacheable) */ 192 port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); 193 port_info->tx_desc_cur = port_info->tx_desc_base; 194 195 /* Initialize all descriptors */ 196 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; 197 cur_tx_desc++, i++) { 198 cur_tx_desc->td0 = 0x00; 199 cur_tx_desc->td1 = 0x00; 200 cur_tx_desc->td2 = 0x00; 201 } 202 203 /* Mark the end of the descriptors */ 204 cur_tx_desc--; 205 cur_tx_desc->td0 |= TD_TDLE; 206 207 /* Point the controller to the tx descriptor list. Must use physical 208 addresses */ 209 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); 210 #if defined(SH_ETH_TYPE_GETHER) 211 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); 212 sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); 213 sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ 214 #endif 215 216 err: 217 return ret; 218 } 219 220 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) 221 { 222 int port = eth->port, i , ret = 0; 223 struct sh_eth_info *port_info = ð->port_info[port]; 224 struct rx_desc_s *cur_rx_desc; 225 u32 tmp_addr; 226 u8 *rx_buf; 227 228 /* 229 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned 230 */ 231 port_info->rx_desc_malloc = malloc(NUM_RX_DESC * 232 sizeof(struct rx_desc_s) + 233 RX_DESC_SIZE - 1); 234 if (!port_info->rx_desc_malloc) { 235 printf(SHETHER_NAME ": malloc failed\n"); 236 ret = -ENOMEM; 237 goto err; 238 } 239 240 tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & 241 ~(RX_DESC_SIZE - 1)); 242 flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); 243 /* Make sure we use a P2 address (non-cacheable) */ 244 port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); 245 246 port_info->rx_desc_cur = port_info->rx_desc_base; 247 248 /* 249 * Allocate rx data buffers. They must be 32 bytes aligned and in 250 * P2 area 251 */ 252 port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); 253 if (!port_info->rx_buf_malloc) { 254 printf(SHETHER_NAME ": malloc failed\n"); 255 ret = -ENOMEM; 256 goto err_buf_malloc; 257 } 258 259 tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & 260 ~(32 - 1)); 261 port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); 262 263 /* Initialize all descriptors */ 264 for (cur_rx_desc = port_info->rx_desc_base, 265 rx_buf = port_info->rx_buf_base, i = 0; 266 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { 267 cur_rx_desc->rd0 = RD_RACT; 268 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; 269 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); 270 } 271 272 /* Mark the end of the descriptors */ 273 cur_rx_desc--; 274 cur_rx_desc->rd0 |= RD_RDLE; 275 276 /* Point the controller to the rx descriptor list */ 277 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); 278 #if defined(SH_ETH_TYPE_GETHER) 279 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); 280 sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); 281 sh_eth_write(eth, RDFFR_RDLF, RDFFR); 282 #endif 283 284 return ret; 285 286 err_buf_malloc: 287 free(port_info->rx_desc_malloc); 288 port_info->rx_desc_malloc = NULL; 289 290 err: 291 return ret; 292 } 293 294 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) 295 { 296 int port = eth->port; 297 struct sh_eth_info *port_info = ð->port_info[port]; 298 299 if (port_info->tx_desc_malloc) { 300 free(port_info->tx_desc_malloc); 301 port_info->tx_desc_malloc = NULL; 302 } 303 } 304 305 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) 306 { 307 int port = eth->port; 308 struct sh_eth_info *port_info = ð->port_info[port]; 309 310 if (port_info->rx_desc_malloc) { 311 free(port_info->rx_desc_malloc); 312 port_info->rx_desc_malloc = NULL; 313 } 314 315 if (port_info->rx_buf_malloc) { 316 free(port_info->rx_buf_malloc); 317 port_info->rx_buf_malloc = NULL; 318 } 319 } 320 321 static int sh_eth_desc_init(struct sh_eth_dev *eth) 322 { 323 int ret = 0; 324 325 ret = sh_eth_tx_desc_init(eth); 326 if (ret) 327 goto err_tx_init; 328 329 ret = sh_eth_rx_desc_init(eth); 330 if (ret) 331 goto err_rx_init; 332 333 return ret; 334 err_rx_init: 335 sh_eth_tx_desc_free(eth); 336 337 err_tx_init: 338 return ret; 339 } 340 341 static int sh_eth_phy_config(struct sh_eth_dev *eth) 342 { 343 int port = eth->port, ret = 0; 344 struct sh_eth_info *port_info = ð->port_info[port]; 345 struct eth_device *dev = port_info->dev; 346 struct phy_device *phydev; 347 348 phydev = phy_connect( 349 miiphy_get_dev_by_name(dev->name), 350 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); 351 port_info->phydev = phydev; 352 phy_config(phydev); 353 354 return ret; 355 } 356 357 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) 358 { 359 int port = eth->port, ret = 0; 360 u32 val; 361 struct sh_eth_info *port_info = ð->port_info[port]; 362 struct eth_device *dev = port_info->dev; 363 struct phy_device *phy; 364 365 /* Configure e-dmac registers */ 366 sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL, 367 EDMR); 368 sh_eth_write(eth, 0, EESIPR); 369 sh_eth_write(eth, 0, TRSCER); 370 sh_eth_write(eth, 0, TFTR); 371 sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); 372 sh_eth_write(eth, RMCR_RST, RMCR); 373 #if defined(SH_ETH_TYPE_GETHER) 374 sh_eth_write(eth, 0, RPADIR); 375 #endif 376 sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); 377 378 /* Configure e-mac registers */ 379 sh_eth_write(eth, 0, ECSIPR); 380 381 /* Set Mac address */ 382 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | 383 dev->enetaddr[2] << 8 | dev->enetaddr[3]; 384 sh_eth_write(eth, val, MAHR); 385 386 val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; 387 sh_eth_write(eth, val, MALR); 388 389 sh_eth_write(eth, RFLR_RFL_MIN, RFLR); 390 #if defined(SH_ETH_TYPE_GETHER) 391 sh_eth_write(eth, 0, PIPR); 392 sh_eth_write(eth, APR_AP, APR); 393 sh_eth_write(eth, MPR_MP, MPR); 394 sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); 395 #endif 396 397 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) 398 sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); 399 #endif 400 /* Configure phy */ 401 ret = sh_eth_phy_config(eth); 402 if (ret) { 403 printf(SHETHER_NAME ": phy config timeout\n"); 404 goto err_phy_cfg; 405 } 406 phy = port_info->phydev; 407 ret = phy_startup(phy); 408 if (ret) { 409 printf(SHETHER_NAME ": phy startup failure\n"); 410 return ret; 411 } 412 413 val = 0; 414 415 /* Set the transfer speed */ 416 if (phy->speed == 100) { 417 printf(SHETHER_NAME ": 100Base/"); 418 #if defined(SH_ETH_TYPE_GETHER) 419 sh_eth_write(eth, GECMR_100B, GECMR); 420 #elif defined(CONFIG_CPU_SH7757) 421 sh_eth_write(eth, 1, RTRATE); 422 #elif defined(CONFIG_CPU_SH7724) 423 val = ECMR_RTM; 424 #endif 425 } else if (phy->speed == 10) { 426 printf(SHETHER_NAME ": 10Base/"); 427 #if defined(SH_ETH_TYPE_GETHER) 428 sh_eth_write(eth, GECMR_10B, GECMR); 429 #elif defined(CONFIG_CPU_SH7757) 430 sh_eth_write(eth, 0, RTRATE); 431 #endif 432 } 433 #if defined(SH_ETH_TYPE_GETHER) 434 else if (phy->speed == 1000) { 435 printf(SHETHER_NAME ": 1000Base/"); 436 sh_eth_write(eth, GECMR_1000B, GECMR); 437 } 438 #endif 439 440 /* Check if full duplex mode is supported by the phy */ 441 if (phy->duplex) { 442 printf("Full\n"); 443 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), 444 ECMR); 445 } else { 446 printf("Half\n"); 447 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); 448 } 449 450 return ret; 451 452 err_phy_cfg: 453 return ret; 454 } 455 456 static void sh_eth_start(struct sh_eth_dev *eth) 457 { 458 /* 459 * Enable the e-dmac receiver only. The transmitter will be enabled when 460 * we have something to transmit 461 */ 462 sh_eth_write(eth, EDRRR_R, EDRRR); 463 } 464 465 static void sh_eth_stop(struct sh_eth_dev *eth) 466 { 467 sh_eth_write(eth, ~EDRRR_R, EDRRR); 468 } 469 470 int sh_eth_init(struct eth_device *dev, bd_t *bd) 471 { 472 int ret = 0; 473 struct sh_eth_dev *eth = dev->priv; 474 475 ret = sh_eth_reset(eth); 476 if (ret) 477 goto err; 478 479 ret = sh_eth_desc_init(eth); 480 if (ret) 481 goto err; 482 483 ret = sh_eth_config(eth, bd); 484 if (ret) 485 goto err_config; 486 487 sh_eth_start(eth); 488 489 return ret; 490 491 err_config: 492 sh_eth_tx_desc_free(eth); 493 sh_eth_rx_desc_free(eth); 494 495 err: 496 return ret; 497 } 498 499 void sh_eth_halt(struct eth_device *dev) 500 { 501 struct sh_eth_dev *eth = dev->priv; 502 sh_eth_stop(eth); 503 } 504 505 int sh_eth_initialize(bd_t *bd) 506 { 507 int ret = 0; 508 struct sh_eth_dev *eth = NULL; 509 struct eth_device *dev = NULL; 510 511 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); 512 if (!eth) { 513 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 514 ret = -ENOMEM; 515 goto err; 516 } 517 518 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 519 if (!dev) { 520 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 521 ret = -ENOMEM; 522 goto err; 523 } 524 memset(dev, 0, sizeof(struct eth_device)); 525 memset(eth, 0, sizeof(struct sh_eth_dev)); 526 527 eth->port = CONFIG_SH_ETHER_USE_PORT; 528 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 529 530 dev->priv = (void *)eth; 531 dev->iobase = 0; 532 dev->init = sh_eth_init; 533 dev->halt = sh_eth_halt; 534 dev->send = sh_eth_send; 535 dev->recv = sh_eth_recv; 536 eth->port_info[eth->port].dev = dev; 537 538 sprintf(dev->name, SHETHER_NAME); 539 540 /* Register Device to EtherNet subsystem */ 541 eth_register(dev); 542 543 bb_miiphy_buses[0].priv = eth; 544 miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); 545 546 if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) 547 puts("Please set MAC address\n"); 548 549 return ret; 550 551 err: 552 if (dev) 553 free(dev); 554 555 if (eth) 556 free(eth); 557 558 printf(SHETHER_NAME ": Failed\n"); 559 return ret; 560 } 561 562 /******* for bb_miiphy *******/ 563 static int sh_eth_bb_init(struct bb_miiphy_bus *bus) 564 { 565 return 0; 566 } 567 568 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) 569 { 570 struct sh_eth_dev *eth = bus->priv; 571 572 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR); 573 574 return 0; 575 } 576 577 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) 578 { 579 struct sh_eth_dev *eth = bus->priv; 580 581 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR); 582 583 return 0; 584 } 585 586 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) 587 { 588 struct sh_eth_dev *eth = bus->priv; 589 590 if (v) 591 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR); 592 else 593 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR); 594 595 return 0; 596 } 597 598 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) 599 { 600 struct sh_eth_dev *eth = bus->priv; 601 602 *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3; 603 604 return 0; 605 } 606 607 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) 608 { 609 struct sh_eth_dev *eth = bus->priv; 610 611 if (v) 612 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR); 613 else 614 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR); 615 616 return 0; 617 } 618 619 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) 620 { 621 udelay(10); 622 623 return 0; 624 } 625 626 struct bb_miiphy_bus bb_miiphy_buses[] = { 627 { 628 .name = "sh_eth", 629 .init = sh_eth_bb_init, 630 .mdio_active = sh_eth_bb_mdio_active, 631 .mdio_tristate = sh_eth_bb_mdio_tristate, 632 .set_mdio = sh_eth_bb_set_mdio, 633 .get_mdio = sh_eth_bb_get_mdio, 634 .set_mdc = sh_eth_bb_set_mdc, 635 .delay = sh_eth_bb_delay, 636 } 637 }; 638 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); 639