1 /* 2 * sh_eth.c - Driver for Renesas ethernet controler. 3 * 4 * Copyright (C) 2008, 2011 Renesas Solutions Corp. 5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <config.h> 12 #include <common.h> 13 #include <malloc.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <miiphy.h> 17 #include <asm/errno.h> 18 #include <asm/io.h> 19 20 #include "sh_eth.h" 21 22 #ifndef CONFIG_SH_ETHER_USE_PORT 23 # error "Please define CONFIG_SH_ETHER_USE_PORT" 24 #endif 25 #ifndef CONFIG_SH_ETHER_PHY_ADDR 26 # error "Please define CONFIG_SH_ETHER_PHY_ADDR" 27 #endif 28 #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK 29 #define flush_cache_wback(addr, len) \ 30 dcache_wback_range((u32)addr, (u32)(addr + len - 1)) 31 #else 32 #define flush_cache_wback(...) 33 #endif 34 35 #define TIMEOUT_CNT 1000 36 37 int sh_eth_send(struct eth_device *dev, void *packet, int len) 38 { 39 struct sh_eth_dev *eth = dev->priv; 40 int port = eth->port, ret = 0, timeout; 41 struct sh_eth_info *port_info = ð->port_info[port]; 42 43 if (!packet || len > 0xffff) { 44 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); 45 ret = -EINVAL; 46 goto err; 47 } 48 49 /* packet must be a 4 byte boundary */ 50 if ((int)packet & 3) { 51 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); 52 ret = -EFAULT; 53 goto err; 54 } 55 56 /* Update tx descriptor */ 57 flush_cache_wback(packet, len); 58 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); 59 port_info->tx_desc_cur->td1 = len << 16; 60 /* Must preserve the end of descriptor list indication */ 61 if (port_info->tx_desc_cur->td0 & TD_TDLE) 62 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; 63 else 64 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; 65 66 /* Restart the transmitter if disabled */ 67 if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) 68 sh_eth_write(eth, EDTRR_TRNS, EDTRR); 69 70 /* Wait until packet is transmitted */ 71 timeout = TIMEOUT_CNT; 72 while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) 73 udelay(100); 74 75 if (timeout < 0) { 76 printf(SHETHER_NAME ": transmit timeout\n"); 77 ret = -ETIMEDOUT; 78 goto err; 79 } 80 81 port_info->tx_desc_cur++; 82 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) 83 port_info->tx_desc_cur = port_info->tx_desc_base; 84 85 err: 86 return ret; 87 } 88 89 int sh_eth_recv(struct eth_device *dev) 90 { 91 struct sh_eth_dev *eth = dev->priv; 92 int port = eth->port, len = 0; 93 struct sh_eth_info *port_info = ð->port_info[port]; 94 uchar *packet; 95 96 /* Check if the rx descriptor is ready */ 97 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { 98 /* Check for errors */ 99 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { 100 len = port_info->rx_desc_cur->rd1 & 0xffff; 101 packet = (uchar *) 102 ADDR_TO_P2(port_info->rx_desc_cur->rd2); 103 NetReceive(packet, len); 104 } 105 106 /* Make current descriptor available again */ 107 if (port_info->rx_desc_cur->rd0 & RD_RDLE) 108 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; 109 else 110 port_info->rx_desc_cur->rd0 = RD_RACT; 111 112 /* Point to the next descriptor */ 113 port_info->rx_desc_cur++; 114 if (port_info->rx_desc_cur >= 115 port_info->rx_desc_base + NUM_RX_DESC) 116 port_info->rx_desc_cur = port_info->rx_desc_base; 117 } 118 119 /* Restart the receiver if disabled */ 120 if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) 121 sh_eth_write(eth, EDRRR_R, EDRRR); 122 123 return len; 124 } 125 126 static int sh_eth_reset(struct sh_eth_dev *eth) 127 { 128 #if defined(SH_ETH_TYPE_GETHER) 129 int ret = 0, i; 130 131 /* Start e-dmac transmitter and receiver */ 132 sh_eth_write(eth, EDSR_ENALL, EDSR); 133 134 /* Perform a software reset and wait for it to complete */ 135 sh_eth_write(eth, EDMR_SRST, EDMR); 136 for (i = 0; i < TIMEOUT_CNT ; i++) { 137 if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) 138 break; 139 udelay(1000); 140 } 141 142 if (i == TIMEOUT_CNT) { 143 printf(SHETHER_NAME ": Software reset timeout\n"); 144 ret = -EIO; 145 } 146 147 return ret; 148 #else 149 sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR); 150 udelay(3000); 151 sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR); 152 153 return 0; 154 #endif 155 } 156 157 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) 158 { 159 int port = eth->port, i, ret = 0; 160 u32 tmp_addr; 161 struct sh_eth_info *port_info = ð->port_info[port]; 162 struct tx_desc_s *cur_tx_desc; 163 164 /* 165 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned 166 */ 167 port_info->tx_desc_malloc = malloc(NUM_TX_DESC * 168 sizeof(struct tx_desc_s) + 169 TX_DESC_SIZE - 1); 170 if (!port_info->tx_desc_malloc) { 171 printf(SHETHER_NAME ": malloc failed\n"); 172 ret = -ENOMEM; 173 goto err; 174 } 175 176 tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & 177 ~(TX_DESC_SIZE - 1)); 178 flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); 179 /* Make sure we use a P2 address (non-cacheable) */ 180 port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); 181 port_info->tx_desc_cur = port_info->tx_desc_base; 182 183 /* Initialize all descriptors */ 184 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; 185 cur_tx_desc++, i++) { 186 cur_tx_desc->td0 = 0x00; 187 cur_tx_desc->td1 = 0x00; 188 cur_tx_desc->td2 = 0x00; 189 } 190 191 /* Mark the end of the descriptors */ 192 cur_tx_desc--; 193 cur_tx_desc->td0 |= TD_TDLE; 194 195 /* Point the controller to the tx descriptor list. Must use physical 196 addresses */ 197 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); 198 #if defined(SH_ETH_TYPE_GETHER) 199 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); 200 sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); 201 sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ 202 #endif 203 204 err: 205 return ret; 206 } 207 208 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) 209 { 210 int port = eth->port, i , ret = 0; 211 struct sh_eth_info *port_info = ð->port_info[port]; 212 struct rx_desc_s *cur_rx_desc; 213 u32 tmp_addr; 214 u8 *rx_buf; 215 216 /* 217 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned 218 */ 219 port_info->rx_desc_malloc = malloc(NUM_RX_DESC * 220 sizeof(struct rx_desc_s) + 221 RX_DESC_SIZE - 1); 222 if (!port_info->rx_desc_malloc) { 223 printf(SHETHER_NAME ": malloc failed\n"); 224 ret = -ENOMEM; 225 goto err; 226 } 227 228 tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & 229 ~(RX_DESC_SIZE - 1)); 230 flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); 231 /* Make sure we use a P2 address (non-cacheable) */ 232 port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); 233 234 port_info->rx_desc_cur = port_info->rx_desc_base; 235 236 /* 237 * Allocate rx data buffers. They must be 32 bytes aligned and in 238 * P2 area 239 */ 240 port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); 241 if (!port_info->rx_buf_malloc) { 242 printf(SHETHER_NAME ": malloc failed\n"); 243 ret = -ENOMEM; 244 goto err_buf_malloc; 245 } 246 247 tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & 248 ~(32 - 1)); 249 port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); 250 251 /* Initialize all descriptors */ 252 for (cur_rx_desc = port_info->rx_desc_base, 253 rx_buf = port_info->rx_buf_base, i = 0; 254 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { 255 cur_rx_desc->rd0 = RD_RACT; 256 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; 257 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); 258 } 259 260 /* Mark the end of the descriptors */ 261 cur_rx_desc--; 262 cur_rx_desc->rd0 |= RD_RDLE; 263 264 /* Point the controller to the rx descriptor list */ 265 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); 266 #if defined(SH_ETH_TYPE_GETHER) 267 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); 268 sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); 269 sh_eth_write(eth, RDFFR_RDLF, RDFFR); 270 #endif 271 272 return ret; 273 274 err_buf_malloc: 275 free(port_info->rx_desc_malloc); 276 port_info->rx_desc_malloc = NULL; 277 278 err: 279 return ret; 280 } 281 282 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) 283 { 284 int port = eth->port; 285 struct sh_eth_info *port_info = ð->port_info[port]; 286 287 if (port_info->tx_desc_malloc) { 288 free(port_info->tx_desc_malloc); 289 port_info->tx_desc_malloc = NULL; 290 } 291 } 292 293 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) 294 { 295 int port = eth->port; 296 struct sh_eth_info *port_info = ð->port_info[port]; 297 298 if (port_info->rx_desc_malloc) { 299 free(port_info->rx_desc_malloc); 300 port_info->rx_desc_malloc = NULL; 301 } 302 303 if (port_info->rx_buf_malloc) { 304 free(port_info->rx_buf_malloc); 305 port_info->rx_buf_malloc = NULL; 306 } 307 } 308 309 static int sh_eth_desc_init(struct sh_eth_dev *eth) 310 { 311 int ret = 0; 312 313 ret = sh_eth_tx_desc_init(eth); 314 if (ret) 315 goto err_tx_init; 316 317 ret = sh_eth_rx_desc_init(eth); 318 if (ret) 319 goto err_rx_init; 320 321 return ret; 322 err_rx_init: 323 sh_eth_tx_desc_free(eth); 324 325 err_tx_init: 326 return ret; 327 } 328 329 static int sh_eth_phy_config(struct sh_eth_dev *eth) 330 { 331 int port = eth->port, ret = 0; 332 struct sh_eth_info *port_info = ð->port_info[port]; 333 struct eth_device *dev = port_info->dev; 334 struct phy_device *phydev; 335 336 phydev = phy_connect( 337 miiphy_get_dev_by_name(dev->name), 338 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); 339 port_info->phydev = phydev; 340 phy_config(phydev); 341 342 return ret; 343 } 344 345 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) 346 { 347 int port = eth->port, ret = 0; 348 u32 val; 349 struct sh_eth_info *port_info = ð->port_info[port]; 350 struct eth_device *dev = port_info->dev; 351 struct phy_device *phy; 352 353 /* Configure e-dmac registers */ 354 sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL, 355 EDMR); 356 sh_eth_write(eth, 0, EESIPR); 357 sh_eth_write(eth, 0, TRSCER); 358 sh_eth_write(eth, 0, TFTR); 359 sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); 360 sh_eth_write(eth, RMCR_RST, RMCR); 361 #if defined(SH_ETH_TYPE_GETHER) 362 sh_eth_write(eth, 0, RPADIR); 363 #endif 364 sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); 365 366 /* Configure e-mac registers */ 367 sh_eth_write(eth, 0, ECSIPR); 368 369 /* Set Mac address */ 370 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | 371 dev->enetaddr[2] << 8 | dev->enetaddr[3]; 372 sh_eth_write(eth, val, MAHR); 373 374 val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; 375 sh_eth_write(eth, val, MALR); 376 377 sh_eth_write(eth, RFLR_RFL_MIN, RFLR); 378 #if defined(SH_ETH_TYPE_GETHER) 379 sh_eth_write(eth, 0, PIPR); 380 sh_eth_write(eth, APR_AP, APR); 381 sh_eth_write(eth, MPR_MP, MPR); 382 sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); 383 #endif 384 385 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) 386 sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); 387 #endif 388 /* Configure phy */ 389 ret = sh_eth_phy_config(eth); 390 if (ret) { 391 printf(SHETHER_NAME ": phy config timeout\n"); 392 goto err_phy_cfg; 393 } 394 phy = port_info->phydev; 395 ret = phy_startup(phy); 396 if (ret) { 397 printf(SHETHER_NAME ": phy startup failure\n"); 398 return ret; 399 } 400 401 val = 0; 402 403 /* Set the transfer speed */ 404 if (phy->speed == 100) { 405 printf(SHETHER_NAME ": 100Base/"); 406 #if defined(SH_ETH_TYPE_GETHER) 407 sh_eth_write(eth, GECMR_100B, GECMR); 408 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 409 sh_eth_write(eth, 1, RTRATE); 410 #elif defined(CONFIG_CPU_SH7724) 411 val = ECMR_RTM; 412 #endif 413 } else if (phy->speed == 10) { 414 printf(SHETHER_NAME ": 10Base/"); 415 #if defined(SH_ETH_TYPE_GETHER) 416 sh_eth_write(eth, GECMR_10B, GECMR); 417 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 418 sh_eth_write(eth, 0, RTRATE); 419 #endif 420 } 421 #if defined(SH_ETH_TYPE_GETHER) 422 else if (phy->speed == 1000) { 423 printf(SHETHER_NAME ": 1000Base/"); 424 sh_eth_write(eth, GECMR_1000B, GECMR); 425 } 426 #endif 427 428 /* Check if full duplex mode is supported by the phy */ 429 if (phy->duplex) { 430 printf("Full\n"); 431 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), 432 ECMR); 433 } else { 434 printf("Half\n"); 435 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); 436 } 437 438 return ret; 439 440 err_phy_cfg: 441 return ret; 442 } 443 444 static void sh_eth_start(struct sh_eth_dev *eth) 445 { 446 /* 447 * Enable the e-dmac receiver only. The transmitter will be enabled when 448 * we have something to transmit 449 */ 450 sh_eth_write(eth, EDRRR_R, EDRRR); 451 } 452 453 static void sh_eth_stop(struct sh_eth_dev *eth) 454 { 455 sh_eth_write(eth, ~EDRRR_R, EDRRR); 456 } 457 458 int sh_eth_init(struct eth_device *dev, bd_t *bd) 459 { 460 int ret = 0; 461 struct sh_eth_dev *eth = dev->priv; 462 463 ret = sh_eth_reset(eth); 464 if (ret) 465 goto err; 466 467 ret = sh_eth_desc_init(eth); 468 if (ret) 469 goto err; 470 471 ret = sh_eth_config(eth, bd); 472 if (ret) 473 goto err_config; 474 475 sh_eth_start(eth); 476 477 return ret; 478 479 err_config: 480 sh_eth_tx_desc_free(eth); 481 sh_eth_rx_desc_free(eth); 482 483 err: 484 return ret; 485 } 486 487 void sh_eth_halt(struct eth_device *dev) 488 { 489 struct sh_eth_dev *eth = dev->priv; 490 sh_eth_stop(eth); 491 } 492 493 int sh_eth_initialize(bd_t *bd) 494 { 495 int ret = 0; 496 struct sh_eth_dev *eth = NULL; 497 struct eth_device *dev = NULL; 498 499 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); 500 if (!eth) { 501 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 502 ret = -ENOMEM; 503 goto err; 504 } 505 506 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 507 if (!dev) { 508 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 509 ret = -ENOMEM; 510 goto err; 511 } 512 memset(dev, 0, sizeof(struct eth_device)); 513 memset(eth, 0, sizeof(struct sh_eth_dev)); 514 515 eth->port = CONFIG_SH_ETHER_USE_PORT; 516 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 517 518 dev->priv = (void *)eth; 519 dev->iobase = 0; 520 dev->init = sh_eth_init; 521 dev->halt = sh_eth_halt; 522 dev->send = sh_eth_send; 523 dev->recv = sh_eth_recv; 524 eth->port_info[eth->port].dev = dev; 525 526 sprintf(dev->name, SHETHER_NAME); 527 528 /* Register Device to EtherNet subsystem */ 529 eth_register(dev); 530 531 bb_miiphy_buses[0].priv = eth; 532 miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); 533 534 if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) 535 puts("Please set MAC address\n"); 536 537 return ret; 538 539 err: 540 if (dev) 541 free(dev); 542 543 if (eth) 544 free(eth); 545 546 printf(SHETHER_NAME ": Failed\n"); 547 return ret; 548 } 549 550 /******* for bb_miiphy *******/ 551 static int sh_eth_bb_init(struct bb_miiphy_bus *bus) 552 { 553 return 0; 554 } 555 556 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) 557 { 558 struct sh_eth_dev *eth = bus->priv; 559 560 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR); 561 562 return 0; 563 } 564 565 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) 566 { 567 struct sh_eth_dev *eth = bus->priv; 568 569 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR); 570 571 return 0; 572 } 573 574 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) 575 { 576 struct sh_eth_dev *eth = bus->priv; 577 578 if (v) 579 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR); 580 else 581 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR); 582 583 return 0; 584 } 585 586 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) 587 { 588 struct sh_eth_dev *eth = bus->priv; 589 590 *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3; 591 592 return 0; 593 } 594 595 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) 596 { 597 struct sh_eth_dev *eth = bus->priv; 598 599 if (v) 600 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR); 601 else 602 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR); 603 604 return 0; 605 } 606 607 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) 608 { 609 udelay(10); 610 611 return 0; 612 } 613 614 struct bb_miiphy_bus bb_miiphy_buses[] = { 615 { 616 .name = "sh_eth", 617 .init = sh_eth_bb_init, 618 .mdio_active = sh_eth_bb_mdio_active, 619 .mdio_tristate = sh_eth_bb_mdio_tristate, 620 .set_mdio = sh_eth_bb_set_mdio, 621 .get_mdio = sh_eth_bb_get_mdio, 622 .set_mdc = sh_eth_bb_set_mdc, 623 .delay = sh_eth_bb_delay, 624 } 625 }; 626 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); 627