1 /* 2 * sh_eth.c - Driver for Renesas SH7763's ethernet controler. 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (c) 2008 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <config.h> 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <asm/errno.h> 29 #include <asm/io.h> 30 31 #include "sh_eth.h" 32 33 #ifndef CONFIG_SH_ETHER_USE_PORT 34 # error "Please define CONFIG_SH_ETHER_USE_PORT" 35 #endif 36 #ifndef CONFIG_SH_ETHER_PHY_ADDR 37 # error "Please define CONFIG_SH_ETHER_PHY_ADDR" 38 #endif 39 #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK 40 #define flush_cache_wback(addr, len) \ 41 dcache_wback_range((u32)addr, (u32)(addr + len - 1)) 42 #else 43 #define flush_cache_wback(...) 44 #endif 45 46 #define SH_ETH_PHY_DELAY 50000 47 48 /* 49 * Bits are written to the PHY serially using the 50 * PIR register, just like a bit banger. 51 */ 52 static void sh_eth_mii_write_phy_bits(int port, u32 val, int len) 53 { 54 int i; 55 u32 pir; 56 57 /* Bit positions is 1 less than the number of bits */ 58 for (i = len - 1; i >= 0; i--) { 59 /* Write direction, bit to write, clock is low */ 60 pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); 61 outl(pir, PIR(port)); 62 udelay(1); 63 /* Write direction, bit to write, clock is high */ 64 pir = 3 | ((val & 1 << i) ? 1 << 2 : 0); 65 outl(pir, PIR(port)); 66 udelay(1); 67 /* Write direction, bit to write, clock is low */ 68 pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); 69 outl(pir, PIR(port)); 70 udelay(1); 71 } 72 } 73 74 static void sh_eth_mii_bus_release(int port) 75 { 76 /* Read direction, clock is low */ 77 outl(0, PIR(port)); 78 udelay(1); 79 /* Read direction, clock is high */ 80 outl(1, PIR(port)); 81 udelay(1); 82 /* Read direction, clock is low */ 83 outl(0, PIR(port)); 84 udelay(1); 85 } 86 87 static void sh_eth_mii_ind_bus_release(int port) 88 { 89 /* Read direction, clock is low */ 90 outl(0, PIR(port)); 91 udelay(1); 92 } 93 94 static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len) 95 { 96 int i; 97 u32 pir; 98 99 *val = 0; 100 for (i = len - 1; i >= 0; i--) { 101 /* Read direction, clock is high */ 102 outl(1, PIR(port)); 103 udelay(1); 104 /* Read bit */ 105 pir = inl(PIR(port)); 106 *val |= (pir & 8) ? 1 << i : 0; 107 /* Read direction, clock is low */ 108 outl(0, PIR(port)); 109 udelay(1); 110 } 111 } 112 113 #define PHY_INIT 0xFFFFFFFF 114 #define PHY_READ 0x02 115 #define PHY_WRITE 0x01 116 /* 117 * To read a phy register, mii managements frames are sent to the phy. 118 * The frames look like this: 119 * pre (32 bits): 0xffff ffff 120 * st (2 bits): 01 121 * op (2bits): 10: read 01: write 122 * phyad (5 bits): xxxxx 123 * regad (5 bits): xxxxx 124 * ta (Bus release): 125 * data (16 bits): read data 126 */ 127 static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg) 128 { 129 u32 val; 130 131 /* Sent mii management frame */ 132 /* pre */ 133 sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); 134 /* st (start of frame) */ 135 sh_eth_mii_write_phy_bits(port, 0x1, 2); 136 /* op (code) */ 137 sh_eth_mii_write_phy_bits(port, PHY_READ, 2); 138 /* phy address */ 139 sh_eth_mii_write_phy_bits(port, phy_addr, 5); 140 /* Register to read */ 141 sh_eth_mii_write_phy_bits(port, reg, 5); 142 143 /* Bus release */ 144 sh_eth_mii_bus_release(port); 145 146 /* Read register */ 147 sh_eth_mii_read_phy_bits(port, &val, 16); 148 149 return val; 150 } 151 152 /* 153 * To write a phy register, mii managements frames are sent to the phy. 154 * The frames look like this: 155 * pre (32 bits): 0xffff ffff 156 * st (2 bits): 01 157 * op (2bits): 10: read 01: write 158 * phyad (5 bits): xxxxx 159 * regad (5 bits): xxxxx 160 * ta (2 bits): 10 161 * data (16 bits): write data 162 * idle (Independent bus release) 163 */ 164 static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val) 165 { 166 /* Sent mii management frame */ 167 /* pre */ 168 sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); 169 /* st (start of frame) */ 170 sh_eth_mii_write_phy_bits(port, 0x1, 2); 171 /* op (code) */ 172 sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2); 173 /* phy address */ 174 sh_eth_mii_write_phy_bits(port, phy_addr, 5); 175 /* Register to read */ 176 sh_eth_mii_write_phy_bits(port, reg, 5); 177 /* ta */ 178 sh_eth_mii_write_phy_bits(port, PHY_READ, 2); 179 /* Write register data */ 180 sh_eth_mii_write_phy_bits(port, val, 16); 181 182 /* Independent bus release */ 183 sh_eth_mii_ind_bus_release(port); 184 } 185 186 int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) 187 { 188 struct sh_eth_dev *eth = dev->priv; 189 int port = eth->port, ret = 0, timeout; 190 struct sh_eth_info *port_info = ð->port_info[port]; 191 192 if (!packet || len > 0xffff) { 193 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); 194 ret = -EINVAL; 195 goto err; 196 } 197 198 /* packet must be a 4 byte boundary */ 199 if ((int)packet & (4 - 1)) { 200 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__); 201 ret = -EFAULT; 202 goto err; 203 } 204 205 /* Update tx descriptor */ 206 flush_cache_wback(packet, len); 207 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); 208 port_info->tx_desc_cur->td1 = len << 16; 209 /* Must preserve the end of descriptor list indication */ 210 if (port_info->tx_desc_cur->td0 & TD_TDLE) 211 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; 212 else 213 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; 214 215 /* Restart the transmitter if disabled */ 216 if (!(inl(EDTRR(port)) & EDTRR_TRNS)) 217 outl(EDTRR_TRNS, EDTRR(port)); 218 219 /* Wait until packet is transmitted */ 220 timeout = 1000; 221 while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) 222 udelay(100); 223 224 if (timeout < 0) { 225 printf(SHETHER_NAME ": transmit timeout\n"); 226 ret = -ETIMEDOUT; 227 goto err; 228 } 229 230 port_info->tx_desc_cur++; 231 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) 232 port_info->tx_desc_cur = port_info->tx_desc_base; 233 234 return ret; 235 err: 236 return ret; 237 } 238 239 int sh_eth_recv(struct eth_device *dev) 240 { 241 struct sh_eth_dev *eth = dev->priv; 242 int port = eth->port, len = 0; 243 struct sh_eth_info *port_info = ð->port_info[port]; 244 volatile u8 *packet; 245 246 /* Check if the rx descriptor is ready */ 247 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { 248 /* Check for errors */ 249 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { 250 len = port_info->rx_desc_cur->rd1 & 0xffff; 251 packet = (volatile u8 *) 252 ADDR_TO_P2(port_info->rx_desc_cur->rd2); 253 NetReceive(packet, len); 254 } 255 256 /* Make current descriptor available again */ 257 if (port_info->rx_desc_cur->rd0 & RD_RDLE) 258 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; 259 else 260 port_info->rx_desc_cur->rd0 = RD_RACT; 261 262 /* Point to the next descriptor */ 263 port_info->rx_desc_cur++; 264 if (port_info->rx_desc_cur >= 265 port_info->rx_desc_base + NUM_RX_DESC) 266 port_info->rx_desc_cur = port_info->rx_desc_base; 267 } 268 269 /* Restart the receiver if disabled */ 270 if (!(inl(EDRRR(port)) & EDRRR_R)) 271 outl(EDRRR_R, EDRRR(port)); 272 273 return len; 274 } 275 276 #define EDMR_INIT_CNT 1000 277 static int sh_eth_reset(struct sh_eth_dev *eth) 278 { 279 int port = eth->port; 280 #if defined(CONFIG_CPU_SH7763) 281 int ret = 0, i; 282 283 /* Start e-dmac transmitter and receiver */ 284 outl(EDSR_ENALL, EDSR(port)); 285 286 /* Perform a software reset and wait for it to complete */ 287 outl(EDMR_SRST, EDMR(port)); 288 for (i = 0; i < EDMR_INIT_CNT; i++) { 289 if (!(inl(EDMR(port)) & EDMR_SRST)) 290 break; 291 udelay(1000); 292 } 293 294 if (i == EDMR_INIT_CNT) { 295 printf(SHETHER_NAME ": Software reset timeout\n"); 296 ret = -EIO; 297 } 298 299 return ret; 300 #else 301 outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port)); 302 udelay(3000); 303 outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port)); 304 305 return 0; 306 #endif 307 } 308 309 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) 310 { 311 int port = eth->port, i, ret = 0; 312 u32 tmp_addr; 313 struct sh_eth_info *port_info = ð->port_info[port]; 314 struct tx_desc_s *cur_tx_desc; 315 316 /* 317 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned 318 */ 319 port_info->tx_desc_malloc = malloc(NUM_TX_DESC * 320 sizeof(struct tx_desc_s) + 321 TX_DESC_SIZE - 1); 322 if (!port_info->tx_desc_malloc) { 323 printf(SHETHER_NAME ": malloc failed\n"); 324 ret = -ENOMEM; 325 goto err; 326 } 327 328 tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & 329 ~(TX_DESC_SIZE - 1)); 330 flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); 331 /* Make sure we use a P2 address (non-cacheable) */ 332 port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); 333 port_info->tx_desc_cur = port_info->tx_desc_base; 334 335 /* Initialize all descriptors */ 336 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; 337 cur_tx_desc++, i++) { 338 cur_tx_desc->td0 = 0x00; 339 cur_tx_desc->td1 = 0x00; 340 cur_tx_desc->td2 = 0x00; 341 } 342 343 /* Mark the end of the descriptors */ 344 cur_tx_desc--; 345 cur_tx_desc->td0 |= TD_TDLE; 346 347 /* Point the controller to the tx descriptor list. Must use physical 348 addresses */ 349 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); 350 #if defined(CONFIG_CPU_SH7763) 351 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); 352 outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); 353 outl(0x01, TDFFR(port));/* Last discriptor bit */ 354 #endif 355 356 err: 357 return ret; 358 } 359 360 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) 361 { 362 int port = eth->port, i , ret = 0; 363 struct sh_eth_info *port_info = ð->port_info[port]; 364 struct rx_desc_s *cur_rx_desc; 365 u32 tmp_addr; 366 u8 *rx_buf; 367 368 /* 369 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned 370 */ 371 port_info->rx_desc_malloc = malloc(NUM_RX_DESC * 372 sizeof(struct rx_desc_s) + 373 RX_DESC_SIZE - 1); 374 if (!port_info->rx_desc_malloc) { 375 printf(SHETHER_NAME ": malloc failed\n"); 376 ret = -ENOMEM; 377 goto err; 378 } 379 380 tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & 381 ~(RX_DESC_SIZE - 1)); 382 flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); 383 /* Make sure we use a P2 address (non-cacheable) */ 384 port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); 385 386 port_info->rx_desc_cur = port_info->rx_desc_base; 387 388 /* 389 * Allocate rx data buffers. They must be 32 bytes aligned and in 390 * P2 area 391 */ 392 port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); 393 if (!port_info->rx_buf_malloc) { 394 printf(SHETHER_NAME ": malloc failed\n"); 395 ret = -ENOMEM; 396 goto err_buf_malloc; 397 } 398 399 tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & 400 ~(32 - 1)); 401 port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); 402 403 /* Initialize all descriptors */ 404 for (cur_rx_desc = port_info->rx_desc_base, 405 rx_buf = port_info->rx_buf_base, i = 0; 406 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { 407 cur_rx_desc->rd0 = RD_RACT; 408 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; 409 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf); 410 } 411 412 /* Mark the end of the descriptors */ 413 cur_rx_desc--; 414 cur_rx_desc->rd0 |= RD_RDLE; 415 416 /* Point the controller to the rx descriptor list */ 417 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); 418 #if defined(CONFIG_CPU_SH7763) 419 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); 420 outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); 421 outl(RDFFR_RDLF, RDFFR(port)); 422 #endif 423 424 return ret; 425 426 err_buf_malloc: 427 free(port_info->rx_desc_malloc); 428 port_info->rx_desc_malloc = NULL; 429 430 err: 431 return ret; 432 } 433 434 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) 435 { 436 int port = eth->port; 437 struct sh_eth_info *port_info = ð->port_info[port]; 438 439 if (port_info->tx_desc_malloc) { 440 free(port_info->tx_desc_malloc); 441 port_info->tx_desc_malloc = NULL; 442 } 443 } 444 445 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) 446 { 447 int port = eth->port; 448 struct sh_eth_info *port_info = ð->port_info[port]; 449 450 if (port_info->rx_desc_malloc) { 451 free(port_info->rx_desc_malloc); 452 port_info->rx_desc_malloc = NULL; 453 } 454 455 if (port_info->rx_buf_malloc) { 456 free(port_info->rx_buf_malloc); 457 port_info->rx_buf_malloc = NULL; 458 } 459 } 460 461 static int sh_eth_desc_init(struct sh_eth_dev *eth) 462 { 463 int ret = 0; 464 465 ret = sh_eth_tx_desc_init(eth); 466 if (ret) 467 goto err_tx_init; 468 469 ret = sh_eth_rx_desc_init(eth); 470 if (ret) 471 goto err_rx_init; 472 473 return ret; 474 err_rx_init: 475 sh_eth_tx_desc_free(eth); 476 477 err_tx_init: 478 return ret; 479 } 480 481 static int sh_eth_phy_config(struct sh_eth_dev *eth) 482 { 483 int port = eth->port, timeout, ret = 0; 484 struct sh_eth_info *port_info = ð->port_info[port]; 485 u32 val; 486 487 /* Reset phy */ 488 sh_eth_mii_write_phy_reg 489 (port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET); 490 timeout = 10; 491 while (timeout--) { 492 val = sh_eth_mii_read_phy_reg(port, 493 port_info->phy_addr, PHY_CTRL); 494 if (!(val & PHY_C_RESET)) 495 break; 496 udelay(SH_ETH_PHY_DELAY); 497 } 498 499 if (timeout < 0) { 500 printf(SHETHER_NAME ": phy reset timeout\n"); 501 ret = -EIO; 502 goto err_tout; 503 } 504 505 /* Advertise 100/10 baseT full/half duplex */ 506 sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA, 507 (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT)); 508 /* Autonegotiation, normal operation, full duplex, enable tx */ 509 sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, 510 (PHY_C_ANEGEN|PHY_C_RANEG)); 511 /* Wait for autonegotiation to complete */ 512 timeout = 100; 513 while (timeout--) { 514 val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); 515 if (val & PHY_S_ANEGC) 516 break; 517 518 udelay(SH_ETH_PHY_DELAY); 519 } 520 521 if (timeout < 0) { 522 printf(SHETHER_NAME ": phy auto-negotiation failed\n"); 523 ret = -ETIMEDOUT; 524 goto err_tout; 525 } 526 527 return ret; 528 529 err_tout: 530 return ret; 531 } 532 533 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) 534 { 535 int port = eth->port, ret = 0; 536 u32 val, phy_status; 537 struct sh_eth_info *port_info = ð->port_info[port]; 538 struct eth_device *dev = port_info->dev; 539 540 /* Configure e-dmac registers */ 541 outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); 542 outl(0, EESIPR(port)); 543 outl(0, TRSCER(port)); 544 outl(0, TFTR(port)); 545 outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); 546 outl(RMCR_RST, RMCR(port)); 547 #ifndef CONFIG_CPU_SH7757 548 outl(0, RPADIR(port)); 549 #endif 550 outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); 551 552 /* Configure e-mac registers */ 553 #if defined(CONFIG_CPU_SH7757) 554 outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | 555 ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port)); 556 #else 557 outl(0, ECSIPR(port)); 558 #endif 559 560 /* Set Mac address */ 561 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | 562 dev->enetaddr[2] << 8 | dev->enetaddr[3]; 563 outl(val, MAHR(port)); 564 565 val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; 566 outl(val, MALR(port)); 567 568 outl(RFLR_RFL_MIN, RFLR(port)); 569 #ifndef CONFIG_CPU_SH7757 570 outl(0, PIPR(port)); 571 #endif 572 outl(APR_AP, APR(port)); 573 outl(MPR_MP, MPR(port)); 574 #ifdef CONFIG_CPU_SH7757 575 outl(TPAUSER_UNLIMITED, TPAUSER(port)); 576 #else 577 outl(TPAUSER_TPAUSE, TPAUSER(port)); 578 #endif 579 /* Configure phy */ 580 ret = sh_eth_phy_config(eth); 581 if (ret) { 582 printf(SHETHER_NAME ": phy config timeout\n"); 583 goto err_phy_cfg; 584 } 585 /* Read phy status to finish configuring the e-mac */ 586 phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); 587 588 /* Set the transfer speed */ 589 #ifdef CONFIG_CPU_SH7763 590 if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { 591 printf(SHETHER_NAME ": 100Base/"); 592 outl(GECMR_100B, GECMR(port)); 593 } else { 594 printf(SHETHER_NAME ": 10Base/"); 595 outl(GECMR_10B, GECMR(port)); 596 } 597 #endif 598 #if defined(CONFIG_CPU_SH7757) 599 if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { 600 printf("100Base/"); 601 outl(1, RTRATE(port)); 602 } else { 603 printf("10Base/"); 604 outl(0, RTRATE(port)); 605 } 606 #endif 607 608 /* Check if full duplex mode is supported by the phy */ 609 if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { 610 printf("Full\n"); 611 outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); 612 } else { 613 printf("Half\n"); 614 outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); 615 } 616 617 return ret; 618 619 err_phy_cfg: 620 return ret; 621 } 622 623 static void sh_eth_start(struct sh_eth_dev *eth) 624 { 625 /* 626 * Enable the e-dmac receiver only. The transmitter will be enabled when 627 * we have something to transmit 628 */ 629 outl(EDRRR_R, EDRRR(eth->port)); 630 } 631 632 static void sh_eth_stop(struct sh_eth_dev *eth) 633 { 634 outl(~EDRRR_R, EDRRR(eth->port)); 635 } 636 637 int sh_eth_init(struct eth_device *dev, bd_t *bd) 638 { 639 int ret = 0; 640 struct sh_eth_dev *eth = dev->priv; 641 642 ret = sh_eth_reset(eth); 643 if (ret) 644 goto err; 645 646 ret = sh_eth_desc_init(eth); 647 if (ret) 648 goto err; 649 650 ret = sh_eth_config(eth, bd); 651 if (ret) 652 goto err_config; 653 654 sh_eth_start(eth); 655 656 return ret; 657 658 err_config: 659 sh_eth_tx_desc_free(eth); 660 sh_eth_rx_desc_free(eth); 661 662 err: 663 return ret; 664 } 665 666 void sh_eth_halt(struct eth_device *dev) 667 { 668 struct sh_eth_dev *eth = dev->priv; 669 sh_eth_stop(eth); 670 } 671 672 int sh_eth_initialize(bd_t *bd) 673 { 674 int ret = 0; 675 struct sh_eth_dev *eth = NULL; 676 struct eth_device *dev = NULL; 677 678 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); 679 if (!eth) { 680 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 681 ret = -ENOMEM; 682 goto err; 683 } 684 685 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 686 if (!dev) { 687 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 688 ret = -ENOMEM; 689 goto err; 690 } 691 memset(dev, 0, sizeof(struct eth_device)); 692 memset(eth, 0, sizeof(struct sh_eth_dev)); 693 694 eth->port = CONFIG_SH_ETHER_USE_PORT; 695 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 696 697 dev->priv = (void *)eth; 698 dev->iobase = 0; 699 dev->init = sh_eth_init; 700 dev->halt = sh_eth_halt; 701 dev->send = sh_eth_send; 702 dev->recv = sh_eth_recv; 703 eth->port_info[eth->port].dev = dev; 704 705 sprintf(dev->name, SHETHER_NAME); 706 707 /* Register Device to EtherNet subsystem */ 708 eth_register(dev); 709 710 if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) 711 puts("Please set MAC address\n"); 712 713 return ret; 714 715 err: 716 if (dev) 717 free(dev); 718 719 if (eth) 720 free(eth); 721 722 printf(SHETHER_NAME ": Failed\n"); 723 return ret; 724 } 725