1 /* 2 * sh_eth.c - Driver for Renesas ethernet controller. 3 * 4 * Copyright (C) 2008, 2011 Renesas Solutions Corp. 5 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu 6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> 7 * Copyright (C) 2013, 2014 Renesas Electronics Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <config.h> 13 #include <common.h> 14 #include <malloc.h> 15 #include <net.h> 16 #include <netdev.h> 17 #include <miiphy.h> 18 #include <linux/errno.h> 19 #include <asm/io.h> 20 21 #ifdef CONFIG_DM_ETH 22 #include <clk.h> 23 #include <dm.h> 24 #include <linux/mii.h> 25 #include <asm/gpio.h> 26 #endif 27 28 #include "sh_eth.h" 29 30 #ifndef CONFIG_SH_ETHER_USE_PORT 31 # error "Please define CONFIG_SH_ETHER_USE_PORT" 32 #endif 33 #ifndef CONFIG_SH_ETHER_PHY_ADDR 34 # error "Please define CONFIG_SH_ETHER_PHY_ADDR" 35 #endif 36 37 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) 38 #define flush_cache_wback(addr, len) \ 39 flush_dcache_range((u32)addr, \ 40 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE))) 41 #else 42 #define flush_cache_wback(...) 43 #endif 44 45 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) 46 #define invalidate_cache(addr, len) \ 47 { \ 48 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ 49 u32 start, end; \ 50 \ 51 start = (u32)addr; \ 52 end = start + len; \ 53 start &= ~(line_size - 1); \ 54 end = ((end + line_size - 1) & ~(line_size - 1)); \ 55 \ 56 invalidate_dcache_range(start, end); \ 57 } 58 #else 59 #define invalidate_cache(...) 60 #endif 61 62 #define TIMEOUT_CNT 1000 63 64 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len) 65 { 66 int port = eth->port, ret = 0, timeout; 67 struct sh_eth_info *port_info = ð->port_info[port]; 68 69 if (!packet || len > 0xffff) { 70 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); 71 ret = -EINVAL; 72 goto err; 73 } 74 75 /* packet must be a 4 byte boundary */ 76 if ((int)packet & 3) { 77 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n" 78 , __func__); 79 ret = -EFAULT; 80 goto err; 81 } 82 83 /* Update tx descriptor */ 84 flush_cache_wback(packet, len); 85 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); 86 port_info->tx_desc_cur->td1 = len << 16; 87 /* Must preserve the end of descriptor list indication */ 88 if (port_info->tx_desc_cur->td0 & TD_TDLE) 89 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; 90 else 91 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; 92 93 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s)); 94 95 /* Restart the transmitter if disabled */ 96 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS)) 97 sh_eth_write(port_info, EDTRR_TRNS, EDTRR); 98 99 /* Wait until packet is transmitted */ 100 timeout = TIMEOUT_CNT; 101 do { 102 invalidate_cache(port_info->tx_desc_cur, 103 sizeof(struct tx_desc_s)); 104 udelay(100); 105 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--); 106 107 if (timeout < 0) { 108 printf(SHETHER_NAME ": transmit timeout\n"); 109 ret = -ETIMEDOUT; 110 goto err; 111 } 112 113 port_info->tx_desc_cur++; 114 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) 115 port_info->tx_desc_cur = port_info->tx_desc_base; 116 117 err: 118 return ret; 119 } 120 121 static int sh_eth_recv_start(struct sh_eth_dev *eth) 122 { 123 int port = eth->port, len = 0; 124 struct sh_eth_info *port_info = ð->port_info[port]; 125 126 /* Check if the rx descriptor is ready */ 127 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); 128 if (port_info->rx_desc_cur->rd0 & RD_RACT) 129 return -EINVAL; 130 131 /* Check for errors */ 132 if (port_info->rx_desc_cur->rd0 & RD_RFE) 133 return -EINVAL; 134 135 len = port_info->rx_desc_cur->rd1 & 0xffff; 136 137 return len; 138 } 139 140 static void sh_eth_recv_finish(struct sh_eth_dev *eth) 141 { 142 struct sh_eth_info *port_info = ð->port_info[eth->port]; 143 144 /* Make current descriptor available again */ 145 if (port_info->rx_desc_cur->rd0 & RD_RDLE) 146 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; 147 else 148 port_info->rx_desc_cur->rd0 = RD_RACT; 149 150 flush_cache_wback(port_info->rx_desc_cur, 151 sizeof(struct rx_desc_s)); 152 153 /* Point to the next descriptor */ 154 port_info->rx_desc_cur++; 155 if (port_info->rx_desc_cur >= 156 port_info->rx_desc_base + NUM_RX_DESC) 157 port_info->rx_desc_cur = port_info->rx_desc_base; 158 } 159 160 static int sh_eth_reset(struct sh_eth_dev *eth) 161 { 162 struct sh_eth_info *port_info = ð->port_info[eth->port]; 163 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 164 int ret = 0, i; 165 166 /* Start e-dmac transmitter and receiver */ 167 sh_eth_write(port_info, EDSR_ENALL, EDSR); 168 169 /* Perform a software reset and wait for it to complete */ 170 sh_eth_write(port_info, EDMR_SRST, EDMR); 171 for (i = 0; i < TIMEOUT_CNT; i++) { 172 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST)) 173 break; 174 udelay(1000); 175 } 176 177 if (i == TIMEOUT_CNT) { 178 printf(SHETHER_NAME ": Software reset timeout\n"); 179 ret = -EIO; 180 } 181 182 return ret; 183 #else 184 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR); 185 udelay(3000); 186 sh_eth_write(port_info, 187 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR); 188 189 return 0; 190 #endif 191 } 192 193 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) 194 { 195 int port = eth->port, i, ret = 0; 196 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); 197 struct sh_eth_info *port_info = ð->port_info[port]; 198 struct tx_desc_s *cur_tx_desc; 199 200 /* 201 * Allocate rx descriptors. They must be aligned to size of struct 202 * tx_desc_s. 203 */ 204 port_info->tx_desc_alloc = 205 memalign(sizeof(struct tx_desc_s), alloc_desc_size); 206 if (!port_info->tx_desc_alloc) { 207 printf(SHETHER_NAME ": memalign failed\n"); 208 ret = -ENOMEM; 209 goto err; 210 } 211 212 flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size); 213 214 /* Make sure we use a P2 address (non-cacheable) */ 215 port_info->tx_desc_base = 216 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc); 217 port_info->tx_desc_cur = port_info->tx_desc_base; 218 219 /* Initialize all descriptors */ 220 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; 221 cur_tx_desc++, i++) { 222 cur_tx_desc->td0 = 0x00; 223 cur_tx_desc->td1 = 0x00; 224 cur_tx_desc->td2 = 0x00; 225 } 226 227 /* Mark the end of the descriptors */ 228 cur_tx_desc--; 229 cur_tx_desc->td0 |= TD_TDLE; 230 231 /* 232 * Point the controller to the tx descriptor list. Must use physical 233 * addresses 234 */ 235 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); 236 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 237 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); 238 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR); 239 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */ 240 #endif 241 242 err: 243 return ret; 244 } 245 246 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) 247 { 248 int port = eth->port, i, ret = 0; 249 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); 250 struct sh_eth_info *port_info = ð->port_info[port]; 251 struct rx_desc_s *cur_rx_desc; 252 u8 *rx_buf; 253 254 /* 255 * Allocate rx descriptors. They must be aligned to size of struct 256 * rx_desc_s. 257 */ 258 port_info->rx_desc_alloc = 259 memalign(sizeof(struct rx_desc_s), alloc_desc_size); 260 if (!port_info->rx_desc_alloc) { 261 printf(SHETHER_NAME ": memalign failed\n"); 262 ret = -ENOMEM; 263 goto err; 264 } 265 266 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size); 267 268 /* Make sure we use a P2 address (non-cacheable) */ 269 port_info->rx_desc_base = 270 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc); 271 272 port_info->rx_desc_cur = port_info->rx_desc_base; 273 274 /* 275 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes 276 * aligned and in P2 area. 277 */ 278 port_info->rx_buf_alloc = 279 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE); 280 if (!port_info->rx_buf_alloc) { 281 printf(SHETHER_NAME ": alloc failed\n"); 282 ret = -ENOMEM; 283 goto err_buf_alloc; 284 } 285 286 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc); 287 288 /* Initialize all descriptors */ 289 for (cur_rx_desc = port_info->rx_desc_base, 290 rx_buf = port_info->rx_buf_base, i = 0; 291 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { 292 cur_rx_desc->rd0 = RD_RACT; 293 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; 294 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf); 295 } 296 297 /* Mark the end of the descriptors */ 298 cur_rx_desc--; 299 cur_rx_desc->rd0 |= RD_RDLE; 300 301 /* Point the controller to the rx descriptor list */ 302 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); 303 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 304 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); 305 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR); 306 sh_eth_write(port_info, RDFFR_RDLF, RDFFR); 307 #endif 308 309 return ret; 310 311 err_buf_alloc: 312 free(port_info->rx_desc_alloc); 313 port_info->rx_desc_alloc = NULL; 314 315 err: 316 return ret; 317 } 318 319 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) 320 { 321 int port = eth->port; 322 struct sh_eth_info *port_info = ð->port_info[port]; 323 324 if (port_info->tx_desc_alloc) { 325 free(port_info->tx_desc_alloc); 326 port_info->tx_desc_alloc = NULL; 327 } 328 } 329 330 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) 331 { 332 int port = eth->port; 333 struct sh_eth_info *port_info = ð->port_info[port]; 334 335 if (port_info->rx_desc_alloc) { 336 free(port_info->rx_desc_alloc); 337 port_info->rx_desc_alloc = NULL; 338 } 339 340 if (port_info->rx_buf_alloc) { 341 free(port_info->rx_buf_alloc); 342 port_info->rx_buf_alloc = NULL; 343 } 344 } 345 346 static int sh_eth_desc_init(struct sh_eth_dev *eth) 347 { 348 int ret = 0; 349 350 ret = sh_eth_tx_desc_init(eth); 351 if (ret) 352 goto err_tx_init; 353 354 ret = sh_eth_rx_desc_init(eth); 355 if (ret) 356 goto err_rx_init; 357 358 return ret; 359 err_rx_init: 360 sh_eth_tx_desc_free(eth); 361 362 err_tx_init: 363 return ret; 364 } 365 366 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info, 367 unsigned char *mac) 368 { 369 u32 val; 370 371 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 372 sh_eth_write(port_info, val, MAHR); 373 374 val = (mac[4] << 8) | mac[5]; 375 sh_eth_write(port_info, val, MALR); 376 } 377 378 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) 379 { 380 struct sh_eth_info *port_info = ð->port_info[eth->port]; 381 382 /* Configure e-dmac registers */ 383 sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) | 384 (EMDR_DESC | EDMR_EL), EDMR); 385 386 sh_eth_write(port_info, 0, EESIPR); 387 sh_eth_write(port_info, 0, TRSCER); 388 sh_eth_write(port_info, 0, TFTR); 389 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); 390 sh_eth_write(port_info, RMCR_RST, RMCR); 391 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 392 sh_eth_write(port_info, 0, RPADIR); 393 #endif 394 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); 395 396 /* Configure e-mac registers */ 397 sh_eth_write(port_info, 0, ECSIPR); 398 399 /* Set Mac address */ 400 sh_eth_write_hwaddr(port_info, mac); 401 402 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR); 403 #if defined(SH_ETH_TYPE_GETHER) 404 sh_eth_write(port_info, 0, PIPR); 405 #endif 406 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) 407 sh_eth_write(port_info, APR_AP, APR); 408 sh_eth_write(port_info, MPR_MP, MPR); 409 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER); 410 #endif 411 412 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) 413 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); 414 #elif defined(CONFIG_RCAR_GEN2) 415 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR); 416 #endif 417 } 418 419 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) 420 { 421 struct sh_eth_info *port_info = ð->port_info[eth->port]; 422 struct phy_device *phy = port_info->phydev; 423 int ret = 0; 424 u32 val = 0; 425 426 /* Set the transfer speed */ 427 if (phy->speed == 100) { 428 printf(SHETHER_NAME ": 100Base/"); 429 #if defined(SH_ETH_TYPE_GETHER) 430 sh_eth_write(port_info, GECMR_100B, GECMR); 431 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 432 sh_eth_write(port_info, 1, RTRATE); 433 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2) 434 val = ECMR_RTM; 435 #endif 436 } else if (phy->speed == 10) { 437 printf(SHETHER_NAME ": 10Base/"); 438 #if defined(SH_ETH_TYPE_GETHER) 439 sh_eth_write(port_info, GECMR_10B, GECMR); 440 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) 441 sh_eth_write(port_info, 0, RTRATE); 442 #endif 443 } 444 #if defined(SH_ETH_TYPE_GETHER) 445 else if (phy->speed == 1000) { 446 printf(SHETHER_NAME ": 1000Base/"); 447 sh_eth_write(port_info, GECMR_1000B, GECMR); 448 } 449 #endif 450 451 /* Check if full duplex mode is supported by the phy */ 452 if (phy->duplex) { 453 printf("Full\n"); 454 sh_eth_write(port_info, 455 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM), 456 ECMR); 457 } else { 458 printf("Half\n"); 459 sh_eth_write(port_info, 460 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE), 461 ECMR); 462 } 463 464 return ret; 465 } 466 467 static void sh_eth_start(struct sh_eth_dev *eth) 468 { 469 struct sh_eth_info *port_info = ð->port_info[eth->port]; 470 471 /* 472 * Enable the e-dmac receiver only. The transmitter will be enabled when 473 * we have something to transmit 474 */ 475 sh_eth_write(port_info, EDRRR_R, EDRRR); 476 } 477 478 static void sh_eth_stop(struct sh_eth_dev *eth) 479 { 480 struct sh_eth_info *port_info = ð->port_info[eth->port]; 481 482 sh_eth_write(port_info, ~EDRRR_R, EDRRR); 483 } 484 485 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac) 486 { 487 int ret = 0; 488 489 ret = sh_eth_reset(eth); 490 if (ret) 491 return ret; 492 493 ret = sh_eth_desc_init(eth); 494 if (ret) 495 return ret; 496 497 sh_eth_mac_regs_config(eth, mac); 498 499 return 0; 500 } 501 502 static int sh_eth_start_common(struct sh_eth_dev *eth) 503 { 504 struct sh_eth_info *port_info = ð->port_info[eth->port]; 505 int ret; 506 507 ret = phy_startup(port_info->phydev); 508 if (ret) { 509 printf(SHETHER_NAME ": phy startup failure\n"); 510 return ret; 511 } 512 513 ret = sh_eth_phy_regs_config(eth); 514 if (ret) 515 return ret; 516 517 sh_eth_start(eth); 518 519 return 0; 520 } 521 522 #ifndef CONFIG_DM_ETH 523 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth) 524 { 525 int port = eth->port, ret = 0; 526 struct sh_eth_info *port_info = ð->port_info[port]; 527 struct eth_device *dev = port_info->dev; 528 struct phy_device *phydev; 529 530 phydev = phy_connect( 531 miiphy_get_dev_by_name(dev->name), 532 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); 533 port_info->phydev = phydev; 534 phy_config(phydev); 535 536 return ret; 537 } 538 539 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len) 540 { 541 struct sh_eth_dev *eth = dev->priv; 542 543 return sh_eth_send_common(eth, packet, len); 544 } 545 546 static int sh_eth_recv_common(struct sh_eth_dev *eth) 547 { 548 int port = eth->port, len = 0; 549 struct sh_eth_info *port_info = ð->port_info[port]; 550 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2); 551 552 len = sh_eth_recv_start(eth); 553 if (len > 0) { 554 invalidate_cache(packet, len); 555 net_process_received_packet(packet, len); 556 sh_eth_recv_finish(eth); 557 } else 558 len = 0; 559 560 /* Restart the receiver if disabled */ 561 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) 562 sh_eth_write(port_info, EDRRR_R, EDRRR); 563 564 return len; 565 } 566 567 static int sh_eth_recv_legacy(struct eth_device *dev) 568 { 569 struct sh_eth_dev *eth = dev->priv; 570 571 return sh_eth_recv_common(eth); 572 } 573 574 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd) 575 { 576 struct sh_eth_dev *eth = dev->priv; 577 int ret; 578 579 ret = sh_eth_init_common(eth, dev->enetaddr); 580 if (ret) 581 return ret; 582 583 ret = sh_eth_phy_config_legacy(eth); 584 if (ret) { 585 printf(SHETHER_NAME ": phy config timeout\n"); 586 goto err_start; 587 } 588 589 ret = sh_eth_start_common(eth); 590 if (ret) 591 goto err_start; 592 593 return 0; 594 595 err_start: 596 sh_eth_tx_desc_free(eth); 597 sh_eth_rx_desc_free(eth); 598 return ret; 599 } 600 601 void sh_eth_halt_legacy(struct eth_device *dev) 602 { 603 struct sh_eth_dev *eth = dev->priv; 604 605 sh_eth_stop(eth); 606 } 607 608 int sh_eth_initialize(bd_t *bd) 609 { 610 int ret = 0; 611 struct sh_eth_dev *eth = NULL; 612 struct eth_device *dev = NULL; 613 struct mii_dev *mdiodev; 614 615 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); 616 if (!eth) { 617 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 618 ret = -ENOMEM; 619 goto err; 620 } 621 622 dev = (struct eth_device *)malloc(sizeof(struct eth_device)); 623 if (!dev) { 624 printf(SHETHER_NAME ": %s: malloc failed\n", __func__); 625 ret = -ENOMEM; 626 goto err; 627 } 628 memset(dev, 0, sizeof(struct eth_device)); 629 memset(eth, 0, sizeof(struct sh_eth_dev)); 630 631 eth->port = CONFIG_SH_ETHER_USE_PORT; 632 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 633 eth->port_info[eth->port].iobase = 634 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port); 635 636 dev->priv = (void *)eth; 637 dev->iobase = 0; 638 dev->init = sh_eth_init_legacy; 639 dev->halt = sh_eth_halt_legacy; 640 dev->send = sh_eth_send_legacy; 641 dev->recv = sh_eth_recv_legacy; 642 eth->port_info[eth->port].dev = dev; 643 644 strcpy(dev->name, SHETHER_NAME); 645 646 /* Register Device to EtherNet subsystem */ 647 eth_register(dev); 648 649 bb_miiphy_buses[0].priv = eth; 650 mdiodev = mdio_alloc(); 651 if (!mdiodev) 652 return -ENOMEM; 653 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 654 mdiodev->read = bb_miiphy_read; 655 mdiodev->write = bb_miiphy_write; 656 657 ret = mdio_register(mdiodev); 658 if (ret < 0) 659 return ret; 660 661 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr)) 662 puts("Please set MAC address\n"); 663 664 return ret; 665 666 err: 667 if (dev) 668 free(dev); 669 670 if (eth) 671 free(eth); 672 673 printf(SHETHER_NAME ": Failed\n"); 674 return ret; 675 } 676 677 #else /* CONFIG_DM_ETH */ 678 679 struct sh_ether_priv { 680 struct sh_eth_dev shdev; 681 682 struct mii_dev *bus; 683 void __iomem *iobase; 684 struct clk clk; 685 struct gpio_desc reset_gpio; 686 }; 687 688 static int sh_ether_send(struct udevice *dev, void *packet, int len) 689 { 690 struct sh_ether_priv *priv = dev_get_priv(dev); 691 struct sh_eth_dev *eth = &priv->shdev; 692 693 return sh_eth_send_common(eth, packet, len); 694 } 695 696 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp) 697 { 698 struct sh_ether_priv *priv = dev_get_priv(dev); 699 struct sh_eth_dev *eth = &priv->shdev; 700 struct sh_eth_info *port_info = ð->port_info[eth->port]; 701 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2); 702 int len; 703 704 len = sh_eth_recv_start(eth); 705 if (len > 0) { 706 invalidate_cache(packet, len); 707 *packetp = packet; 708 709 return len; 710 } else { 711 len = 0; 712 713 /* Restart the receiver if disabled */ 714 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) 715 sh_eth_write(port_info, EDRRR_R, EDRRR); 716 717 return -EAGAIN; 718 } 719 } 720 721 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length) 722 { 723 struct sh_ether_priv *priv = dev_get_priv(dev); 724 struct sh_eth_dev *eth = &priv->shdev; 725 struct sh_eth_info *port_info = ð->port_info[eth->port]; 726 727 sh_eth_recv_finish(eth); 728 729 /* Restart the receiver if disabled */ 730 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) 731 sh_eth_write(port_info, EDRRR_R, EDRRR); 732 733 return 0; 734 } 735 736 static int sh_ether_write_hwaddr(struct udevice *dev) 737 { 738 struct sh_ether_priv *priv = dev_get_priv(dev); 739 struct sh_eth_dev *eth = &priv->shdev; 740 struct sh_eth_info *port_info = ð->port_info[eth->port]; 741 struct eth_pdata *pdata = dev_get_platdata(dev); 742 743 sh_eth_write_hwaddr(port_info, pdata->enetaddr); 744 745 return 0; 746 } 747 748 static int sh_eth_phy_config(struct udevice *dev) 749 { 750 struct sh_ether_priv *priv = dev_get_priv(dev); 751 struct eth_pdata *pdata = dev_get_platdata(dev); 752 struct sh_eth_dev *eth = &priv->shdev; 753 int port = eth->port, ret = 0; 754 struct sh_eth_info *port_info = ð->port_info[port]; 755 struct phy_device *phydev; 756 int mask = 0xffffffff; 757 758 phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface); 759 if (!phydev) 760 return -ENODEV; 761 762 phy_connect_dev(phydev, dev); 763 764 port_info->phydev = phydev; 765 phy_config(phydev); 766 767 return ret; 768 } 769 770 static int sh_ether_start(struct udevice *dev) 771 { 772 struct sh_ether_priv *priv = dev_get_priv(dev); 773 struct eth_pdata *pdata = dev_get_platdata(dev); 774 struct sh_eth_dev *eth = &priv->shdev; 775 int ret; 776 777 ret = clk_enable(&priv->clk); 778 if (ret) 779 return ret; 780 781 ret = sh_eth_init_common(eth, pdata->enetaddr); 782 if (ret) 783 goto err_clk; 784 785 ret = sh_eth_phy_config(dev); 786 if (ret) { 787 printf(SHETHER_NAME ": phy config timeout\n"); 788 goto err_start; 789 } 790 791 ret = sh_eth_start_common(eth); 792 if (ret) 793 goto err_start; 794 795 return 0; 796 797 err_start: 798 sh_eth_tx_desc_free(eth); 799 sh_eth_rx_desc_free(eth); 800 err_clk: 801 clk_disable(&priv->clk); 802 return ret; 803 } 804 805 static void sh_ether_stop(struct udevice *dev) 806 { 807 struct sh_ether_priv *priv = dev_get_priv(dev); 808 809 sh_eth_stop(&priv->shdev); 810 clk_disable(&priv->clk); 811 } 812 813 static int sh_ether_probe(struct udevice *udev) 814 { 815 struct eth_pdata *pdata = dev_get_platdata(udev); 816 struct sh_ether_priv *priv = dev_get_priv(udev); 817 struct sh_eth_dev *eth = &priv->shdev; 818 struct mii_dev *mdiodev; 819 void __iomem *iobase; 820 int ret; 821 822 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE); 823 priv->iobase = iobase; 824 825 ret = clk_get_by_index(udev, 0, &priv->clk); 826 if (ret < 0) 827 goto err_mdio_alloc; 828 829 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio, 830 GPIOD_IS_OUT); 831 832 mdiodev = mdio_alloc(); 833 if (!mdiodev) { 834 ret = -ENOMEM; 835 goto err_mdio_alloc; 836 } 837 838 mdiodev->read = bb_miiphy_read; 839 mdiodev->write = bb_miiphy_write; 840 bb_miiphy_buses[0].priv = eth; 841 snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name); 842 843 ret = mdio_register(mdiodev); 844 if (ret < 0) 845 goto err_mdio_register; 846 847 priv->bus = miiphy_get_dev_by_name(udev->name); 848 849 eth->port = CONFIG_SH_ETHER_USE_PORT; 850 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; 851 eth->port_info[eth->port].iobase = 852 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port); 853 854 return 0; 855 856 err_mdio_register: 857 mdio_free(mdiodev); 858 err_mdio_alloc: 859 unmap_physmem(priv->iobase, MAP_NOCACHE); 860 return ret; 861 } 862 863 static int sh_ether_remove(struct udevice *udev) 864 { 865 struct sh_ether_priv *priv = dev_get_priv(udev); 866 struct sh_eth_dev *eth = &priv->shdev; 867 struct sh_eth_info *port_info = ð->port_info[eth->port]; 868 869 free(port_info->phydev); 870 mdio_unregister(priv->bus); 871 mdio_free(priv->bus); 872 873 if (dm_gpio_is_valid(&priv->reset_gpio)) 874 dm_gpio_free(udev, &priv->reset_gpio); 875 876 unmap_physmem(priv->iobase, MAP_NOCACHE); 877 878 return 0; 879 } 880 881 static const struct eth_ops sh_ether_ops = { 882 .start = sh_ether_start, 883 .send = sh_ether_send, 884 .recv = sh_ether_recv, 885 .free_pkt = sh_ether_free_pkt, 886 .stop = sh_ether_stop, 887 .write_hwaddr = sh_ether_write_hwaddr, 888 }; 889 890 int sh_ether_ofdata_to_platdata(struct udevice *dev) 891 { 892 struct eth_pdata *pdata = dev_get_platdata(dev); 893 const char *phy_mode; 894 const fdt32_t *cell; 895 int ret = 0; 896 897 pdata->iobase = devfdt_get_addr(dev); 898 pdata->phy_interface = -1; 899 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 900 NULL); 901 if (phy_mode) 902 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 903 if (pdata->phy_interface == -1) { 904 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 905 return -EINVAL; 906 } 907 908 pdata->max_speed = 1000; 909 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); 910 if (cell) 911 pdata->max_speed = fdt32_to_cpu(*cell); 912 913 sprintf(bb_miiphy_buses[0].name, dev->name); 914 915 return ret; 916 } 917 918 static const struct udevice_id sh_ether_ids[] = { 919 { .compatible = "renesas,ether-r8a7791" }, 920 { } 921 }; 922 923 U_BOOT_DRIVER(eth_sh_ether) = { 924 .name = "sh_ether", 925 .id = UCLASS_ETH, 926 .of_match = sh_ether_ids, 927 .ofdata_to_platdata = sh_ether_ofdata_to_platdata, 928 .probe = sh_ether_probe, 929 .remove = sh_ether_remove, 930 .ops = &sh_ether_ops, 931 .priv_auto_alloc_size = sizeof(struct sh_ether_priv), 932 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 933 .flags = DM_FLAG_ALLOC_PRIV_DMA, 934 }; 935 #endif 936 937 /******* for bb_miiphy *******/ 938 static int sh_eth_bb_init(struct bb_miiphy_bus *bus) 939 { 940 return 0; 941 } 942 943 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) 944 { 945 struct sh_eth_dev *eth = bus->priv; 946 struct sh_eth_info *port_info = ð->port_info[eth->port]; 947 948 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR); 949 950 return 0; 951 } 952 953 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) 954 { 955 struct sh_eth_dev *eth = bus->priv; 956 struct sh_eth_info *port_info = ð->port_info[eth->port]; 957 958 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR); 959 960 return 0; 961 } 962 963 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) 964 { 965 struct sh_eth_dev *eth = bus->priv; 966 struct sh_eth_info *port_info = ð->port_info[eth->port]; 967 968 if (v) 969 sh_eth_write(port_info, 970 sh_eth_read(port_info, PIR) | PIR_MDO, PIR); 971 else 972 sh_eth_write(port_info, 973 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR); 974 975 return 0; 976 } 977 978 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) 979 { 980 struct sh_eth_dev *eth = bus->priv; 981 struct sh_eth_info *port_info = ð->port_info[eth->port]; 982 983 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3; 984 985 return 0; 986 } 987 988 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) 989 { 990 struct sh_eth_dev *eth = bus->priv; 991 struct sh_eth_info *port_info = ð->port_info[eth->port]; 992 993 if (v) 994 sh_eth_write(port_info, 995 sh_eth_read(port_info, PIR) | PIR_MDC, PIR); 996 else 997 sh_eth_write(port_info, 998 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR); 999 1000 return 0; 1001 } 1002 1003 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) 1004 { 1005 udelay(10); 1006 1007 return 0; 1008 } 1009 1010 struct bb_miiphy_bus bb_miiphy_buses[] = { 1011 { 1012 .name = "sh_eth", 1013 .init = sh_eth_bb_init, 1014 .mdio_active = sh_eth_bb_mdio_active, 1015 .mdio_tristate = sh_eth_bb_mdio_tristate, 1016 .set_mdio = sh_eth_bb_set_mdio, 1017 .get_mdio = sh_eth_bb_get_mdio, 1018 .set_mdc = sh_eth_bb_set_mdc, 1019 .delay = sh_eth_bb_delay, 1020 } 1021 }; 1022 1023 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); 1024