1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 28 * Portions of this code based on: 29 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 30 * for Linux kernel 2.4.x. 31 * 32 * Written 2002 ShuChen <shuchen@realtek.com.tw> 33 * See Linux Driver for full information 34 * 35 * Linux Driver Version 1.27a, 10.02.2002 36 * 37 * Thanks to: 38 * Jean Chen of RealTek Semiconductor Corp. for 39 * providing the evaluation NIC used to develop 40 * this driver. RealTek's support for Etherboot 41 * is appreciated. 42 * 43 * REVISION HISTORY: 44 * ================ 45 * 46 * v1.0 11-26-2003 timlegge Initial port of Linux driver 47 * v1.5 01-17-2004 timlegge Initial driver output cleanup 48 * 49 * Indent Options: indent -kr -i8 50 ***************************************************************************/ 51 /* 52 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 53 * Modified to use le32_to_cpu and cpu_to_le32 properly 54 */ 55 #include <common.h> 56 #include <malloc.h> 57 #include <net.h> 58 #include <asm/io.h> 59 #include <pci.h> 60 61 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ 62 defined(CONFIG_RTL8169) 63 64 #undef DEBUG_RTL8169 65 #undef DEBUG_RTL8169_TX 66 #undef DEBUG_RTL8169_RX 67 68 #define drv_version "v1.5" 69 #define drv_date "01-17-2004" 70 71 static u32 ioaddr; 72 73 /* Condensed operations for readability. */ 74 #define currticks() get_timer(0) 75 76 /* media options */ 77 #define MAX_UNITS 8 78 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 79 80 /* MAC address length*/ 81 #define MAC_ADDR_LEN 6 82 83 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 84 #define MAX_ETH_FRAME_SIZE 1536 85 86 #define TX_FIFO_THRESH 256 /* In bytes */ 87 88 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 89 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 90 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 91 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 92 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 93 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 94 95 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 96 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 97 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 98 #define RX_BUF_LEN 8192 99 100 #define RTL_MIN_IO_SIZE 0x80 101 #define TX_TIMEOUT (6*HZ) 102 103 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 104 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 105 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 106 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 107 #define RTL_R8(reg) readb (ioaddr + (reg)) 108 #define RTL_R16(reg) readw (ioaddr + (reg)) 109 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 110 111 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 112 #define ETH_ALEN MAC_ADDR_LEN 113 #define ETH_ZLEN 60 114 115 enum RTL8169_registers { 116 MAC0 = 0, /* Ethernet hardware address. */ 117 MAR0 = 8, /* Multicast filter. */ 118 TxDescStartAddr = 0x20, 119 TxHDescStartAddr = 0x28, 120 FLASH = 0x30, 121 ERSR = 0x36, 122 ChipCmd = 0x37, 123 TxPoll = 0x38, 124 IntrMask = 0x3C, 125 IntrStatus = 0x3E, 126 TxConfig = 0x40, 127 RxConfig = 0x44, 128 RxMissed = 0x4C, 129 Cfg9346 = 0x50, 130 Config0 = 0x51, 131 Config1 = 0x52, 132 Config2 = 0x53, 133 Config3 = 0x54, 134 Config4 = 0x55, 135 Config5 = 0x56, 136 MultiIntr = 0x5C, 137 PHYAR = 0x60, 138 TBICSR = 0x64, 139 TBI_ANAR = 0x68, 140 TBI_LPAR = 0x6A, 141 PHYstatus = 0x6C, 142 RxMaxSize = 0xDA, 143 CPlusCmd = 0xE0, 144 RxDescStartAddr = 0xE4, 145 EarlyTxThres = 0xEC, 146 FuncEvent = 0xF0, 147 FuncEventMask = 0xF4, 148 FuncPresetState = 0xF8, 149 FuncForceEvent = 0xFC, 150 }; 151 152 enum RTL8169_register_content { 153 /*InterruptStatusBits */ 154 SYSErr = 0x8000, 155 PCSTimeout = 0x4000, 156 SWInt = 0x0100, 157 TxDescUnavail = 0x80, 158 RxFIFOOver = 0x40, 159 RxUnderrun = 0x20, 160 RxOverflow = 0x10, 161 TxErr = 0x08, 162 TxOK = 0x04, 163 RxErr = 0x02, 164 RxOK = 0x01, 165 166 /*RxStatusDesc */ 167 RxRES = 0x00200000, 168 RxCRC = 0x00080000, 169 RxRUNT = 0x00100000, 170 RxRWT = 0x00400000, 171 172 /*ChipCmdBits */ 173 CmdReset = 0x10, 174 CmdRxEnb = 0x08, 175 CmdTxEnb = 0x04, 176 RxBufEmpty = 0x01, 177 178 /*Cfg9346Bits */ 179 Cfg9346_Lock = 0x00, 180 Cfg9346_Unlock = 0xC0, 181 182 /*rx_mode_bits */ 183 AcceptErr = 0x20, 184 AcceptRunt = 0x10, 185 AcceptBroadcast = 0x08, 186 AcceptMulticast = 0x04, 187 AcceptMyPhys = 0x02, 188 AcceptAllPhys = 0x01, 189 190 /*RxConfigBits */ 191 RxCfgFIFOShift = 13, 192 RxCfgDMAShift = 8, 193 194 /*TxConfigBits */ 195 TxInterFrameGapShift = 24, 196 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 197 198 /*rtl8169_PHYstatus */ 199 TBI_Enable = 0x80, 200 TxFlowCtrl = 0x40, 201 RxFlowCtrl = 0x20, 202 _1000bpsF = 0x10, 203 _100bps = 0x08, 204 _10bps = 0x04, 205 LinkStatus = 0x02, 206 FullDup = 0x01, 207 208 /*GIGABIT_PHY_registers */ 209 PHY_CTRL_REG = 0, 210 PHY_STAT_REG = 1, 211 PHY_AUTO_NEGO_REG = 4, 212 PHY_1000_CTRL_REG = 9, 213 214 /*GIGABIT_PHY_REG_BIT */ 215 PHY_Restart_Auto_Nego = 0x0200, 216 PHY_Enable_Auto_Nego = 0x1000, 217 218 /* PHY_STAT_REG = 1; */ 219 PHY_Auto_Nego_Comp = 0x0020, 220 221 /* PHY_AUTO_NEGO_REG = 4; */ 222 PHY_Cap_10_Half = 0x0020, 223 PHY_Cap_10_Full = 0x0040, 224 PHY_Cap_100_Half = 0x0080, 225 PHY_Cap_100_Full = 0x0100, 226 227 /* PHY_1000_CTRL_REG = 9; */ 228 PHY_Cap_1000_Full = 0x0200, 229 230 PHY_Cap_Null = 0x0, 231 232 /*_MediaType*/ 233 _10_Half = 0x01, 234 _10_Full = 0x02, 235 _100_Half = 0x04, 236 _100_Full = 0x08, 237 _1000_Full = 0x10, 238 239 /*_TBICSRBit*/ 240 TBILinkOK = 0x02000000, 241 }; 242 243 static struct { 244 const char *name; 245 u8 version; /* depend on RTL8169 docs */ 246 u32 RxConfigMask; /* should clear the bits supported by this chip */ 247 } rtl_chip_info[] = { 248 {"RTL-8169", 0x00, 0xff7e1880,}, 249 {"RTL-8169", 0x04, 0xff7e1880,}, 250 }; 251 252 enum _DescStatusBit { 253 OWNbit = 0x80000000, 254 EORbit = 0x40000000, 255 FSbit = 0x20000000, 256 LSbit = 0x10000000, 257 }; 258 259 struct TxDesc { 260 u32 status; 261 u32 vlan_tag; 262 u32 buf_addr; 263 u32 buf_Haddr; 264 }; 265 266 struct RxDesc { 267 u32 status; 268 u32 vlan_tag; 269 u32 buf_addr; 270 u32 buf_Haddr; 271 }; 272 273 /* Define the TX Descriptor */ 274 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 275 /* __attribute__ ((aligned(256))); */ 276 277 /* Create a static buffer of size RX_BUF_SZ for each 278 TX Descriptor. All descriptors point to a 279 part of this buffer */ 280 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 281 282 /* Define the RX Descriptor */ 283 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 284 /* __attribute__ ((aligned(256))); */ 285 286 /* Create a static buffer of size RX_BUF_SZ for each 287 RX Descriptor All descriptors point to a 288 part of this buffer */ 289 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 290 291 struct rtl8169_private { 292 void *mmio_addr; /* memory map physical address */ 293 int chipset; 294 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 295 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 296 unsigned long dirty_tx; 297 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 298 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 299 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 300 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 301 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 302 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 303 unsigned char *Tx_skbuff[NUM_TX_DESC]; 304 } tpx; 305 306 static struct rtl8169_private *tpc; 307 308 static const u16 rtl8169_intr_mask = 309 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 310 TxOK | RxErr | RxOK; 311 static const unsigned int rtl8169_rx_config = 312 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 313 314 static struct pci_device_id supported[] = { 315 {PCI_VENDOR_ID_REALTEK, 0x8169}, 316 {} 317 }; 318 319 void mdio_write(int RegAddr, int value) 320 { 321 int i; 322 323 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 324 udelay(1000); 325 326 for (i = 2000; i > 0; i--) { 327 /* Check if the RTL8169 has completed writing to the specified MII register */ 328 if (!(RTL_R32(PHYAR) & 0x80000000)) { 329 break; 330 } else { 331 udelay(100); 332 } 333 } 334 } 335 336 int mdio_read(int RegAddr) 337 { 338 int i, value = -1; 339 340 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 341 udelay(1000); 342 343 for (i = 2000; i > 0; i--) { 344 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 345 if (RTL_R32(PHYAR) & 0x80000000) { 346 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 347 break; 348 } else { 349 udelay(100); 350 } 351 } 352 return value; 353 } 354 355 static int rtl8169_init_board(struct eth_device *dev) 356 { 357 int i; 358 u32 tmp; 359 360 #ifdef DEBUG_RTL8169 361 printf ("%s\n", __FUNCTION__); 362 #endif 363 ioaddr = dev->iobase; 364 365 /* Soft reset the chip. */ 366 RTL_W8(ChipCmd, CmdReset); 367 368 /* Check that the chip has finished the reset. */ 369 for (i = 1000; i > 0; i--) 370 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 371 break; 372 else 373 udelay(10); 374 375 /* identify chip attached to board */ 376 tmp = RTL_R32(TxConfig); 377 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 378 379 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 380 if (tmp == rtl_chip_info[i].version) { 381 tpc->chipset = i; 382 goto match; 383 } 384 } 385 386 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 387 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 388 printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); 389 tpc->chipset = 0; 390 391 match: 392 return 0; 393 } 394 395 /************************************************************************** 396 RECV - Receive a frame 397 ***************************************************************************/ 398 static int rtl_recv(struct eth_device *dev) 399 { 400 /* return true if there's an ethernet packet ready to read */ 401 /* nic->packet should contain data on return */ 402 /* nic->packetlen should contain length of data */ 403 int cur_rx; 404 int length = 0; 405 406 #ifdef DEBUG_RTL8169_RX 407 printf ("%s\n", __FUNCTION__); 408 #endif 409 ioaddr = dev->iobase; 410 411 cur_rx = tpc->cur_rx; 412 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 413 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 414 unsigned char rxdata[RX_BUF_LEN]; 415 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 416 status) & 0x00001FFF) - 4; 417 418 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 419 NetReceive(rxdata, length); 420 421 if (cur_rx == NUM_RX_DESC - 1) 422 tpc->RxDescArray[cur_rx].status = 423 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 424 else 425 tpc->RxDescArray[cur_rx].status = 426 cpu_to_le32(OWNbit + RX_BUF_SIZE); 427 tpc->RxDescArray[cur_rx].buf_addr = 428 cpu_to_le32(tpc->RxBufferRing[cur_rx]); 429 } else { 430 puts("Error Rx"); 431 } 432 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 433 tpc->cur_rx = cur_rx; 434 return 1; 435 436 } 437 tpc->cur_rx = cur_rx; 438 return (0); /* initially as this is called to flush the input */ 439 } 440 441 #define HZ 1000 442 /************************************************************************** 443 SEND - Transmit a frame 444 ***************************************************************************/ 445 static int rtl_send(struct eth_device *dev, volatile void *packet, int length) 446 { 447 /* send the packet to destination */ 448 449 u32 to; 450 u8 *ptxb; 451 int entry = tpc->cur_tx % NUM_TX_DESC; 452 u32 len = length; 453 int ret; 454 455 #ifdef DEBUG_RTL8169_TX 456 int stime = currticks(); 457 printf ("%s\n", __FUNCTION__); 458 printf("sending %d bytes\n", len); 459 #endif 460 461 ioaddr = dev->iobase; 462 463 /* point to the current txb incase multiple tx_rings are used */ 464 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 465 memcpy(ptxb, (char *)packet, (int)length); 466 467 while (len < ETH_ZLEN) 468 ptxb[len++] = '\0'; 469 470 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(ptxb); 471 if (entry != (NUM_TX_DESC - 1)) { 472 tpc->TxDescArray[entry].status = 473 cpu_to_le32((OWNbit | FSbit | LSbit) | 474 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 475 } else { 476 tpc->TxDescArray[entry].status = 477 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 478 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 479 } 480 RTL_W8(TxPoll, 0x40); /* set polling bit */ 481 482 tpc->cur_tx++; 483 to = currticks() + TX_TIMEOUT; 484 while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 485 && (currticks() < to)); /* wait */ 486 487 if (currticks() >= to) { 488 #ifdef DEBUG_RTL8169_TX 489 puts ("tx timeout/error\n"); 490 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 491 #endif 492 ret = 0; 493 } else { 494 #ifdef DEBUG_RTL8169_TX 495 puts("tx done\n"); 496 #endif 497 ret = length; 498 } 499 /* Delay to make net console (nc) work properly */ 500 udelay(20); 501 return ret; 502 } 503 504 static void rtl8169_set_rx_mode(struct eth_device *dev) 505 { 506 u32 mc_filter[2]; /* Multicast hash filter */ 507 int rx_mode; 508 u32 tmp = 0; 509 510 #ifdef DEBUG_RTL8169 511 printf ("%s\n", __FUNCTION__); 512 #endif 513 514 /* IFF_ALLMULTI */ 515 /* Too many to filter perfectly -- accept all multicasts. */ 516 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 517 mc_filter[1] = mc_filter[0] = 0xffffffff; 518 519 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 520 rtl_chip_info[tpc->chipset].RxConfigMask); 521 522 RTL_W32(RxConfig, tmp); 523 RTL_W32(MAR0 + 0, mc_filter[0]); 524 RTL_W32(MAR0 + 4, mc_filter[1]); 525 } 526 527 static void rtl8169_hw_start(struct eth_device *dev) 528 { 529 u32 i; 530 531 #ifdef DEBUG_RTL8169 532 int stime = currticks(); 533 printf ("%s\n", __FUNCTION__); 534 #endif 535 536 #if 0 537 /* Soft reset the chip. */ 538 RTL_W8(ChipCmd, CmdReset); 539 540 /* Check that the chip has finished the reset. */ 541 for (i = 1000; i > 0; i--) { 542 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 543 break; 544 else 545 udelay(10); 546 } 547 #endif 548 549 RTL_W8(Cfg9346, Cfg9346_Unlock); 550 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 551 RTL_W8(EarlyTxThres, EarlyTxThld); 552 553 /* For gigabit rtl8169 */ 554 RTL_W16(RxMaxSize, RxPacketMaxSize); 555 556 /* Set Rx Config register */ 557 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 558 rtl_chip_info[tpc->chipset].RxConfigMask); 559 RTL_W32(RxConfig, i); 560 561 /* Set DMA burst size and Interframe Gap Time */ 562 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 563 (InterFrameGap << TxInterFrameGapShift)); 564 565 566 tpc->cur_rx = 0; 567 568 RTL_W32(TxDescStartAddr, tpc->TxDescArray); 569 RTL_W32(RxDescStartAddr, tpc->RxDescArray); 570 RTL_W8(Cfg9346, Cfg9346_Lock); 571 udelay(10); 572 573 RTL_W32(RxMissed, 0); 574 575 rtl8169_set_rx_mode(dev); 576 577 /* no early-rx interrupts */ 578 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 579 580 #ifdef DEBUG_RTL8169 581 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 582 #endif 583 } 584 585 static void rtl8169_init_ring(struct eth_device *dev) 586 { 587 int i; 588 589 #ifdef DEBUG_RTL8169 590 int stime = currticks(); 591 printf ("%s\n", __FUNCTION__); 592 #endif 593 594 tpc->cur_rx = 0; 595 tpc->cur_tx = 0; 596 tpc->dirty_tx = 0; 597 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 598 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 599 600 for (i = 0; i < NUM_TX_DESC; i++) { 601 tpc->Tx_skbuff[i] = &txb[i]; 602 } 603 604 for (i = 0; i < NUM_RX_DESC; i++) { 605 if (i == (NUM_RX_DESC - 1)) 606 tpc->RxDescArray[i].status = 607 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 608 else 609 tpc->RxDescArray[i].status = 610 cpu_to_le32(OWNbit + RX_BUF_SIZE); 611 612 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 613 tpc->RxDescArray[i].buf_addr = 614 cpu_to_le32(tpc->RxBufferRing[i]); 615 } 616 617 #ifdef DEBUG_RTL8169 618 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 619 #endif 620 } 621 622 /************************************************************************** 623 RESET - Finish setting up the ethernet interface 624 ***************************************************************************/ 625 static int rtl_reset(struct eth_device *dev, bd_t *bis) 626 { 627 int i; 628 629 #ifdef DEBUG_RTL8169 630 int stime = currticks(); 631 printf ("%s\n", __FUNCTION__); 632 #endif 633 634 tpc->TxDescArrays = tx_ring; 635 /* Tx Desscriptor needs 256 bytes alignment; */ 636 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 637 255) & ~255); 638 639 tpc->RxDescArrays = rx_ring; 640 /* Rx Desscriptor needs 256 bytes alignment; */ 641 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 642 255) & ~255); 643 644 rtl8169_init_ring(dev); 645 rtl8169_hw_start(dev); 646 /* Construct a perfect filter frame with the mac address as first match 647 * and broadcast for all others */ 648 for (i = 0; i < 192; i++) 649 txb[i] = 0xFF; 650 651 txb[0] = dev->enetaddr[0]; 652 txb[1] = dev->enetaddr[1]; 653 txb[2] = dev->enetaddr[2]; 654 txb[3] = dev->enetaddr[3]; 655 txb[4] = dev->enetaddr[4]; 656 txb[5] = dev->enetaddr[5]; 657 658 #ifdef DEBUG_RTL8169 659 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 660 #endif 661 return 0; 662 } 663 664 /************************************************************************** 665 HALT - Turn off ethernet interface 666 ***************************************************************************/ 667 static void rtl_halt(struct eth_device *dev) 668 { 669 int i; 670 671 #ifdef DEBUG_RTL8169 672 printf ("%s\n", __FUNCTION__); 673 #endif 674 675 ioaddr = dev->iobase; 676 677 /* Stop the chip's Tx and Rx DMA processes. */ 678 RTL_W8(ChipCmd, 0x00); 679 680 /* Disable interrupts by clearing the interrupt mask. */ 681 RTL_W16(IntrMask, 0x0000); 682 683 RTL_W32(RxMissed, 0); 684 685 tpc->TxDescArrays = NULL; 686 tpc->RxDescArrays = NULL; 687 tpc->TxDescArray = NULL; 688 tpc->RxDescArray = NULL; 689 for (i = 0; i < NUM_RX_DESC; i++) { 690 tpc->RxBufferRing[i] = NULL; 691 } 692 } 693 694 /************************************************************************** 695 INIT - Look for an adapter, this routine's visible to the outside 696 ***************************************************************************/ 697 698 #define board_found 1 699 #define valid_link 0 700 static int rtl_init(struct eth_device *dev, bd_t *bis) 701 { 702 static int board_idx = -1; 703 static int printed_version = 0; 704 int i, rc; 705 int option = -1, Cap10_100 = 0, Cap1000 = 0; 706 707 #ifdef DEBUG_RTL8169 708 printf ("%s\n", __FUNCTION__); 709 #endif 710 711 ioaddr = dev->iobase; 712 713 board_idx++; 714 715 printed_version = 1; 716 717 /* point to private storage */ 718 tpc = &tpx; 719 720 rc = rtl8169_init_board(dev); 721 if (rc) 722 return rc; 723 724 /* Get MAC address. FIXME: read EEPROM */ 725 for (i = 0; i < MAC_ADDR_LEN; i++) 726 bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); 727 728 #ifdef DEBUG_RTL8169 729 printf("MAC Address"); 730 for (i = 0; i < MAC_ADDR_LEN; i++) 731 printf(":%02x", dev->enetaddr[i]); 732 putc('\n'); 733 #endif 734 735 #ifdef DEBUG_RTL8169 736 /* Print out some hardware info */ 737 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 738 #endif 739 740 /* if TBI is not endbled */ 741 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 742 int val = mdio_read(PHY_AUTO_NEGO_REG); 743 744 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 745 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 746 if (option > 0) { 747 #ifdef DEBUG_RTL8169 748 printf("%s: Force-mode Enabled.\n", dev->name); 749 #endif 750 Cap10_100 = 0, Cap1000 = 0; 751 switch (option) { 752 case _10_Half: 753 Cap10_100 = PHY_Cap_10_Half; 754 Cap1000 = PHY_Cap_Null; 755 break; 756 case _10_Full: 757 Cap10_100 = PHY_Cap_10_Full; 758 Cap1000 = PHY_Cap_Null; 759 break; 760 case _100_Half: 761 Cap10_100 = PHY_Cap_100_Half; 762 Cap1000 = PHY_Cap_Null; 763 break; 764 case _100_Full: 765 Cap10_100 = PHY_Cap_100_Full; 766 Cap1000 = PHY_Cap_Null; 767 break; 768 case _1000_Full: 769 Cap10_100 = PHY_Cap_Null; 770 Cap1000 = PHY_Cap_1000_Full; 771 break; 772 default: 773 break; 774 } 775 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 776 mdio_write(PHY_1000_CTRL_REG, Cap1000); 777 } else { 778 #ifdef DEBUG_RTL8169 779 printf("%s: Auto-negotiation Enabled.\n", 780 dev->name); 781 #endif 782 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 783 mdio_write(PHY_AUTO_NEGO_REG, 784 PHY_Cap_10_Half | PHY_Cap_10_Full | 785 PHY_Cap_100_Half | PHY_Cap_100_Full | 786 (val & 0x1F)); 787 788 /* enable 1000 Full Mode */ 789 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 790 791 } 792 793 /* Enable auto-negotiation and restart auto-nigotiation */ 794 mdio_write(PHY_CTRL_REG, 795 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 796 udelay(100); 797 798 /* wait for auto-negotiation process */ 799 for (i = 10000; i > 0; i--) { 800 /* check if auto-negotiation complete */ 801 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 802 udelay(100); 803 option = RTL_R8(PHYstatus); 804 if (option & _1000bpsF) { 805 #ifdef DEBUG_RTL8169 806 printf("%s: 1000Mbps Full-duplex operation.\n", 807 dev->name); 808 #endif 809 } else { 810 #ifdef DEBUG_RTL8169 811 printf("%s: %sMbps %s-duplex operation.\n", 812 dev->name, 813 (option & _100bps) ? "100" : 814 "10", 815 (option & FullDup) ? "Full" : 816 "Half"); 817 #endif 818 } 819 break; 820 } else { 821 udelay(100); 822 } 823 } /* end for-loop to wait for auto-negotiation process */ 824 825 } else { 826 udelay(100); 827 #ifdef DEBUG_RTL8169 828 printf 829 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 830 dev->name, 831 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 832 #endif 833 } 834 835 return 1; 836 } 837 838 int rtl8169_initialize(bd_t *bis) 839 { 840 pci_dev_t devno; 841 int card_number = 0; 842 struct eth_device *dev; 843 u32 iobase; 844 int idx=0; 845 846 while(1){ 847 /* Find RTL8169 */ 848 if ((devno = pci_find_devices(supported, idx++)) < 0) 849 break; 850 851 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 852 iobase &= ~0xf; 853 854 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 855 856 dev = (struct eth_device *)malloc(sizeof *dev); 857 858 sprintf (dev->name, "RTL8169#%d", card_number); 859 860 dev->priv = (void *) devno; 861 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 862 863 dev->init = rtl_reset; 864 dev->halt = rtl_halt; 865 dev->send = rtl_send; 866 dev->recv = rtl_recv; 867 868 eth_register (dev); 869 870 rtl_init(dev, bis); 871 872 card_number++; 873 } 874 return card_number; 875 } 876 877 #endif 878