1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * rtl8169.c : U-Boot driver for the RealTek RTL8169 4 * 5 * Masami Komiya (mkomiya@sonare.it) 6 * 7 * Most part is taken from r8169.c of etherboot 8 * 9 */ 10 11 /************************************************************************** 12 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 13 * Written 2003 by Timothy Legge <tlegge@rogers.com> 14 * 15 * Portions of this code based on: 16 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 17 * for Linux kernel 2.4.x. 18 * 19 * Written 2002 ShuChen <shuchen@realtek.com.tw> 20 * See Linux Driver for full information 21 * 22 * Linux Driver Version 1.27a, 10.02.2002 23 * 24 * Thanks to: 25 * Jean Chen of RealTek Semiconductor Corp. for 26 * providing the evaluation NIC used to develop 27 * this driver. RealTek's support for Etherboot 28 * is appreciated. 29 * 30 * REVISION HISTORY: 31 * ================ 32 * 33 * v1.0 11-26-2003 timlegge Initial port of Linux driver 34 * v1.5 01-17-2004 timlegge Initial driver output cleanup 35 * 36 * Indent Options: indent -kr -i8 37 ***************************************************************************/ 38 /* 39 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 40 * Modified to use le32_to_cpu and cpu_to_le32 properly 41 */ 42 #include <common.h> 43 #include <dm.h> 44 #include <errno.h> 45 #include <malloc.h> 46 #include <memalign.h> 47 #include <net.h> 48 #ifndef CONFIG_DM_ETH 49 #include <netdev.h> 50 #endif 51 #include <asm/io.h> 52 #include <pci.h> 53 54 #undef DEBUG_RTL8169 55 #undef DEBUG_RTL8169_TX 56 #undef DEBUG_RTL8169_RX 57 58 #define drv_version "v1.5" 59 #define drv_date "01-17-2004" 60 61 static unsigned long ioaddr; 62 63 /* Condensed operations for readability. */ 64 #define currticks() get_timer(0) 65 66 /* media options */ 67 #define MAX_UNITS 8 68 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 69 70 /* MAC address length*/ 71 #define MAC_ADDR_LEN 6 72 73 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 74 #define MAX_ETH_FRAME_SIZE 1536 75 76 #define TX_FIFO_THRESH 256 /* In bytes */ 77 78 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 79 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 80 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 81 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 82 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 83 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 84 85 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 86 #ifdef CONFIG_SYS_RX_ETH_BUFFER 87 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER 88 #else 89 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 90 #endif 91 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 92 #define RX_BUF_LEN 8192 93 94 #define RTL_MIN_IO_SIZE 0x80 95 #define TX_TIMEOUT (6*HZ) 96 97 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 98 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg)) 99 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg)) 100 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg)) 101 #define RTL_R8(reg) readb(ioaddr + (reg)) 102 #define RTL_R16(reg) readw(ioaddr + (reg)) 103 #define RTL_R32(reg) readl(ioaddr + (reg)) 104 105 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \ 106 (pci_addr_t)(unsigned long)a) 107 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \ 108 (phys_addr_t)a) 109 110 enum RTL8169_registers { 111 MAC0 = 0, /* Ethernet hardware address. */ 112 MAR0 = 8, /* Multicast filter. */ 113 TxDescStartAddrLow = 0x20, 114 TxDescStartAddrHigh = 0x24, 115 TxHDescStartAddrLow = 0x28, 116 TxHDescStartAddrHigh = 0x2c, 117 FLASH = 0x30, 118 ERSR = 0x36, 119 ChipCmd = 0x37, 120 TxPoll = 0x38, 121 IntrMask = 0x3C, 122 IntrStatus = 0x3E, 123 TxConfig = 0x40, 124 RxConfig = 0x44, 125 RxMissed = 0x4C, 126 Cfg9346 = 0x50, 127 Config0 = 0x51, 128 Config1 = 0x52, 129 Config2 = 0x53, 130 Config3 = 0x54, 131 Config4 = 0x55, 132 Config5 = 0x56, 133 MultiIntr = 0x5C, 134 PHYAR = 0x60, 135 TBICSR = 0x64, 136 TBI_ANAR = 0x68, 137 TBI_LPAR = 0x6A, 138 PHYstatus = 0x6C, 139 RxMaxSize = 0xDA, 140 CPlusCmd = 0xE0, 141 RxDescStartAddrLow = 0xE4, 142 RxDescStartAddrHigh = 0xE8, 143 EarlyTxThres = 0xEC, 144 FuncEvent = 0xF0, 145 FuncEventMask = 0xF4, 146 FuncPresetState = 0xF8, 147 FuncForceEvent = 0xFC, 148 }; 149 150 enum RTL8169_register_content { 151 /*InterruptStatusBits */ 152 SYSErr = 0x8000, 153 PCSTimeout = 0x4000, 154 SWInt = 0x0100, 155 TxDescUnavail = 0x80, 156 RxFIFOOver = 0x40, 157 RxUnderrun = 0x20, 158 RxOverflow = 0x10, 159 TxErr = 0x08, 160 TxOK = 0x04, 161 RxErr = 0x02, 162 RxOK = 0x01, 163 164 /*RxStatusDesc */ 165 RxRES = 0x00200000, 166 RxCRC = 0x00080000, 167 RxRUNT = 0x00100000, 168 RxRWT = 0x00400000, 169 170 /*ChipCmdBits */ 171 CmdReset = 0x10, 172 CmdRxEnb = 0x08, 173 CmdTxEnb = 0x04, 174 RxBufEmpty = 0x01, 175 176 /*Cfg9346Bits */ 177 Cfg9346_Lock = 0x00, 178 Cfg9346_Unlock = 0xC0, 179 180 /*rx_mode_bits */ 181 AcceptErr = 0x20, 182 AcceptRunt = 0x10, 183 AcceptBroadcast = 0x08, 184 AcceptMulticast = 0x04, 185 AcceptMyPhys = 0x02, 186 AcceptAllPhys = 0x01, 187 188 /*RxConfigBits */ 189 RxCfgFIFOShift = 13, 190 RxCfgDMAShift = 8, 191 192 /*TxConfigBits */ 193 TxInterFrameGapShift = 24, 194 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 195 196 /*rtl8169_PHYstatus */ 197 TBI_Enable = 0x80, 198 TxFlowCtrl = 0x40, 199 RxFlowCtrl = 0x20, 200 _1000bpsF = 0x10, 201 _100bps = 0x08, 202 _10bps = 0x04, 203 LinkStatus = 0x02, 204 FullDup = 0x01, 205 206 /*GIGABIT_PHY_registers */ 207 PHY_CTRL_REG = 0, 208 PHY_STAT_REG = 1, 209 PHY_AUTO_NEGO_REG = 4, 210 PHY_1000_CTRL_REG = 9, 211 212 /*GIGABIT_PHY_REG_BIT */ 213 PHY_Restart_Auto_Nego = 0x0200, 214 PHY_Enable_Auto_Nego = 0x1000, 215 216 /* PHY_STAT_REG = 1; */ 217 PHY_Auto_Nego_Comp = 0x0020, 218 219 /* PHY_AUTO_NEGO_REG = 4; */ 220 PHY_Cap_10_Half = 0x0020, 221 PHY_Cap_10_Full = 0x0040, 222 PHY_Cap_100_Half = 0x0080, 223 PHY_Cap_100_Full = 0x0100, 224 225 /* PHY_1000_CTRL_REG = 9; */ 226 PHY_Cap_1000_Full = 0x0200, 227 228 PHY_Cap_Null = 0x0, 229 230 /*_MediaType*/ 231 _10_Half = 0x01, 232 _10_Full = 0x02, 233 _100_Half = 0x04, 234 _100_Full = 0x08, 235 _1000_Full = 0x10, 236 237 /*_TBICSRBit*/ 238 TBILinkOK = 0x02000000, 239 }; 240 241 static struct { 242 const char *name; 243 u8 version; /* depend on RTL8169 docs */ 244 u32 RxConfigMask; /* should clear the bits supported by this chip */ 245 } rtl_chip_info[] = { 246 {"RTL-8169", 0x00, 0xff7e1880,}, 247 {"RTL-8169", 0x04, 0xff7e1880,}, 248 {"RTL-8169", 0x00, 0xff7e1880,}, 249 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 250 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 251 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 252 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 253 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 254 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 255 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 256 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 257 {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, 258 {"RTL-8101e", 0x34, 0xff7e1880,}, 259 {"RTL-8100e", 0x32, 0xff7e1880,}, 260 }; 261 262 enum _DescStatusBit { 263 OWNbit = 0x80000000, 264 EORbit = 0x40000000, 265 FSbit = 0x20000000, 266 LSbit = 0x10000000, 267 }; 268 269 struct TxDesc { 270 u32 status; 271 u32 vlan_tag; 272 u32 buf_addr; 273 u32 buf_Haddr; 274 }; 275 276 struct RxDesc { 277 u32 status; 278 u32 vlan_tag; 279 u32 buf_addr; 280 u32 buf_Haddr; 281 }; 282 283 static unsigned char rxdata[RX_BUF_LEN]; 284 285 #define RTL8169_DESC_SIZE 16 286 287 #if ARCH_DMA_MINALIGN > 256 288 # define RTL8169_ALIGN ARCH_DMA_MINALIGN 289 #else 290 # define RTL8169_ALIGN 256 291 #endif 292 293 /* 294 * Warn if the cache-line size is larger than the descriptor size. In such 295 * cases the driver will likely fail because the CPU needs to flush the cache 296 * when requeuing RX buffers, therefore descriptors written by the hardware 297 * may be discarded. 298 * 299 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 300 * the driver to allocate descriptors from a pool of non-cached memory. 301 */ 302 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN 303 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ 304 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) 305 #warning cache-line size is larger than descriptor size 306 #endif 307 #endif 308 309 /* 310 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All 311 * descriptors point to a part of this buffer. 312 */ 313 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 314 315 /* 316 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All 317 * descriptors point to a part of this buffer. 318 */ 319 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 320 321 struct rtl8169_private { 322 ulong iobase; 323 void *mmio_addr; /* memory map physical address */ 324 int chipset; 325 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 326 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 327 unsigned long dirty_tx; 328 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 329 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 330 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 331 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 332 unsigned char *Tx_skbuff[NUM_TX_DESC]; 333 } tpx; 334 335 static struct rtl8169_private *tpc; 336 337 static const unsigned int rtl8169_rx_config = 338 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 339 340 static struct pci_device_id supported[] = { 341 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, 342 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, 343 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, 344 {} 345 }; 346 347 void mdio_write(int RegAddr, int value) 348 { 349 int i; 350 351 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 352 udelay(1000); 353 354 for (i = 2000; i > 0; i--) { 355 /* Check if the RTL8169 has completed writing to the specified MII register */ 356 if (!(RTL_R32(PHYAR) & 0x80000000)) { 357 break; 358 } else { 359 udelay(100); 360 } 361 } 362 } 363 364 int mdio_read(int RegAddr) 365 { 366 int i, value = -1; 367 368 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 369 udelay(1000); 370 371 for (i = 2000; i > 0; i--) { 372 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 373 if (RTL_R32(PHYAR) & 0x80000000) { 374 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 375 break; 376 } else { 377 udelay(100); 378 } 379 } 380 return value; 381 } 382 383 static int rtl8169_init_board(unsigned long dev_iobase, const char *name) 384 { 385 int i; 386 u32 tmp; 387 388 #ifdef DEBUG_RTL8169 389 printf ("%s\n", __FUNCTION__); 390 #endif 391 ioaddr = dev_iobase; 392 393 /* Soft reset the chip. */ 394 RTL_W8(ChipCmd, CmdReset); 395 396 /* Check that the chip has finished the reset. */ 397 for (i = 1000; i > 0; i--) 398 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 399 break; 400 else 401 udelay(10); 402 403 /* identify chip attached to board */ 404 tmp = RTL_R32(TxConfig); 405 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 406 407 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 408 if (tmp == rtl_chip_info[i].version) { 409 tpc->chipset = i; 410 goto match; 411 } 412 } 413 414 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 415 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", 416 name); 417 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 418 tpc->chipset = 0; 419 420 match: 421 return 0; 422 } 423 424 /* 425 * TX and RX descriptors are 16 bytes. This causes problems with the cache 426 * maintenance on CPUs where the cache-line size exceeds the size of these 427 * descriptors. What will happen is that when the driver receives a packet 428 * it will be immediately requeued for the hardware to reuse. The CPU will 429 * therefore need to flush the cache-line containing the descriptor, which 430 * will cause all other descriptors in the same cache-line to be flushed 431 * along with it. If one of those descriptors had been written to by the 432 * device those changes (and the associated packet) will be lost. 433 * 434 * To work around this, we make use of non-cached memory if available. If 435 * descriptors are mapped uncached there's no need to manually flush them 436 * or invalidate them. 437 * 438 * Note that this only applies to descriptors. The packet data buffers do 439 * not have the same constraints since they are 1536 bytes large, so they 440 * are unlikely to share cache-lines. 441 */ 442 static void *rtl_alloc_descs(unsigned int num) 443 { 444 size_t size = num * RTL8169_DESC_SIZE; 445 446 #ifdef CONFIG_SYS_NONCACHED_MEMORY 447 return (void *)noncached_alloc(size, RTL8169_ALIGN); 448 #else 449 return memalign(RTL8169_ALIGN, size); 450 #endif 451 } 452 453 /* 454 * Cache maintenance functions. These are simple wrappers around the more 455 * general purpose flush_cache() and invalidate_dcache_range() functions. 456 */ 457 458 static void rtl_inval_rx_desc(struct RxDesc *desc) 459 { 460 #ifndef CONFIG_SYS_NONCACHED_MEMORY 461 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 462 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 463 464 invalidate_dcache_range(start, end); 465 #endif 466 } 467 468 static void rtl_flush_rx_desc(struct RxDesc *desc) 469 { 470 #ifndef CONFIG_SYS_NONCACHED_MEMORY 471 flush_cache((unsigned long)desc, sizeof(*desc)); 472 #endif 473 } 474 475 static void rtl_inval_tx_desc(struct TxDesc *desc) 476 { 477 #ifndef CONFIG_SYS_NONCACHED_MEMORY 478 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 479 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 480 481 invalidate_dcache_range(start, end); 482 #endif 483 } 484 485 static void rtl_flush_tx_desc(struct TxDesc *desc) 486 { 487 #ifndef CONFIG_SYS_NONCACHED_MEMORY 488 flush_cache((unsigned long)desc, sizeof(*desc)); 489 #endif 490 } 491 492 static void rtl_inval_buffer(void *buf, size_t size) 493 { 494 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 495 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 496 497 invalidate_dcache_range(start, end); 498 } 499 500 static void rtl_flush_buffer(void *buf, size_t size) 501 { 502 flush_cache((unsigned long)buf, size); 503 } 504 505 /************************************************************************** 506 RECV - Receive a frame 507 ***************************************************************************/ 508 #ifdef CONFIG_DM_ETH 509 static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, 510 uchar **packetp) 511 #else 512 static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase, 513 uchar **packetp) 514 #endif 515 { 516 /* return true if there's an ethernet packet ready to read */ 517 /* nic->packet should contain data on return */ 518 /* nic->packetlen should contain length of data */ 519 int cur_rx; 520 int length = 0; 521 522 #ifdef DEBUG_RTL8169_RX 523 printf ("%s\n", __FUNCTION__); 524 #endif 525 ioaddr = dev_iobase; 526 527 cur_rx = tpc->cur_rx; 528 529 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 530 531 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 532 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 533 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 534 status) & 0x00001FFF) - 4; 535 536 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 537 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 538 539 if (cur_rx == NUM_RX_DESC - 1) 540 tpc->RxDescArray[cur_rx].status = 541 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 542 else 543 tpc->RxDescArray[cur_rx].status = 544 cpu_to_le32(OWNbit + RX_BUF_SIZE); 545 #ifdef CONFIG_DM_ETH 546 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( 547 dm_pci_mem_to_phys(dev, 548 (pci_addr_t)(unsigned long) 549 tpc->RxBufferRing[cur_rx])); 550 #else 551 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( 552 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long) 553 tpc->RxBufferRing[cur_rx])); 554 #endif 555 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 556 #ifdef CONFIG_DM_ETH 557 *packetp = rxdata; 558 #else 559 net_process_received_packet(rxdata, length); 560 #endif 561 } else { 562 puts("Error Rx"); 563 length = -EIO; 564 } 565 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 566 tpc->cur_rx = cur_rx; 567 return length; 568 569 } else { 570 ushort sts = RTL_R8(IntrStatus); 571 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 572 udelay(100); /* wait */ 573 } 574 tpc->cur_rx = cur_rx; 575 return (0); /* initially as this is called to flush the input */ 576 } 577 578 #ifdef CONFIG_DM_ETH 579 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) 580 { 581 struct rtl8169_private *priv = dev_get_priv(dev); 582 583 return rtl_recv_common(dev, priv->iobase, packetp); 584 } 585 #else 586 static int rtl_recv(struct eth_device *dev) 587 { 588 return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv, 589 dev->iobase, NULL); 590 } 591 #endif /* nCONFIG_DM_ETH */ 592 593 #define HZ 1000 594 /************************************************************************** 595 SEND - Transmit a frame 596 ***************************************************************************/ 597 #ifdef CONFIG_DM_ETH 598 static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, 599 void *packet, int length) 600 #else 601 static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, 602 void *packet, int length) 603 #endif 604 { 605 /* send the packet to destination */ 606 607 u32 to; 608 u8 *ptxb; 609 int entry = tpc->cur_tx % NUM_TX_DESC; 610 u32 len = length; 611 int ret; 612 613 #ifdef DEBUG_RTL8169_TX 614 int stime = currticks(); 615 printf ("%s\n", __FUNCTION__); 616 printf("sending %d bytes\n", len); 617 #endif 618 619 ioaddr = dev_iobase; 620 621 /* point to the current txb incase multiple tx_rings are used */ 622 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 623 memcpy(ptxb, (char *)packet, (int)length); 624 625 while (len < ETH_ZLEN) 626 ptxb[len++] = '\0'; 627 628 rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN)); 629 630 tpc->TxDescArray[entry].buf_Haddr = 0; 631 #ifdef CONFIG_DM_ETH 632 tpc->TxDescArray[entry].buf_addr = cpu_to_le32( 633 dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); 634 #else 635 tpc->TxDescArray[entry].buf_addr = cpu_to_le32( 636 pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); 637 #endif 638 if (entry != (NUM_TX_DESC - 1)) { 639 tpc->TxDescArray[entry].status = 640 cpu_to_le32((OWNbit | FSbit | LSbit) | 641 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 642 } else { 643 tpc->TxDescArray[entry].status = 644 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 645 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 646 } 647 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 648 RTL_W8(TxPoll, 0x40); /* set polling bit */ 649 650 tpc->cur_tx++; 651 to = currticks() + TX_TIMEOUT; 652 do { 653 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 654 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 655 && (currticks() < to)); /* wait */ 656 657 if (currticks() >= to) { 658 #ifdef DEBUG_RTL8169_TX 659 puts("tx timeout/error\n"); 660 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 661 #endif 662 ret = -ETIMEDOUT; 663 } else { 664 #ifdef DEBUG_RTL8169_TX 665 puts("tx done\n"); 666 #endif 667 ret = 0; 668 } 669 /* Delay to make net console (nc) work properly */ 670 udelay(20); 671 return ret; 672 } 673 674 #ifdef CONFIG_DM_ETH 675 int rtl8169_eth_send(struct udevice *dev, void *packet, int length) 676 { 677 struct rtl8169_private *priv = dev_get_priv(dev); 678 679 return rtl_send_common(dev, priv->iobase, packet, length); 680 } 681 682 #else 683 static int rtl_send(struct eth_device *dev, void *packet, int length) 684 { 685 return rtl_send_common((pci_dev_t)(unsigned long)dev->priv, 686 dev->iobase, packet, length); 687 } 688 #endif 689 690 static void rtl8169_set_rx_mode(void) 691 { 692 u32 mc_filter[2]; /* Multicast hash filter */ 693 int rx_mode; 694 u32 tmp = 0; 695 696 #ifdef DEBUG_RTL8169 697 printf ("%s\n", __FUNCTION__); 698 #endif 699 700 /* IFF_ALLMULTI */ 701 /* Too many to filter perfectly -- accept all multicasts. */ 702 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 703 mc_filter[1] = mc_filter[0] = 0xffffffff; 704 705 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 706 rtl_chip_info[tpc->chipset].RxConfigMask); 707 708 RTL_W32(RxConfig, tmp); 709 RTL_W32(MAR0 + 0, mc_filter[0]); 710 RTL_W32(MAR0 + 4, mc_filter[1]); 711 } 712 713 #ifdef CONFIG_DM_ETH 714 static void rtl8169_hw_start(struct udevice *dev) 715 #else 716 static void rtl8169_hw_start(pci_dev_t dev) 717 #endif 718 { 719 u32 i; 720 721 #ifdef DEBUG_RTL8169 722 int stime = currticks(); 723 printf ("%s\n", __FUNCTION__); 724 #endif 725 726 #if 0 727 /* Soft reset the chip. */ 728 RTL_W8(ChipCmd, CmdReset); 729 730 /* Check that the chip has finished the reset. */ 731 for (i = 1000; i > 0; i--) { 732 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 733 break; 734 else 735 udelay(10); 736 } 737 #endif 738 739 RTL_W8(Cfg9346, Cfg9346_Unlock); 740 741 /* RTL-8169sb/8110sb or previous version */ 742 if (tpc->chipset <= 5) 743 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 744 745 RTL_W8(EarlyTxThres, EarlyTxThld); 746 747 /* For gigabit rtl8169 */ 748 RTL_W16(RxMaxSize, RxPacketMaxSize); 749 750 /* Set Rx Config register */ 751 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 752 rtl_chip_info[tpc->chipset].RxConfigMask); 753 RTL_W32(RxConfig, i); 754 755 /* Set DMA burst size and Interframe Gap Time */ 756 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 757 (InterFrameGap << TxInterFrameGapShift)); 758 759 760 tpc->cur_rx = 0; 761 762 #ifdef CONFIG_DM_ETH 763 RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev, 764 (pci_addr_t)(unsigned long)tpc->TxDescArray)); 765 #else 766 RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev, 767 (pci_addr_t)(unsigned long)tpc->TxDescArray)); 768 #endif 769 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 770 #ifdef CONFIG_DM_ETH 771 RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys( 772 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); 773 #else 774 RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( 775 dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); 776 #endif 777 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 778 779 /* RTL-8169sc/8110sc or later version */ 780 if (tpc->chipset > 5) 781 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 782 783 RTL_W8(Cfg9346, Cfg9346_Lock); 784 udelay(10); 785 786 RTL_W32(RxMissed, 0); 787 788 rtl8169_set_rx_mode(); 789 790 /* no early-rx interrupts */ 791 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 792 793 #ifdef DEBUG_RTL8169 794 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 795 #endif 796 } 797 798 #ifdef CONFIG_DM_ETH 799 static void rtl8169_init_ring(struct udevice *dev) 800 #else 801 static void rtl8169_init_ring(pci_dev_t dev) 802 #endif 803 { 804 int i; 805 806 #ifdef DEBUG_RTL8169 807 int stime = currticks(); 808 printf ("%s\n", __FUNCTION__); 809 #endif 810 811 tpc->cur_rx = 0; 812 tpc->cur_tx = 0; 813 tpc->dirty_tx = 0; 814 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 815 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 816 817 for (i = 0; i < NUM_TX_DESC; i++) { 818 tpc->Tx_skbuff[i] = &txb[i]; 819 } 820 821 for (i = 0; i < NUM_RX_DESC; i++) { 822 if (i == (NUM_RX_DESC - 1)) 823 tpc->RxDescArray[i].status = 824 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 825 else 826 tpc->RxDescArray[i].status = 827 cpu_to_le32(OWNbit + RX_BUF_SIZE); 828 829 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 830 #ifdef CONFIG_DM_ETH 831 tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys( 832 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); 833 #else 834 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( 835 dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); 836 #endif 837 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 838 } 839 840 #ifdef DEBUG_RTL8169 841 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 842 #endif 843 } 844 845 #ifdef CONFIG_DM_ETH 846 static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr, 847 unsigned long dev_iobase) 848 #else 849 static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr, 850 unsigned long dev_iobase) 851 #endif 852 { 853 int i; 854 855 #ifdef DEBUG_RTL8169 856 int stime = currticks(); 857 printf ("%s\n", __FUNCTION__); 858 #endif 859 860 ioaddr = dev_iobase; 861 862 rtl8169_init_ring(dev); 863 rtl8169_hw_start(dev); 864 /* Construct a perfect filter frame with the mac address as first match 865 * and broadcast for all others */ 866 for (i = 0; i < 192; i++) 867 txb[i] = 0xFF; 868 869 txb[0] = enetaddr[0]; 870 txb[1] = enetaddr[1]; 871 txb[2] = enetaddr[2]; 872 txb[3] = enetaddr[3]; 873 txb[4] = enetaddr[4]; 874 txb[5] = enetaddr[5]; 875 876 #ifdef DEBUG_RTL8169 877 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 878 #endif 879 } 880 881 #ifdef CONFIG_DM_ETH 882 static int rtl8169_eth_start(struct udevice *dev) 883 { 884 struct eth_pdata *plat = dev_get_platdata(dev); 885 struct rtl8169_private *priv = dev_get_priv(dev); 886 887 rtl8169_common_start(dev, plat->enetaddr, priv->iobase); 888 889 return 0; 890 } 891 #else 892 /************************************************************************** 893 RESET - Finish setting up the ethernet interface 894 ***************************************************************************/ 895 static int rtl_reset(struct eth_device *dev, bd_t *bis) 896 { 897 rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv, 898 dev->enetaddr, dev->iobase); 899 900 return 0; 901 } 902 #endif /* nCONFIG_DM_ETH */ 903 904 static void rtl_halt_common(unsigned long dev_iobase) 905 { 906 int i; 907 908 #ifdef DEBUG_RTL8169 909 printf ("%s\n", __FUNCTION__); 910 #endif 911 912 ioaddr = dev_iobase; 913 914 /* Stop the chip's Tx and Rx DMA processes. */ 915 RTL_W8(ChipCmd, 0x00); 916 917 /* Disable interrupts by clearing the interrupt mask. */ 918 RTL_W16(IntrMask, 0x0000); 919 920 RTL_W32(RxMissed, 0); 921 922 for (i = 0; i < NUM_RX_DESC; i++) { 923 tpc->RxBufferRing[i] = NULL; 924 } 925 } 926 927 #ifdef CONFIG_DM_ETH 928 void rtl8169_eth_stop(struct udevice *dev) 929 { 930 struct rtl8169_private *priv = dev_get_priv(dev); 931 932 rtl_halt_common(priv->iobase); 933 } 934 #else 935 /************************************************************************** 936 HALT - Turn off ethernet interface 937 ***************************************************************************/ 938 static void rtl_halt(struct eth_device *dev) 939 { 940 rtl_halt_common(dev->iobase); 941 } 942 #endif 943 944 /************************************************************************** 945 INIT - Look for an adapter, this routine's visible to the outside 946 ***************************************************************************/ 947 948 #define board_found 1 949 #define valid_link 0 950 static int rtl_init(unsigned long dev_ioaddr, const char *name, 951 unsigned char *enetaddr) 952 { 953 static int board_idx = -1; 954 int i, rc; 955 int option = -1, Cap10_100 = 0, Cap1000 = 0; 956 957 #ifdef DEBUG_RTL8169 958 printf ("%s\n", __FUNCTION__); 959 #endif 960 ioaddr = dev_ioaddr; 961 962 board_idx++; 963 964 /* point to private storage */ 965 tpc = &tpx; 966 967 rc = rtl8169_init_board(ioaddr, name); 968 if (rc) 969 return rc; 970 971 /* Get MAC address. FIXME: read EEPROM */ 972 for (i = 0; i < MAC_ADDR_LEN; i++) 973 enetaddr[i] = RTL_R8(MAC0 + i); 974 975 #ifdef DEBUG_RTL8169 976 printf("chipset = %d\n", tpc->chipset); 977 printf("MAC Address"); 978 for (i = 0; i < MAC_ADDR_LEN; i++) 979 printf(":%02x", enetaddr[i]); 980 putc('\n'); 981 #endif 982 983 #ifdef DEBUG_RTL8169 984 /* Print out some hardware info */ 985 printf("%s: at ioaddr 0x%lx\n", name, ioaddr); 986 #endif 987 988 /* if TBI is not endbled */ 989 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 990 int val = mdio_read(PHY_AUTO_NEGO_REG); 991 992 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 993 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 994 if (option > 0) { 995 #ifdef DEBUG_RTL8169 996 printf("%s: Force-mode Enabled.\n", name); 997 #endif 998 Cap10_100 = 0, Cap1000 = 0; 999 switch (option) { 1000 case _10_Half: 1001 Cap10_100 = PHY_Cap_10_Half; 1002 Cap1000 = PHY_Cap_Null; 1003 break; 1004 case _10_Full: 1005 Cap10_100 = PHY_Cap_10_Full; 1006 Cap1000 = PHY_Cap_Null; 1007 break; 1008 case _100_Half: 1009 Cap10_100 = PHY_Cap_100_Half; 1010 Cap1000 = PHY_Cap_Null; 1011 break; 1012 case _100_Full: 1013 Cap10_100 = PHY_Cap_100_Full; 1014 Cap1000 = PHY_Cap_Null; 1015 break; 1016 case _1000_Full: 1017 Cap10_100 = PHY_Cap_Null; 1018 Cap1000 = PHY_Cap_1000_Full; 1019 break; 1020 default: 1021 break; 1022 } 1023 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 1024 mdio_write(PHY_1000_CTRL_REG, Cap1000); 1025 } else { 1026 #ifdef DEBUG_RTL8169 1027 printf("%s: Auto-negotiation Enabled.\n", 1028 name); 1029 #endif 1030 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 1031 mdio_write(PHY_AUTO_NEGO_REG, 1032 PHY_Cap_10_Half | PHY_Cap_10_Full | 1033 PHY_Cap_100_Half | PHY_Cap_100_Full | 1034 (val & 0x1F)); 1035 1036 /* enable 1000 Full Mode */ 1037 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 1038 1039 } 1040 1041 /* Enable auto-negotiation and restart auto-nigotiation */ 1042 mdio_write(PHY_CTRL_REG, 1043 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 1044 udelay(100); 1045 1046 /* wait for auto-negotiation process */ 1047 for (i = 10000; i > 0; i--) { 1048 /* check if auto-negotiation complete */ 1049 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 1050 udelay(100); 1051 option = RTL_R8(PHYstatus); 1052 if (option & _1000bpsF) { 1053 #ifdef DEBUG_RTL8169 1054 printf("%s: 1000Mbps Full-duplex operation.\n", 1055 name); 1056 #endif 1057 } else { 1058 #ifdef DEBUG_RTL8169 1059 printf("%s: %sMbps %s-duplex operation.\n", 1060 name, 1061 (option & _100bps) ? "100" : 1062 "10", 1063 (option & FullDup) ? "Full" : 1064 "Half"); 1065 #endif 1066 } 1067 break; 1068 } else { 1069 udelay(100); 1070 } 1071 } /* end for-loop to wait for auto-negotiation process */ 1072 1073 } else { 1074 udelay(100); 1075 #ifdef DEBUG_RTL8169 1076 printf 1077 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 1078 name, 1079 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 1080 #endif 1081 } 1082 1083 1084 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); 1085 if (!tpc->RxDescArray) 1086 return -ENOMEM; 1087 1088 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); 1089 if (!tpc->TxDescArray) 1090 return -ENOMEM; 1091 1092 return 0; 1093 } 1094 1095 #ifndef CONFIG_DM_ETH 1096 int rtl8169_initialize(bd_t *bis) 1097 { 1098 pci_dev_t devno; 1099 int card_number = 0; 1100 struct eth_device *dev; 1101 u32 iobase; 1102 int idx=0; 1103 1104 while(1){ 1105 unsigned int region; 1106 u16 device; 1107 int err; 1108 1109 /* Find RTL8169 */ 1110 if ((devno = pci_find_devices(supported, idx++)) < 0) 1111 break; 1112 1113 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 1114 switch (device) { 1115 case 0x8168: 1116 region = 2; 1117 break; 1118 1119 default: 1120 region = 1; 1121 break; 1122 } 1123 1124 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 1125 iobase &= ~0xf; 1126 1127 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1128 1129 dev = (struct eth_device *)malloc(sizeof *dev); 1130 if (!dev) { 1131 printf("Can not allocate memory of rtl8169\n"); 1132 break; 1133 } 1134 1135 memset(dev, 0, sizeof(*dev)); 1136 sprintf (dev->name, "RTL8169#%d", card_number); 1137 1138 dev->priv = (void *)(unsigned long)devno; 1139 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 1140 1141 dev->init = rtl_reset; 1142 dev->halt = rtl_halt; 1143 dev->send = rtl_send; 1144 dev->recv = rtl_recv; 1145 1146 err = rtl_init(dev->iobase, dev->name, dev->enetaddr); 1147 if (err < 0) { 1148 printf(pr_fmt("failed to initialize card: %d\n"), err); 1149 free(dev); 1150 continue; 1151 } 1152 1153 eth_register (dev); 1154 1155 card_number++; 1156 } 1157 return card_number; 1158 } 1159 #endif 1160 1161 #ifdef CONFIG_DM_ETH 1162 static int rtl8169_eth_probe(struct udevice *dev) 1163 { 1164 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 1165 struct rtl8169_private *priv = dev_get_priv(dev); 1166 struct eth_pdata *plat = dev_get_platdata(dev); 1167 u32 iobase; 1168 int region; 1169 int ret; 1170 1171 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1172 switch (pplat->device) { 1173 case 0x8168: 1174 region = 2; 1175 break; 1176 default: 1177 region = 1; 1178 break; 1179 } 1180 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase); 1181 iobase &= ~0xf; 1182 priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase); 1183 1184 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); 1185 if (ret < 0) { 1186 printf(pr_fmt("failed to initialize card: %d\n"), ret); 1187 return ret; 1188 } 1189 1190 return 0; 1191 } 1192 1193 static const struct eth_ops rtl8169_eth_ops = { 1194 .start = rtl8169_eth_start, 1195 .send = rtl8169_eth_send, 1196 .recv = rtl8169_eth_recv, 1197 .stop = rtl8169_eth_stop, 1198 }; 1199 1200 static const struct udevice_id rtl8169_eth_ids[] = { 1201 { .compatible = "realtek,rtl8169" }, 1202 { } 1203 }; 1204 1205 U_BOOT_DRIVER(eth_rtl8169) = { 1206 .name = "eth_rtl8169", 1207 .id = UCLASS_ETH, 1208 .of_match = rtl8169_eth_ids, 1209 .probe = rtl8169_eth_probe, 1210 .ops = &rtl8169_eth_ops, 1211 .priv_auto_alloc_size = sizeof(struct rtl8169_private), 1212 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1213 }; 1214 1215 U_BOOT_PCI_DEVICE(eth_rtl8169, supported); 1216 #endif 1217