1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <malloc.h> 45 #include <net.h> 46 #include <netdev.h> 47 #include <asm/io.h> 48 #include <pci.h> 49 50 #undef DEBUG_RTL8169 51 #undef DEBUG_RTL8169_TX 52 #undef DEBUG_RTL8169_RX 53 54 #define drv_version "v1.5" 55 #define drv_date "01-17-2004" 56 57 static u32 ioaddr; 58 59 /* Condensed operations for readability. */ 60 #define currticks() get_timer(0) 61 62 /* media options */ 63 #define MAX_UNITS 8 64 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 65 66 /* MAC address length*/ 67 #define MAC_ADDR_LEN 6 68 69 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 70 #define MAX_ETH_FRAME_SIZE 1536 71 72 #define TX_FIFO_THRESH 256 /* In bytes */ 73 74 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 75 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 77 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 78 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 79 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 80 81 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 82 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 83 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 84 #define RX_BUF_LEN 8192 85 86 #define RTL_MIN_IO_SIZE 0x80 87 #define TX_TIMEOUT (6*HZ) 88 89 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 90 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 91 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 92 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 93 #define RTL_R8(reg) readb (ioaddr + (reg)) 94 #define RTL_R16(reg) readw (ioaddr + (reg)) 95 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 96 97 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 98 #define ETH_ALEN MAC_ADDR_LEN 99 #define ETH_ZLEN 60 100 101 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a) 102 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a) 103 104 enum RTL8169_registers { 105 MAC0 = 0, /* Ethernet hardware address. */ 106 MAR0 = 8, /* Multicast filter. */ 107 TxDescStartAddrLow = 0x20, 108 TxDescStartAddrHigh = 0x24, 109 TxHDescStartAddrLow = 0x28, 110 TxHDescStartAddrHigh = 0x2c, 111 FLASH = 0x30, 112 ERSR = 0x36, 113 ChipCmd = 0x37, 114 TxPoll = 0x38, 115 IntrMask = 0x3C, 116 IntrStatus = 0x3E, 117 TxConfig = 0x40, 118 RxConfig = 0x44, 119 RxMissed = 0x4C, 120 Cfg9346 = 0x50, 121 Config0 = 0x51, 122 Config1 = 0x52, 123 Config2 = 0x53, 124 Config3 = 0x54, 125 Config4 = 0x55, 126 Config5 = 0x56, 127 MultiIntr = 0x5C, 128 PHYAR = 0x60, 129 TBICSR = 0x64, 130 TBI_ANAR = 0x68, 131 TBI_LPAR = 0x6A, 132 PHYstatus = 0x6C, 133 RxMaxSize = 0xDA, 134 CPlusCmd = 0xE0, 135 RxDescStartAddrLow = 0xE4, 136 RxDescStartAddrHigh = 0xE8, 137 EarlyTxThres = 0xEC, 138 FuncEvent = 0xF0, 139 FuncEventMask = 0xF4, 140 FuncPresetState = 0xF8, 141 FuncForceEvent = 0xFC, 142 }; 143 144 enum RTL8169_register_content { 145 /*InterruptStatusBits */ 146 SYSErr = 0x8000, 147 PCSTimeout = 0x4000, 148 SWInt = 0x0100, 149 TxDescUnavail = 0x80, 150 RxFIFOOver = 0x40, 151 RxUnderrun = 0x20, 152 RxOverflow = 0x10, 153 TxErr = 0x08, 154 TxOK = 0x04, 155 RxErr = 0x02, 156 RxOK = 0x01, 157 158 /*RxStatusDesc */ 159 RxRES = 0x00200000, 160 RxCRC = 0x00080000, 161 RxRUNT = 0x00100000, 162 RxRWT = 0x00400000, 163 164 /*ChipCmdBits */ 165 CmdReset = 0x10, 166 CmdRxEnb = 0x08, 167 CmdTxEnb = 0x04, 168 RxBufEmpty = 0x01, 169 170 /*Cfg9346Bits */ 171 Cfg9346_Lock = 0x00, 172 Cfg9346_Unlock = 0xC0, 173 174 /*rx_mode_bits */ 175 AcceptErr = 0x20, 176 AcceptRunt = 0x10, 177 AcceptBroadcast = 0x08, 178 AcceptMulticast = 0x04, 179 AcceptMyPhys = 0x02, 180 AcceptAllPhys = 0x01, 181 182 /*RxConfigBits */ 183 RxCfgFIFOShift = 13, 184 RxCfgDMAShift = 8, 185 186 /*TxConfigBits */ 187 TxInterFrameGapShift = 24, 188 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 189 190 /*rtl8169_PHYstatus */ 191 TBI_Enable = 0x80, 192 TxFlowCtrl = 0x40, 193 RxFlowCtrl = 0x20, 194 _1000bpsF = 0x10, 195 _100bps = 0x08, 196 _10bps = 0x04, 197 LinkStatus = 0x02, 198 FullDup = 0x01, 199 200 /*GIGABIT_PHY_registers */ 201 PHY_CTRL_REG = 0, 202 PHY_STAT_REG = 1, 203 PHY_AUTO_NEGO_REG = 4, 204 PHY_1000_CTRL_REG = 9, 205 206 /*GIGABIT_PHY_REG_BIT */ 207 PHY_Restart_Auto_Nego = 0x0200, 208 PHY_Enable_Auto_Nego = 0x1000, 209 210 /* PHY_STAT_REG = 1; */ 211 PHY_Auto_Nego_Comp = 0x0020, 212 213 /* PHY_AUTO_NEGO_REG = 4; */ 214 PHY_Cap_10_Half = 0x0020, 215 PHY_Cap_10_Full = 0x0040, 216 PHY_Cap_100_Half = 0x0080, 217 PHY_Cap_100_Full = 0x0100, 218 219 /* PHY_1000_CTRL_REG = 9; */ 220 PHY_Cap_1000_Full = 0x0200, 221 222 PHY_Cap_Null = 0x0, 223 224 /*_MediaType*/ 225 _10_Half = 0x01, 226 _10_Full = 0x02, 227 _100_Half = 0x04, 228 _100_Full = 0x08, 229 _1000_Full = 0x10, 230 231 /*_TBICSRBit*/ 232 TBILinkOK = 0x02000000, 233 }; 234 235 static struct { 236 const char *name; 237 u8 version; /* depend on RTL8169 docs */ 238 u32 RxConfigMask; /* should clear the bits supported by this chip */ 239 } rtl_chip_info[] = { 240 {"RTL-8169", 0x00, 0xff7e1880,}, 241 {"RTL-8169", 0x04, 0xff7e1880,}, 242 {"RTL-8169", 0x00, 0xff7e1880,}, 243 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 244 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 245 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 246 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 247 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 248 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 249 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 250 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 251 {"RTL-8101e", 0x34, 0xff7e1880,}, 252 {"RTL-8100e", 0x32, 0xff7e1880,}, 253 }; 254 255 enum _DescStatusBit { 256 OWNbit = 0x80000000, 257 EORbit = 0x40000000, 258 FSbit = 0x20000000, 259 LSbit = 0x10000000, 260 }; 261 262 struct TxDesc { 263 u32 status; 264 u32 vlan_tag; 265 u32 buf_addr; 266 u32 buf_Haddr; 267 }; 268 269 struct RxDesc { 270 u32 status; 271 u32 vlan_tag; 272 u32 buf_addr; 273 u32 buf_Haddr; 274 }; 275 276 /* Define the TX Descriptor */ 277 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 278 /* __attribute__ ((aligned(256))); */ 279 280 /* Create a static buffer of size RX_BUF_SZ for each 281 TX Descriptor. All descriptors point to a 282 part of this buffer */ 283 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 284 285 /* Define the RX Descriptor */ 286 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 287 /* __attribute__ ((aligned(256))); */ 288 289 /* Create a static buffer of size RX_BUF_SZ for each 290 RX Descriptor All descriptors point to a 291 part of this buffer */ 292 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 293 294 struct rtl8169_private { 295 void *mmio_addr; /* memory map physical address */ 296 int chipset; 297 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 298 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 299 unsigned long dirty_tx; 300 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 301 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 302 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 303 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 304 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 305 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 306 unsigned char *Tx_skbuff[NUM_TX_DESC]; 307 } tpx; 308 309 static struct rtl8169_private *tpc; 310 311 static const u16 rtl8169_intr_mask = 312 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 313 TxOK | RxErr | RxOK; 314 static const unsigned int rtl8169_rx_config = 315 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 316 317 static struct pci_device_id supported[] = { 318 {PCI_VENDOR_ID_REALTEK, 0x8167}, 319 {PCI_VENDOR_ID_REALTEK, 0x8168}, 320 {PCI_VENDOR_ID_REALTEK, 0x8169}, 321 {} 322 }; 323 324 void mdio_write(int RegAddr, int value) 325 { 326 int i; 327 328 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 329 udelay(1000); 330 331 for (i = 2000; i > 0; i--) { 332 /* Check if the RTL8169 has completed writing to the specified MII register */ 333 if (!(RTL_R32(PHYAR) & 0x80000000)) { 334 break; 335 } else { 336 udelay(100); 337 } 338 } 339 } 340 341 int mdio_read(int RegAddr) 342 { 343 int i, value = -1; 344 345 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 346 udelay(1000); 347 348 for (i = 2000; i > 0; i--) { 349 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 350 if (RTL_R32(PHYAR) & 0x80000000) { 351 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 352 break; 353 } else { 354 udelay(100); 355 } 356 } 357 return value; 358 } 359 360 static int rtl8169_init_board(struct eth_device *dev) 361 { 362 int i; 363 u32 tmp; 364 365 #ifdef DEBUG_RTL8169 366 printf ("%s\n", __FUNCTION__); 367 #endif 368 ioaddr = dev->iobase; 369 370 /* Soft reset the chip. */ 371 RTL_W8(ChipCmd, CmdReset); 372 373 /* Check that the chip has finished the reset. */ 374 for (i = 1000; i > 0; i--) 375 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 376 break; 377 else 378 udelay(10); 379 380 /* identify chip attached to board */ 381 tmp = RTL_R32(TxConfig); 382 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 383 384 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 385 if (tmp == rtl_chip_info[i].version) { 386 tpc->chipset = i; 387 goto match; 388 } 389 } 390 391 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 392 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 393 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 394 tpc->chipset = 0; 395 396 match: 397 return 0; 398 } 399 400 /* 401 * Cache maintenance functions. These are simple wrappers around the more 402 * general purpose flush_cache() and invalidate_dcache_range() functions. 403 */ 404 405 static void rtl_inval_rx_desc(struct RxDesc *desc) 406 { 407 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 408 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 409 410 invalidate_dcache_range(start, end); 411 } 412 413 static void rtl_flush_rx_desc(struct RxDesc *desc) 414 { 415 flush_cache((unsigned long)desc, sizeof(*desc)); 416 } 417 418 static void rtl_inval_tx_desc(struct TxDesc *desc) 419 { 420 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 421 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 422 423 invalidate_dcache_range(start, end); 424 } 425 426 static void rtl_flush_tx_desc(struct TxDesc *desc) 427 { 428 flush_cache((unsigned long)desc, sizeof(*desc)); 429 } 430 431 static void rtl_inval_buffer(void *buf, size_t size) 432 { 433 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 434 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 435 436 invalidate_dcache_range(start, end); 437 } 438 439 static void rtl_flush_buffer(void *buf, size_t size) 440 { 441 flush_cache((unsigned long)buf, size); 442 } 443 444 /************************************************************************** 445 RECV - Receive a frame 446 ***************************************************************************/ 447 static int rtl_recv(struct eth_device *dev) 448 { 449 /* return true if there's an ethernet packet ready to read */ 450 /* nic->packet should contain data on return */ 451 /* nic->packetlen should contain length of data */ 452 int cur_rx; 453 int length = 0; 454 455 #ifdef DEBUG_RTL8169_RX 456 printf ("%s\n", __FUNCTION__); 457 #endif 458 ioaddr = dev->iobase; 459 460 cur_rx = tpc->cur_rx; 461 462 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 463 464 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 465 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 466 unsigned char rxdata[RX_BUF_LEN]; 467 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 468 status) & 0x00001FFF) - 4; 469 470 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 471 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 472 NetReceive(rxdata, length); 473 474 if (cur_rx == NUM_RX_DESC - 1) 475 tpc->RxDescArray[cur_rx].status = 476 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 477 else 478 tpc->RxDescArray[cur_rx].status = 479 cpu_to_le32(OWNbit + RX_BUF_SIZE); 480 tpc->RxDescArray[cur_rx].buf_addr = 481 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx])); 482 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 483 } else { 484 puts("Error Rx"); 485 } 486 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 487 tpc->cur_rx = cur_rx; 488 return 1; 489 490 } else { 491 ushort sts = RTL_R8(IntrStatus); 492 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 493 udelay(100); /* wait */ 494 } 495 tpc->cur_rx = cur_rx; 496 return (0); /* initially as this is called to flush the input */ 497 } 498 499 #define HZ 1000 500 /************************************************************************** 501 SEND - Transmit a frame 502 ***************************************************************************/ 503 static int rtl_send(struct eth_device *dev, void *packet, int length) 504 { 505 /* send the packet to destination */ 506 507 u32 to; 508 u8 *ptxb; 509 int entry = tpc->cur_tx % NUM_TX_DESC; 510 u32 len = length; 511 int ret; 512 513 #ifdef DEBUG_RTL8169_TX 514 int stime = currticks(); 515 printf ("%s\n", __FUNCTION__); 516 printf("sending %d bytes\n", len); 517 #endif 518 519 ioaddr = dev->iobase; 520 521 /* point to the current txb incase multiple tx_rings are used */ 522 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 523 memcpy(ptxb, (char *)packet, (int)length); 524 rtl_flush_buffer(ptxb, length); 525 526 while (len < ETH_ZLEN) 527 ptxb[len++] = '\0'; 528 529 tpc->TxDescArray[entry].buf_Haddr = 0; 530 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb)); 531 if (entry != (NUM_TX_DESC - 1)) { 532 tpc->TxDescArray[entry].status = 533 cpu_to_le32((OWNbit | FSbit | LSbit) | 534 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 535 } else { 536 tpc->TxDescArray[entry].status = 537 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 538 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 539 } 540 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 541 RTL_W8(TxPoll, 0x40); /* set polling bit */ 542 543 tpc->cur_tx++; 544 to = currticks() + TX_TIMEOUT; 545 do { 546 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 547 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 548 && (currticks() < to)); /* wait */ 549 550 if (currticks() >= to) { 551 #ifdef DEBUG_RTL8169_TX 552 puts("tx timeout/error\n"); 553 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 554 #endif 555 ret = 0; 556 } else { 557 #ifdef DEBUG_RTL8169_TX 558 puts("tx done\n"); 559 #endif 560 ret = length; 561 } 562 /* Delay to make net console (nc) work properly */ 563 udelay(20); 564 return ret; 565 } 566 567 static void rtl8169_set_rx_mode(struct eth_device *dev) 568 { 569 u32 mc_filter[2]; /* Multicast hash filter */ 570 int rx_mode; 571 u32 tmp = 0; 572 573 #ifdef DEBUG_RTL8169 574 printf ("%s\n", __FUNCTION__); 575 #endif 576 577 /* IFF_ALLMULTI */ 578 /* Too many to filter perfectly -- accept all multicasts. */ 579 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 580 mc_filter[1] = mc_filter[0] = 0xffffffff; 581 582 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 583 rtl_chip_info[tpc->chipset].RxConfigMask); 584 585 RTL_W32(RxConfig, tmp); 586 RTL_W32(MAR0 + 0, mc_filter[0]); 587 RTL_W32(MAR0 + 4, mc_filter[1]); 588 } 589 590 static void rtl8169_hw_start(struct eth_device *dev) 591 { 592 u32 i; 593 594 #ifdef DEBUG_RTL8169 595 int stime = currticks(); 596 printf ("%s\n", __FUNCTION__); 597 #endif 598 599 #if 0 600 /* Soft reset the chip. */ 601 RTL_W8(ChipCmd, CmdReset); 602 603 /* Check that the chip has finished the reset. */ 604 for (i = 1000; i > 0; i--) { 605 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 606 break; 607 else 608 udelay(10); 609 } 610 #endif 611 612 RTL_W8(Cfg9346, Cfg9346_Unlock); 613 614 /* RTL-8169sb/8110sb or previous version */ 615 if (tpc->chipset <= 5) 616 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 617 618 RTL_W8(EarlyTxThres, EarlyTxThld); 619 620 /* For gigabit rtl8169 */ 621 RTL_W16(RxMaxSize, RxPacketMaxSize); 622 623 /* Set Rx Config register */ 624 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 625 rtl_chip_info[tpc->chipset].RxConfigMask); 626 RTL_W32(RxConfig, i); 627 628 /* Set DMA burst size and Interframe Gap Time */ 629 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 630 (InterFrameGap << TxInterFrameGapShift)); 631 632 633 tpc->cur_rx = 0; 634 635 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray)); 636 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 637 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray)); 638 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 639 640 /* RTL-8169sc/8110sc or later version */ 641 if (tpc->chipset > 5) 642 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 643 644 RTL_W8(Cfg9346, Cfg9346_Lock); 645 udelay(10); 646 647 RTL_W32(RxMissed, 0); 648 649 rtl8169_set_rx_mode(dev); 650 651 /* no early-rx interrupts */ 652 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 653 654 #ifdef DEBUG_RTL8169 655 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 656 #endif 657 } 658 659 static void rtl8169_init_ring(struct eth_device *dev) 660 { 661 int i; 662 663 #ifdef DEBUG_RTL8169 664 int stime = currticks(); 665 printf ("%s\n", __FUNCTION__); 666 #endif 667 668 tpc->cur_rx = 0; 669 tpc->cur_tx = 0; 670 tpc->dirty_tx = 0; 671 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 672 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 673 674 for (i = 0; i < NUM_TX_DESC; i++) { 675 tpc->Tx_skbuff[i] = &txb[i]; 676 } 677 678 for (i = 0; i < NUM_RX_DESC; i++) { 679 if (i == (NUM_RX_DESC - 1)) 680 tpc->RxDescArray[i].status = 681 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 682 else 683 tpc->RxDescArray[i].status = 684 cpu_to_le32(OWNbit + RX_BUF_SIZE); 685 686 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 687 tpc->RxDescArray[i].buf_addr = 688 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i])); 689 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 690 } 691 692 #ifdef DEBUG_RTL8169 693 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 694 #endif 695 } 696 697 /************************************************************************** 698 RESET - Finish setting up the ethernet interface 699 ***************************************************************************/ 700 static int rtl_reset(struct eth_device *dev, bd_t *bis) 701 { 702 int i; 703 704 #ifdef DEBUG_RTL8169 705 int stime = currticks(); 706 printf ("%s\n", __FUNCTION__); 707 #endif 708 709 tpc->TxDescArrays = tx_ring; 710 /* Tx Desscriptor needs 256 bytes alignment; */ 711 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 712 255) & ~255); 713 714 tpc->RxDescArrays = rx_ring; 715 /* Rx Desscriptor needs 256 bytes alignment; */ 716 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 717 255) & ~255); 718 719 rtl8169_init_ring(dev); 720 rtl8169_hw_start(dev); 721 /* Construct a perfect filter frame with the mac address as first match 722 * and broadcast for all others */ 723 for (i = 0; i < 192; i++) 724 txb[i] = 0xFF; 725 726 txb[0] = dev->enetaddr[0]; 727 txb[1] = dev->enetaddr[1]; 728 txb[2] = dev->enetaddr[2]; 729 txb[3] = dev->enetaddr[3]; 730 txb[4] = dev->enetaddr[4]; 731 txb[5] = dev->enetaddr[5]; 732 733 #ifdef DEBUG_RTL8169 734 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 735 #endif 736 return 0; 737 } 738 739 /************************************************************************** 740 HALT - Turn off ethernet interface 741 ***************************************************************************/ 742 static void rtl_halt(struct eth_device *dev) 743 { 744 int i; 745 746 #ifdef DEBUG_RTL8169 747 printf ("%s\n", __FUNCTION__); 748 #endif 749 750 ioaddr = dev->iobase; 751 752 /* Stop the chip's Tx and Rx DMA processes. */ 753 RTL_W8(ChipCmd, 0x00); 754 755 /* Disable interrupts by clearing the interrupt mask. */ 756 RTL_W16(IntrMask, 0x0000); 757 758 RTL_W32(RxMissed, 0); 759 760 tpc->TxDescArrays = NULL; 761 tpc->RxDescArrays = NULL; 762 tpc->TxDescArray = NULL; 763 tpc->RxDescArray = NULL; 764 for (i = 0; i < NUM_RX_DESC; i++) { 765 tpc->RxBufferRing[i] = NULL; 766 } 767 } 768 769 /************************************************************************** 770 INIT - Look for an adapter, this routine's visible to the outside 771 ***************************************************************************/ 772 773 #define board_found 1 774 #define valid_link 0 775 static int rtl_init(struct eth_device *dev, bd_t *bis) 776 { 777 static int board_idx = -1; 778 int i, rc; 779 int option = -1, Cap10_100 = 0, Cap1000 = 0; 780 781 #ifdef DEBUG_RTL8169 782 printf ("%s\n", __FUNCTION__); 783 #endif 784 785 ioaddr = dev->iobase; 786 787 board_idx++; 788 789 /* point to private storage */ 790 tpc = &tpx; 791 792 rc = rtl8169_init_board(dev); 793 if (rc) 794 return rc; 795 796 /* Get MAC address. FIXME: read EEPROM */ 797 for (i = 0; i < MAC_ADDR_LEN; i++) 798 dev->enetaddr[i] = RTL_R8(MAC0 + i); 799 800 #ifdef DEBUG_RTL8169 801 printf("chipset = %d\n", tpc->chipset); 802 printf("MAC Address"); 803 for (i = 0; i < MAC_ADDR_LEN; i++) 804 printf(":%02x", dev->enetaddr[i]); 805 putc('\n'); 806 #endif 807 808 #ifdef DEBUG_RTL8169 809 /* Print out some hardware info */ 810 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 811 #endif 812 813 /* if TBI is not endbled */ 814 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 815 int val = mdio_read(PHY_AUTO_NEGO_REG); 816 817 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 818 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 819 if (option > 0) { 820 #ifdef DEBUG_RTL8169 821 printf("%s: Force-mode Enabled.\n", dev->name); 822 #endif 823 Cap10_100 = 0, Cap1000 = 0; 824 switch (option) { 825 case _10_Half: 826 Cap10_100 = PHY_Cap_10_Half; 827 Cap1000 = PHY_Cap_Null; 828 break; 829 case _10_Full: 830 Cap10_100 = PHY_Cap_10_Full; 831 Cap1000 = PHY_Cap_Null; 832 break; 833 case _100_Half: 834 Cap10_100 = PHY_Cap_100_Half; 835 Cap1000 = PHY_Cap_Null; 836 break; 837 case _100_Full: 838 Cap10_100 = PHY_Cap_100_Full; 839 Cap1000 = PHY_Cap_Null; 840 break; 841 case _1000_Full: 842 Cap10_100 = PHY_Cap_Null; 843 Cap1000 = PHY_Cap_1000_Full; 844 break; 845 default: 846 break; 847 } 848 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 849 mdio_write(PHY_1000_CTRL_REG, Cap1000); 850 } else { 851 #ifdef DEBUG_RTL8169 852 printf("%s: Auto-negotiation Enabled.\n", 853 dev->name); 854 #endif 855 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 856 mdio_write(PHY_AUTO_NEGO_REG, 857 PHY_Cap_10_Half | PHY_Cap_10_Full | 858 PHY_Cap_100_Half | PHY_Cap_100_Full | 859 (val & 0x1F)); 860 861 /* enable 1000 Full Mode */ 862 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 863 864 } 865 866 /* Enable auto-negotiation and restart auto-nigotiation */ 867 mdio_write(PHY_CTRL_REG, 868 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 869 udelay(100); 870 871 /* wait for auto-negotiation process */ 872 for (i = 10000; i > 0; i--) { 873 /* check if auto-negotiation complete */ 874 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 875 udelay(100); 876 option = RTL_R8(PHYstatus); 877 if (option & _1000bpsF) { 878 #ifdef DEBUG_RTL8169 879 printf("%s: 1000Mbps Full-duplex operation.\n", 880 dev->name); 881 #endif 882 } else { 883 #ifdef DEBUG_RTL8169 884 printf("%s: %sMbps %s-duplex operation.\n", 885 dev->name, 886 (option & _100bps) ? "100" : 887 "10", 888 (option & FullDup) ? "Full" : 889 "Half"); 890 #endif 891 } 892 break; 893 } else { 894 udelay(100); 895 } 896 } /* end for-loop to wait for auto-negotiation process */ 897 898 } else { 899 udelay(100); 900 #ifdef DEBUG_RTL8169 901 printf 902 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 903 dev->name, 904 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 905 #endif 906 } 907 908 return 1; 909 } 910 911 int rtl8169_initialize(bd_t *bis) 912 { 913 pci_dev_t devno; 914 int card_number = 0; 915 struct eth_device *dev; 916 u32 iobase; 917 int idx=0; 918 919 while(1){ 920 unsigned int region; 921 u16 device; 922 923 /* Find RTL8169 */ 924 if ((devno = pci_find_devices(supported, idx++)) < 0) 925 break; 926 927 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 928 switch (device) { 929 case 0x8168: 930 region = 2; 931 break; 932 933 default: 934 region = 1; 935 break; 936 } 937 938 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 939 iobase &= ~0xf; 940 941 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 942 943 dev = (struct eth_device *)malloc(sizeof *dev); 944 if (!dev) { 945 printf("Can not allocate memory of rtl8169\n"); 946 break; 947 } 948 949 memset(dev, 0, sizeof(*dev)); 950 sprintf (dev->name, "RTL8169#%d", card_number); 951 952 dev->priv = (void *) devno; 953 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 954 955 dev->init = rtl_reset; 956 dev->halt = rtl_halt; 957 dev->send = rtl_send; 958 dev->recv = rtl_recv; 959 960 eth_register (dev); 961 962 rtl_init(dev, bis); 963 964 card_number++; 965 } 966 return card_number; 967 } 968