1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 28 * Portions of this code based on: 29 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 30 * for Linux kernel 2.4.x. 31 * 32 * Written 2002 ShuChen <shuchen@realtek.com.tw> 33 * See Linux Driver for full information 34 * 35 * Linux Driver Version 1.27a, 10.02.2002 36 * 37 * Thanks to: 38 * Jean Chen of RealTek Semiconductor Corp. for 39 * providing the evaluation NIC used to develop 40 * this driver. RealTek's support for Etherboot 41 * is appreciated. 42 * 43 * REVISION HISTORY: 44 * ================ 45 * 46 * v1.0 11-26-2003 timlegge Initial port of Linux driver 47 * v1.5 01-17-2004 timlegge Initial driver output cleanup 48 * 49 * Indent Options: indent -kr -i8 50 ***************************************************************************/ 51 /* 52 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 53 * Modified to use le32_to_cpu and cpu_to_le32 properly 54 */ 55 #include <common.h> 56 #include <malloc.h> 57 #include <net.h> 58 #include <asm/io.h> 59 #include <pci.h> 60 61 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ 62 defined(CONFIG_RTL8169) 63 64 #undef DEBUG_RTL8169 65 #undef DEBUG_RTL8169_TX 66 #undef DEBUG_RTL8169_RX 67 68 #define drv_version "v1.5" 69 #define drv_date "01-17-2004" 70 71 static u32 ioaddr; 72 73 /* Condensed operations for readability. */ 74 #define currticks() get_timer(0) 75 76 /* media options */ 77 #define MAX_UNITS 8 78 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 79 80 /* MAC address length*/ 81 #define MAC_ADDR_LEN 6 82 83 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 84 #define MAX_ETH_FRAME_SIZE 1536 85 86 #define TX_FIFO_THRESH 256 /* In bytes */ 87 88 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 89 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 90 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 91 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 92 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 93 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 94 95 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 96 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 97 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 98 #define RX_BUF_LEN 8192 99 100 #define RTL_MIN_IO_SIZE 0x80 101 #define TX_TIMEOUT (6*HZ) 102 103 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 104 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 105 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 106 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 107 #define RTL_R8(reg) readb (ioaddr + (reg)) 108 #define RTL_R16(reg) readw (ioaddr + (reg)) 109 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 110 111 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 112 #define ETH_ALEN MAC_ADDR_LEN 113 #define ETH_ZLEN 60 114 115 enum RTL8169_registers { 116 MAC0 = 0, /* Ethernet hardware address. */ 117 MAR0 = 8, /* Multicast filter. */ 118 TxDescStartAddr = 0x20, 119 TxHDescStartAddr = 0x28, 120 FLASH = 0x30, 121 ERSR = 0x36, 122 ChipCmd = 0x37, 123 TxPoll = 0x38, 124 IntrMask = 0x3C, 125 IntrStatus = 0x3E, 126 TxConfig = 0x40, 127 RxConfig = 0x44, 128 RxMissed = 0x4C, 129 Cfg9346 = 0x50, 130 Config0 = 0x51, 131 Config1 = 0x52, 132 Config2 = 0x53, 133 Config3 = 0x54, 134 Config4 = 0x55, 135 Config5 = 0x56, 136 MultiIntr = 0x5C, 137 PHYAR = 0x60, 138 TBICSR = 0x64, 139 TBI_ANAR = 0x68, 140 TBI_LPAR = 0x6A, 141 PHYstatus = 0x6C, 142 RxMaxSize = 0xDA, 143 CPlusCmd = 0xE0, 144 RxDescStartAddr = 0xE4, 145 EarlyTxThres = 0xEC, 146 FuncEvent = 0xF0, 147 FuncEventMask = 0xF4, 148 FuncPresetState = 0xF8, 149 FuncForceEvent = 0xFC, 150 }; 151 152 enum RTL8169_register_content { 153 /*InterruptStatusBits */ 154 SYSErr = 0x8000, 155 PCSTimeout = 0x4000, 156 SWInt = 0x0100, 157 TxDescUnavail = 0x80, 158 RxFIFOOver = 0x40, 159 RxUnderrun = 0x20, 160 RxOverflow = 0x10, 161 TxErr = 0x08, 162 TxOK = 0x04, 163 RxErr = 0x02, 164 RxOK = 0x01, 165 166 /*RxStatusDesc */ 167 RxRES = 0x00200000, 168 RxCRC = 0x00080000, 169 RxRUNT = 0x00100000, 170 RxRWT = 0x00400000, 171 172 /*ChipCmdBits */ 173 CmdReset = 0x10, 174 CmdRxEnb = 0x08, 175 CmdTxEnb = 0x04, 176 RxBufEmpty = 0x01, 177 178 /*Cfg9346Bits */ 179 Cfg9346_Lock = 0x00, 180 Cfg9346_Unlock = 0xC0, 181 182 /*rx_mode_bits */ 183 AcceptErr = 0x20, 184 AcceptRunt = 0x10, 185 AcceptBroadcast = 0x08, 186 AcceptMulticast = 0x04, 187 AcceptMyPhys = 0x02, 188 AcceptAllPhys = 0x01, 189 190 /*RxConfigBits */ 191 RxCfgFIFOShift = 13, 192 RxCfgDMAShift = 8, 193 194 /*TxConfigBits */ 195 TxInterFrameGapShift = 24, 196 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 197 198 /*rtl8169_PHYstatus */ 199 TBI_Enable = 0x80, 200 TxFlowCtrl = 0x40, 201 RxFlowCtrl = 0x20, 202 _1000bpsF = 0x10, 203 _100bps = 0x08, 204 _10bps = 0x04, 205 LinkStatus = 0x02, 206 FullDup = 0x01, 207 208 /*GIGABIT_PHY_registers */ 209 PHY_CTRL_REG = 0, 210 PHY_STAT_REG = 1, 211 PHY_AUTO_NEGO_REG = 4, 212 PHY_1000_CTRL_REG = 9, 213 214 /*GIGABIT_PHY_REG_BIT */ 215 PHY_Restart_Auto_Nego = 0x0200, 216 PHY_Enable_Auto_Nego = 0x1000, 217 218 /* PHY_STAT_REG = 1; */ 219 PHY_Auto_Nego_Comp = 0x0020, 220 221 /* PHY_AUTO_NEGO_REG = 4; */ 222 PHY_Cap_10_Half = 0x0020, 223 PHY_Cap_10_Full = 0x0040, 224 PHY_Cap_100_Half = 0x0080, 225 PHY_Cap_100_Full = 0x0100, 226 227 /* PHY_1000_CTRL_REG = 9; */ 228 PHY_Cap_1000_Full = 0x0200, 229 230 PHY_Cap_Null = 0x0, 231 232 /*_MediaType*/ 233 _10_Half = 0x01, 234 _10_Full = 0x02, 235 _100_Half = 0x04, 236 _100_Full = 0x08, 237 _1000_Full = 0x10, 238 239 /*_TBICSRBit*/ 240 TBILinkOK = 0x02000000, 241 }; 242 243 static struct { 244 const char *name; 245 u8 version; /* depend on RTL8169 docs */ 246 u32 RxConfigMask; /* should clear the bits supported by this chip */ 247 } rtl_chip_info[] = { 248 {"RTL-8169", 0x00, 0xff7e1880,}, 249 {"RTL-8169", 0x04, 0xff7e1880,}, 250 {"RTL-8169", 0x00, 0xff7e1880,}, 251 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 252 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 253 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 254 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 255 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 256 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 257 {"RTL-8101e", 0x34, 0xff7e1880,}, 258 {"RTL-8100e", 0x32, 0xff7e1880,}, 259 }; 260 261 enum _DescStatusBit { 262 OWNbit = 0x80000000, 263 EORbit = 0x40000000, 264 FSbit = 0x20000000, 265 LSbit = 0x10000000, 266 }; 267 268 struct TxDesc { 269 u32 status; 270 u32 vlan_tag; 271 u32 buf_addr; 272 u32 buf_Haddr; 273 }; 274 275 struct RxDesc { 276 u32 status; 277 u32 vlan_tag; 278 u32 buf_addr; 279 u32 buf_Haddr; 280 }; 281 282 /* Define the TX Descriptor */ 283 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 284 /* __attribute__ ((aligned(256))); */ 285 286 /* Create a static buffer of size RX_BUF_SZ for each 287 TX Descriptor. All descriptors point to a 288 part of this buffer */ 289 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 290 291 /* Define the RX Descriptor */ 292 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 293 /* __attribute__ ((aligned(256))); */ 294 295 /* Create a static buffer of size RX_BUF_SZ for each 296 RX Descriptor All descriptors point to a 297 part of this buffer */ 298 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 299 300 struct rtl8169_private { 301 void *mmio_addr; /* memory map physical address */ 302 int chipset; 303 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 304 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 305 unsigned long dirty_tx; 306 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 307 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 308 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 309 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 310 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 311 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 312 unsigned char *Tx_skbuff[NUM_TX_DESC]; 313 } tpx; 314 315 static struct rtl8169_private *tpc; 316 317 static const u16 rtl8169_intr_mask = 318 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 319 TxOK | RxErr | RxOK; 320 static const unsigned int rtl8169_rx_config = 321 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 322 323 static struct pci_device_id supported[] = { 324 {PCI_VENDOR_ID_REALTEK, 0x8167}, 325 {PCI_VENDOR_ID_REALTEK, 0x8169}, 326 {} 327 }; 328 329 void mdio_write(int RegAddr, int value) 330 { 331 int i; 332 333 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 334 udelay(1000); 335 336 for (i = 2000; i > 0; i--) { 337 /* Check if the RTL8169 has completed writing to the specified MII register */ 338 if (!(RTL_R32(PHYAR) & 0x80000000)) { 339 break; 340 } else { 341 udelay(100); 342 } 343 } 344 } 345 346 int mdio_read(int RegAddr) 347 { 348 int i, value = -1; 349 350 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 351 udelay(1000); 352 353 for (i = 2000; i > 0; i--) { 354 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 355 if (RTL_R32(PHYAR) & 0x80000000) { 356 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 357 break; 358 } else { 359 udelay(100); 360 } 361 } 362 return value; 363 } 364 365 static int rtl8169_init_board(struct eth_device *dev) 366 { 367 int i; 368 u32 tmp; 369 370 #ifdef DEBUG_RTL8169 371 printf ("%s\n", __FUNCTION__); 372 #endif 373 ioaddr = dev->iobase; 374 375 /* Soft reset the chip. */ 376 RTL_W8(ChipCmd, CmdReset); 377 378 /* Check that the chip has finished the reset. */ 379 for (i = 1000; i > 0; i--) 380 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 381 break; 382 else 383 udelay(10); 384 385 /* identify chip attached to board */ 386 tmp = RTL_R32(TxConfig); 387 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 388 389 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 390 if (tmp == rtl_chip_info[i].version) { 391 tpc->chipset = i; 392 goto match; 393 } 394 } 395 396 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 397 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 398 printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); 399 tpc->chipset = 0; 400 401 match: 402 return 0; 403 } 404 405 /************************************************************************** 406 RECV - Receive a frame 407 ***************************************************************************/ 408 static int rtl_recv(struct eth_device *dev) 409 { 410 /* return true if there's an ethernet packet ready to read */ 411 /* nic->packet should contain data on return */ 412 /* nic->packetlen should contain length of data */ 413 int cur_rx; 414 int length = 0; 415 416 #ifdef DEBUG_RTL8169_RX 417 printf ("%s\n", __FUNCTION__); 418 #endif 419 ioaddr = dev->iobase; 420 421 cur_rx = tpc->cur_rx; 422 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 423 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 424 unsigned char rxdata[RX_BUF_LEN]; 425 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 426 status) & 0x00001FFF) - 4; 427 428 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 429 NetReceive(rxdata, length); 430 431 if (cur_rx == NUM_RX_DESC - 1) 432 tpc->RxDescArray[cur_rx].status = 433 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 434 else 435 tpc->RxDescArray[cur_rx].status = 436 cpu_to_le32(OWNbit + RX_BUF_SIZE); 437 tpc->RxDescArray[cur_rx].buf_addr = 438 cpu_to_le32((unsigned long)tpc->RxBufferRing[cur_rx]); 439 } else { 440 puts("Error Rx"); 441 } 442 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 443 tpc->cur_rx = cur_rx; 444 return 1; 445 446 } else { 447 ushort sts = RTL_R8(IntrStatus); 448 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 449 udelay(100); /* wait */ 450 } 451 tpc->cur_rx = cur_rx; 452 return (0); /* initially as this is called to flush the input */ 453 } 454 455 #define HZ 1000 456 /************************************************************************** 457 SEND - Transmit a frame 458 ***************************************************************************/ 459 static int rtl_send(struct eth_device *dev, volatile void *packet, int length) 460 { 461 /* send the packet to destination */ 462 463 u32 to; 464 u8 *ptxb; 465 int entry = tpc->cur_tx % NUM_TX_DESC; 466 u32 len = length; 467 int ret; 468 469 #ifdef DEBUG_RTL8169_TX 470 int stime = currticks(); 471 printf ("%s\n", __FUNCTION__); 472 printf("sending %d bytes\n", len); 473 #endif 474 475 ioaddr = dev->iobase; 476 477 /* point to the current txb incase multiple tx_rings are used */ 478 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 479 memcpy(ptxb, (char *)packet, (int)length); 480 481 while (len < ETH_ZLEN) 482 ptxb[len++] = '\0'; 483 484 tpc->TxDescArray[entry].buf_addr = cpu_to_le32((unsigned long)ptxb); 485 if (entry != (NUM_TX_DESC - 1)) { 486 tpc->TxDescArray[entry].status = 487 cpu_to_le32((OWNbit | FSbit | LSbit) | 488 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 489 } else { 490 tpc->TxDescArray[entry].status = 491 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 492 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 493 } 494 RTL_W8(TxPoll, 0x40); /* set polling bit */ 495 496 tpc->cur_tx++; 497 to = currticks() + TX_TIMEOUT; 498 while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 499 && (currticks() < to)); /* wait */ 500 501 if (currticks() >= to) { 502 #ifdef DEBUG_RTL8169_TX 503 puts ("tx timeout/error\n"); 504 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 505 #endif 506 ret = 0; 507 } else { 508 #ifdef DEBUG_RTL8169_TX 509 puts("tx done\n"); 510 #endif 511 ret = length; 512 } 513 /* Delay to make net console (nc) work properly */ 514 udelay(20); 515 return ret; 516 } 517 518 static void rtl8169_set_rx_mode(struct eth_device *dev) 519 { 520 u32 mc_filter[2]; /* Multicast hash filter */ 521 int rx_mode; 522 u32 tmp = 0; 523 524 #ifdef DEBUG_RTL8169 525 printf ("%s\n", __FUNCTION__); 526 #endif 527 528 /* IFF_ALLMULTI */ 529 /* Too many to filter perfectly -- accept all multicasts. */ 530 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 531 mc_filter[1] = mc_filter[0] = 0xffffffff; 532 533 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 534 rtl_chip_info[tpc->chipset].RxConfigMask); 535 536 RTL_W32(RxConfig, tmp); 537 RTL_W32(MAR0 + 0, mc_filter[0]); 538 RTL_W32(MAR0 + 4, mc_filter[1]); 539 } 540 541 static void rtl8169_hw_start(struct eth_device *dev) 542 { 543 u32 i; 544 545 #ifdef DEBUG_RTL8169 546 int stime = currticks(); 547 printf ("%s\n", __FUNCTION__); 548 #endif 549 550 #if 0 551 /* Soft reset the chip. */ 552 RTL_W8(ChipCmd, CmdReset); 553 554 /* Check that the chip has finished the reset. */ 555 for (i = 1000; i > 0; i--) { 556 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 557 break; 558 else 559 udelay(10); 560 } 561 #endif 562 563 RTL_W8(Cfg9346, Cfg9346_Unlock); 564 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 565 RTL_W8(EarlyTxThres, EarlyTxThld); 566 567 /* For gigabit rtl8169 */ 568 RTL_W16(RxMaxSize, RxPacketMaxSize); 569 570 /* Set Rx Config register */ 571 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 572 rtl_chip_info[tpc->chipset].RxConfigMask); 573 RTL_W32(RxConfig, i); 574 575 /* Set DMA burst size and Interframe Gap Time */ 576 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 577 (InterFrameGap << TxInterFrameGapShift)); 578 579 580 tpc->cur_rx = 0; 581 582 RTL_W32(TxDescStartAddr, (unsigned long)tpc->TxDescArray); 583 RTL_W32(RxDescStartAddr, (unsigned long)tpc->RxDescArray); 584 RTL_W8(Cfg9346, Cfg9346_Lock); 585 udelay(10); 586 587 RTL_W32(RxMissed, 0); 588 589 rtl8169_set_rx_mode(dev); 590 591 /* no early-rx interrupts */ 592 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 593 594 #ifdef DEBUG_RTL8169 595 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 596 #endif 597 } 598 599 static void rtl8169_init_ring(struct eth_device *dev) 600 { 601 int i; 602 603 #ifdef DEBUG_RTL8169 604 int stime = currticks(); 605 printf ("%s\n", __FUNCTION__); 606 #endif 607 608 tpc->cur_rx = 0; 609 tpc->cur_tx = 0; 610 tpc->dirty_tx = 0; 611 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 612 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 613 614 for (i = 0; i < NUM_TX_DESC; i++) { 615 tpc->Tx_skbuff[i] = &txb[i]; 616 } 617 618 for (i = 0; i < NUM_RX_DESC; i++) { 619 if (i == (NUM_RX_DESC - 1)) 620 tpc->RxDescArray[i].status = 621 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 622 else 623 tpc->RxDescArray[i].status = 624 cpu_to_le32(OWNbit + RX_BUF_SIZE); 625 626 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 627 tpc->RxDescArray[i].buf_addr = 628 cpu_to_le32((unsigned long)tpc->RxBufferRing[i]); 629 } 630 631 #ifdef DEBUG_RTL8169 632 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 633 #endif 634 } 635 636 /************************************************************************** 637 RESET - Finish setting up the ethernet interface 638 ***************************************************************************/ 639 static int rtl_reset(struct eth_device *dev, bd_t *bis) 640 { 641 int i; 642 643 #ifdef DEBUG_RTL8169 644 int stime = currticks(); 645 printf ("%s\n", __FUNCTION__); 646 #endif 647 648 tpc->TxDescArrays = tx_ring; 649 /* Tx Desscriptor needs 256 bytes alignment; */ 650 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 651 255) & ~255); 652 653 tpc->RxDescArrays = rx_ring; 654 /* Rx Desscriptor needs 256 bytes alignment; */ 655 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 656 255) & ~255); 657 658 rtl8169_init_ring(dev); 659 rtl8169_hw_start(dev); 660 /* Construct a perfect filter frame with the mac address as first match 661 * and broadcast for all others */ 662 for (i = 0; i < 192; i++) 663 txb[i] = 0xFF; 664 665 txb[0] = dev->enetaddr[0]; 666 txb[1] = dev->enetaddr[1]; 667 txb[2] = dev->enetaddr[2]; 668 txb[3] = dev->enetaddr[3]; 669 txb[4] = dev->enetaddr[4]; 670 txb[5] = dev->enetaddr[5]; 671 672 #ifdef DEBUG_RTL8169 673 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 674 #endif 675 return 0; 676 } 677 678 /************************************************************************** 679 HALT - Turn off ethernet interface 680 ***************************************************************************/ 681 static void rtl_halt(struct eth_device *dev) 682 { 683 int i; 684 685 #ifdef DEBUG_RTL8169 686 printf ("%s\n", __FUNCTION__); 687 #endif 688 689 ioaddr = dev->iobase; 690 691 /* Stop the chip's Tx and Rx DMA processes. */ 692 RTL_W8(ChipCmd, 0x00); 693 694 /* Disable interrupts by clearing the interrupt mask. */ 695 RTL_W16(IntrMask, 0x0000); 696 697 RTL_W32(RxMissed, 0); 698 699 tpc->TxDescArrays = NULL; 700 tpc->RxDescArrays = NULL; 701 tpc->TxDescArray = NULL; 702 tpc->RxDescArray = NULL; 703 for (i = 0; i < NUM_RX_DESC; i++) { 704 tpc->RxBufferRing[i] = NULL; 705 } 706 } 707 708 /************************************************************************** 709 INIT - Look for an adapter, this routine's visible to the outside 710 ***************************************************************************/ 711 712 #define board_found 1 713 #define valid_link 0 714 static int rtl_init(struct eth_device *dev, bd_t *bis) 715 { 716 static int board_idx = -1; 717 static int printed_version = 0; 718 int i, rc; 719 int option = -1, Cap10_100 = 0, Cap1000 = 0; 720 721 #ifdef DEBUG_RTL8169 722 printf ("%s\n", __FUNCTION__); 723 #endif 724 725 ioaddr = dev->iobase; 726 727 board_idx++; 728 729 printed_version = 1; 730 731 /* point to private storage */ 732 tpc = &tpx; 733 734 rc = rtl8169_init_board(dev); 735 if (rc) 736 return rc; 737 738 /* Get MAC address. FIXME: read EEPROM */ 739 for (i = 0; i < MAC_ADDR_LEN; i++) 740 bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); 741 742 #ifdef DEBUG_RTL8169 743 printf("MAC Address"); 744 for (i = 0; i < MAC_ADDR_LEN; i++) 745 printf(":%02x", dev->enetaddr[i]); 746 putc('\n'); 747 #endif 748 749 #ifdef DEBUG_RTL8169 750 /* Print out some hardware info */ 751 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 752 #endif 753 754 /* if TBI is not endbled */ 755 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 756 int val = mdio_read(PHY_AUTO_NEGO_REG); 757 758 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 759 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 760 if (option > 0) { 761 #ifdef DEBUG_RTL8169 762 printf("%s: Force-mode Enabled.\n", dev->name); 763 #endif 764 Cap10_100 = 0, Cap1000 = 0; 765 switch (option) { 766 case _10_Half: 767 Cap10_100 = PHY_Cap_10_Half; 768 Cap1000 = PHY_Cap_Null; 769 break; 770 case _10_Full: 771 Cap10_100 = PHY_Cap_10_Full; 772 Cap1000 = PHY_Cap_Null; 773 break; 774 case _100_Half: 775 Cap10_100 = PHY_Cap_100_Half; 776 Cap1000 = PHY_Cap_Null; 777 break; 778 case _100_Full: 779 Cap10_100 = PHY_Cap_100_Full; 780 Cap1000 = PHY_Cap_Null; 781 break; 782 case _1000_Full: 783 Cap10_100 = PHY_Cap_Null; 784 Cap1000 = PHY_Cap_1000_Full; 785 break; 786 default: 787 break; 788 } 789 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 790 mdio_write(PHY_1000_CTRL_REG, Cap1000); 791 } else { 792 #ifdef DEBUG_RTL8169 793 printf("%s: Auto-negotiation Enabled.\n", 794 dev->name); 795 #endif 796 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 797 mdio_write(PHY_AUTO_NEGO_REG, 798 PHY_Cap_10_Half | PHY_Cap_10_Full | 799 PHY_Cap_100_Half | PHY_Cap_100_Full | 800 (val & 0x1F)); 801 802 /* enable 1000 Full Mode */ 803 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 804 805 } 806 807 /* Enable auto-negotiation and restart auto-nigotiation */ 808 mdio_write(PHY_CTRL_REG, 809 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 810 udelay(100); 811 812 /* wait for auto-negotiation process */ 813 for (i = 10000; i > 0; i--) { 814 /* check if auto-negotiation complete */ 815 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 816 udelay(100); 817 option = RTL_R8(PHYstatus); 818 if (option & _1000bpsF) { 819 #ifdef DEBUG_RTL8169 820 printf("%s: 1000Mbps Full-duplex operation.\n", 821 dev->name); 822 #endif 823 } else { 824 #ifdef DEBUG_RTL8169 825 printf("%s: %sMbps %s-duplex operation.\n", 826 dev->name, 827 (option & _100bps) ? "100" : 828 "10", 829 (option & FullDup) ? "Full" : 830 "Half"); 831 #endif 832 } 833 break; 834 } else { 835 udelay(100); 836 } 837 } /* end for-loop to wait for auto-negotiation process */ 838 839 } else { 840 udelay(100); 841 #ifdef DEBUG_RTL8169 842 printf 843 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 844 dev->name, 845 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 846 #endif 847 } 848 849 return 1; 850 } 851 852 int rtl8169_initialize(bd_t *bis) 853 { 854 pci_dev_t devno; 855 int card_number = 0; 856 struct eth_device *dev; 857 u32 iobase; 858 int idx=0; 859 860 while(1){ 861 /* Find RTL8169 */ 862 if ((devno = pci_find_devices(supported, idx++)) < 0) 863 break; 864 865 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 866 iobase &= ~0xf; 867 868 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 869 870 dev = (struct eth_device *)malloc(sizeof *dev); 871 872 sprintf (dev->name, "RTL8169#%d", card_number); 873 874 dev->priv = (void *) devno; 875 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 876 877 dev->init = rtl_reset; 878 dev->halt = rtl_halt; 879 dev->send = rtl_send; 880 dev->recv = rtl_recv; 881 882 eth_register (dev); 883 884 rtl_init(dev, bis); 885 886 card_number++; 887 } 888 return card_number; 889 } 890 891 #endif 892