1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 28 * Portions of this code based on: 29 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 30 * for Linux kernel 2.4.x. 31 * 32 * Written 2002 ShuChen <shuchen@realtek.com.tw> 33 * See Linux Driver for full information 34 * 35 * Linux Driver Version 1.27a, 10.02.2002 36 * 37 * Thanks to: 38 * Jean Chen of RealTek Semiconductor Corp. for 39 * providing the evaluation NIC used to develop 40 * this driver. RealTek's support for Etherboot 41 * is appreciated. 42 * 43 * REVISION HISTORY: 44 * ================ 45 * 46 * v1.0 11-26-2003 timlegge Initial port of Linux driver 47 * v1.5 01-17-2004 timlegge Initial driver output cleanup 48 * 49 * Indent Options: indent -kr -i8 50 ***************************************************************************/ 51 /* 52 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 53 * Modified to use le32_to_cpu and cpu_to_le32 properly 54 */ 55 #include <common.h> 56 #include <malloc.h> 57 #include <net.h> 58 #include <asm/io.h> 59 #include <pci.h> 60 61 #undef DEBUG_RTL8169 62 #undef DEBUG_RTL8169_TX 63 #undef DEBUG_RTL8169_RX 64 65 #define drv_version "v1.5" 66 #define drv_date "01-17-2004" 67 68 static u32 ioaddr; 69 70 /* Condensed operations for readability. */ 71 #define currticks() get_timer(0) 72 73 /* media options */ 74 #define MAX_UNITS 8 75 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 76 77 /* MAC address length*/ 78 #define MAC_ADDR_LEN 6 79 80 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 81 #define MAX_ETH_FRAME_SIZE 1536 82 83 #define TX_FIFO_THRESH 256 /* In bytes */ 84 85 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 86 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 87 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 88 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 89 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 90 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 91 92 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 93 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 94 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 95 #define RX_BUF_LEN 8192 96 97 #define RTL_MIN_IO_SIZE 0x80 98 #define TX_TIMEOUT (6*HZ) 99 100 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 101 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 102 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 103 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 104 #define RTL_R8(reg) readb (ioaddr + (reg)) 105 #define RTL_R16(reg) readw (ioaddr + (reg)) 106 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 107 108 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 109 #define ETH_ALEN MAC_ADDR_LEN 110 #define ETH_ZLEN 60 111 112 enum RTL8169_registers { 113 MAC0 = 0, /* Ethernet hardware address. */ 114 MAR0 = 8, /* Multicast filter. */ 115 TxDescStartAddrLow = 0x20, 116 TxDescStartAddrHigh = 0x24, 117 TxHDescStartAddrLow = 0x28, 118 TxHDescStartAddrHigh = 0x2c, 119 FLASH = 0x30, 120 ERSR = 0x36, 121 ChipCmd = 0x37, 122 TxPoll = 0x38, 123 IntrMask = 0x3C, 124 IntrStatus = 0x3E, 125 TxConfig = 0x40, 126 RxConfig = 0x44, 127 RxMissed = 0x4C, 128 Cfg9346 = 0x50, 129 Config0 = 0x51, 130 Config1 = 0x52, 131 Config2 = 0x53, 132 Config3 = 0x54, 133 Config4 = 0x55, 134 Config5 = 0x56, 135 MultiIntr = 0x5C, 136 PHYAR = 0x60, 137 TBICSR = 0x64, 138 TBI_ANAR = 0x68, 139 TBI_LPAR = 0x6A, 140 PHYstatus = 0x6C, 141 RxMaxSize = 0xDA, 142 CPlusCmd = 0xE0, 143 RxDescStartAddrLow = 0xE4, 144 RxDescStartAddrHigh = 0xE8, 145 EarlyTxThres = 0xEC, 146 FuncEvent = 0xF0, 147 FuncEventMask = 0xF4, 148 FuncPresetState = 0xF8, 149 FuncForceEvent = 0xFC, 150 }; 151 152 enum RTL8169_register_content { 153 /*InterruptStatusBits */ 154 SYSErr = 0x8000, 155 PCSTimeout = 0x4000, 156 SWInt = 0x0100, 157 TxDescUnavail = 0x80, 158 RxFIFOOver = 0x40, 159 RxUnderrun = 0x20, 160 RxOverflow = 0x10, 161 TxErr = 0x08, 162 TxOK = 0x04, 163 RxErr = 0x02, 164 RxOK = 0x01, 165 166 /*RxStatusDesc */ 167 RxRES = 0x00200000, 168 RxCRC = 0x00080000, 169 RxRUNT = 0x00100000, 170 RxRWT = 0x00400000, 171 172 /*ChipCmdBits */ 173 CmdReset = 0x10, 174 CmdRxEnb = 0x08, 175 CmdTxEnb = 0x04, 176 RxBufEmpty = 0x01, 177 178 /*Cfg9346Bits */ 179 Cfg9346_Lock = 0x00, 180 Cfg9346_Unlock = 0xC0, 181 182 /*rx_mode_bits */ 183 AcceptErr = 0x20, 184 AcceptRunt = 0x10, 185 AcceptBroadcast = 0x08, 186 AcceptMulticast = 0x04, 187 AcceptMyPhys = 0x02, 188 AcceptAllPhys = 0x01, 189 190 /*RxConfigBits */ 191 RxCfgFIFOShift = 13, 192 RxCfgDMAShift = 8, 193 194 /*TxConfigBits */ 195 TxInterFrameGapShift = 24, 196 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 197 198 /*rtl8169_PHYstatus */ 199 TBI_Enable = 0x80, 200 TxFlowCtrl = 0x40, 201 RxFlowCtrl = 0x20, 202 _1000bpsF = 0x10, 203 _100bps = 0x08, 204 _10bps = 0x04, 205 LinkStatus = 0x02, 206 FullDup = 0x01, 207 208 /*GIGABIT_PHY_registers */ 209 PHY_CTRL_REG = 0, 210 PHY_STAT_REG = 1, 211 PHY_AUTO_NEGO_REG = 4, 212 PHY_1000_CTRL_REG = 9, 213 214 /*GIGABIT_PHY_REG_BIT */ 215 PHY_Restart_Auto_Nego = 0x0200, 216 PHY_Enable_Auto_Nego = 0x1000, 217 218 /* PHY_STAT_REG = 1; */ 219 PHY_Auto_Nego_Comp = 0x0020, 220 221 /* PHY_AUTO_NEGO_REG = 4; */ 222 PHY_Cap_10_Half = 0x0020, 223 PHY_Cap_10_Full = 0x0040, 224 PHY_Cap_100_Half = 0x0080, 225 PHY_Cap_100_Full = 0x0100, 226 227 /* PHY_1000_CTRL_REG = 9; */ 228 PHY_Cap_1000_Full = 0x0200, 229 230 PHY_Cap_Null = 0x0, 231 232 /*_MediaType*/ 233 _10_Half = 0x01, 234 _10_Full = 0x02, 235 _100_Half = 0x04, 236 _100_Full = 0x08, 237 _1000_Full = 0x10, 238 239 /*_TBICSRBit*/ 240 TBILinkOK = 0x02000000, 241 }; 242 243 static struct { 244 const char *name; 245 u8 version; /* depend on RTL8169 docs */ 246 u32 RxConfigMask; /* should clear the bits supported by this chip */ 247 } rtl_chip_info[] = { 248 {"RTL-8169", 0x00, 0xff7e1880,}, 249 {"RTL-8169", 0x04, 0xff7e1880,}, 250 {"RTL-8169", 0x00, 0xff7e1880,}, 251 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 252 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 253 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 254 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 255 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 256 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 257 {"RTL-8101e", 0x34, 0xff7e1880,}, 258 {"RTL-8100e", 0x32, 0xff7e1880,}, 259 }; 260 261 enum _DescStatusBit { 262 OWNbit = 0x80000000, 263 EORbit = 0x40000000, 264 FSbit = 0x20000000, 265 LSbit = 0x10000000, 266 }; 267 268 struct TxDesc { 269 u32 status; 270 u32 vlan_tag; 271 u32 buf_addr; 272 u32 buf_Haddr; 273 }; 274 275 struct RxDesc { 276 u32 status; 277 u32 vlan_tag; 278 u32 buf_addr; 279 u32 buf_Haddr; 280 }; 281 282 /* Define the TX Descriptor */ 283 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 284 /* __attribute__ ((aligned(256))); */ 285 286 /* Create a static buffer of size RX_BUF_SZ for each 287 TX Descriptor. All descriptors point to a 288 part of this buffer */ 289 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 290 291 /* Define the RX Descriptor */ 292 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 293 /* __attribute__ ((aligned(256))); */ 294 295 /* Create a static buffer of size RX_BUF_SZ for each 296 RX Descriptor All descriptors point to a 297 part of this buffer */ 298 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 299 300 struct rtl8169_private { 301 void *mmio_addr; /* memory map physical address */ 302 int chipset; 303 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 304 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 305 unsigned long dirty_tx; 306 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 307 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 308 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 309 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 310 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 311 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 312 unsigned char *Tx_skbuff[NUM_TX_DESC]; 313 } tpx; 314 315 static struct rtl8169_private *tpc; 316 317 static const u16 rtl8169_intr_mask = 318 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 319 TxOK | RxErr | RxOK; 320 static const unsigned int rtl8169_rx_config = 321 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 322 323 static struct pci_device_id supported[] = { 324 {PCI_VENDOR_ID_REALTEK, 0x8167}, 325 {PCI_VENDOR_ID_REALTEK, 0x8169}, 326 {} 327 }; 328 329 void mdio_write(int RegAddr, int value) 330 { 331 int i; 332 333 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 334 udelay(1000); 335 336 for (i = 2000; i > 0; i--) { 337 /* Check if the RTL8169 has completed writing to the specified MII register */ 338 if (!(RTL_R32(PHYAR) & 0x80000000)) { 339 break; 340 } else { 341 udelay(100); 342 } 343 } 344 } 345 346 int mdio_read(int RegAddr) 347 { 348 int i, value = -1; 349 350 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 351 udelay(1000); 352 353 for (i = 2000; i > 0; i--) { 354 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 355 if (RTL_R32(PHYAR) & 0x80000000) { 356 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 357 break; 358 } else { 359 udelay(100); 360 } 361 } 362 return value; 363 } 364 365 static int rtl8169_init_board(struct eth_device *dev) 366 { 367 int i; 368 u32 tmp; 369 370 #ifdef DEBUG_RTL8169 371 printf ("%s\n", __FUNCTION__); 372 #endif 373 ioaddr = dev->iobase; 374 375 /* Soft reset the chip. */ 376 RTL_W8(ChipCmd, CmdReset); 377 378 /* Check that the chip has finished the reset. */ 379 for (i = 1000; i > 0; i--) 380 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 381 break; 382 else 383 udelay(10); 384 385 /* identify chip attached to board */ 386 tmp = RTL_R32(TxConfig); 387 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 388 389 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 390 if (tmp == rtl_chip_info[i].version) { 391 tpc->chipset = i; 392 goto match; 393 } 394 } 395 396 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 397 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 398 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 399 tpc->chipset = 0; 400 401 match: 402 return 0; 403 } 404 405 /************************************************************************** 406 RECV - Receive a frame 407 ***************************************************************************/ 408 static int rtl_recv(struct eth_device *dev) 409 { 410 /* return true if there's an ethernet packet ready to read */ 411 /* nic->packet should contain data on return */ 412 /* nic->packetlen should contain length of data */ 413 int cur_rx; 414 int length = 0; 415 416 #ifdef DEBUG_RTL8169_RX 417 printf ("%s\n", __FUNCTION__); 418 #endif 419 ioaddr = dev->iobase; 420 421 cur_rx = tpc->cur_rx; 422 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 423 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 424 unsigned char rxdata[RX_BUF_LEN]; 425 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 426 status) & 0x00001FFF) - 4; 427 428 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 429 NetReceive(rxdata, length); 430 431 if (cur_rx == NUM_RX_DESC - 1) 432 tpc->RxDescArray[cur_rx].status = 433 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 434 else 435 tpc->RxDescArray[cur_rx].status = 436 cpu_to_le32(OWNbit + RX_BUF_SIZE); 437 tpc->RxDescArray[cur_rx].buf_addr = 438 cpu_to_le32((unsigned long)tpc->RxBufferRing[cur_rx]); 439 } else { 440 puts("Error Rx"); 441 } 442 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 443 tpc->cur_rx = cur_rx; 444 return 1; 445 446 } else { 447 ushort sts = RTL_R8(IntrStatus); 448 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 449 udelay(100); /* wait */ 450 } 451 tpc->cur_rx = cur_rx; 452 return (0); /* initially as this is called to flush the input */ 453 } 454 455 #define HZ 1000 456 /************************************************************************** 457 SEND - Transmit a frame 458 ***************************************************************************/ 459 static int rtl_send(struct eth_device *dev, volatile void *packet, int length) 460 { 461 /* send the packet to destination */ 462 463 u32 to; 464 u8 *ptxb; 465 int entry = tpc->cur_tx % NUM_TX_DESC; 466 u32 len = length; 467 int ret; 468 469 #ifdef DEBUG_RTL8169_TX 470 int stime = currticks(); 471 printf ("%s\n", __FUNCTION__); 472 printf("sending %d bytes\n", len); 473 #endif 474 475 ioaddr = dev->iobase; 476 477 /* point to the current txb incase multiple tx_rings are used */ 478 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 479 memcpy(ptxb, (char *)packet, (int)length); 480 481 while (len < ETH_ZLEN) 482 ptxb[len++] = '\0'; 483 484 tpc->TxDescArray[entry].buf_Haddr = 0; 485 tpc->TxDescArray[entry].buf_addr = cpu_to_le32((unsigned long)ptxb); 486 if (entry != (NUM_TX_DESC - 1)) { 487 tpc->TxDescArray[entry].status = 488 cpu_to_le32((OWNbit | FSbit | LSbit) | 489 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 490 } else { 491 tpc->TxDescArray[entry].status = 492 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 493 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 494 } 495 RTL_W8(TxPoll, 0x40); /* set polling bit */ 496 497 tpc->cur_tx++; 498 to = currticks() + TX_TIMEOUT; 499 while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 500 && (currticks() < to)); /* wait */ 501 502 if (currticks() >= to) { 503 #ifdef DEBUG_RTL8169_TX 504 puts ("tx timeout/error\n"); 505 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 506 #endif 507 ret = 0; 508 } else { 509 #ifdef DEBUG_RTL8169_TX 510 puts("tx done\n"); 511 #endif 512 ret = length; 513 } 514 /* Delay to make net console (nc) work properly */ 515 udelay(20); 516 return ret; 517 } 518 519 static void rtl8169_set_rx_mode(struct eth_device *dev) 520 { 521 u32 mc_filter[2]; /* Multicast hash filter */ 522 int rx_mode; 523 u32 tmp = 0; 524 525 #ifdef DEBUG_RTL8169 526 printf ("%s\n", __FUNCTION__); 527 #endif 528 529 /* IFF_ALLMULTI */ 530 /* Too many to filter perfectly -- accept all multicasts. */ 531 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 532 mc_filter[1] = mc_filter[0] = 0xffffffff; 533 534 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 535 rtl_chip_info[tpc->chipset].RxConfigMask); 536 537 RTL_W32(RxConfig, tmp); 538 RTL_W32(MAR0 + 0, mc_filter[0]); 539 RTL_W32(MAR0 + 4, mc_filter[1]); 540 } 541 542 static void rtl8169_hw_start(struct eth_device *dev) 543 { 544 u32 i; 545 546 #ifdef DEBUG_RTL8169 547 int stime = currticks(); 548 printf ("%s\n", __FUNCTION__); 549 #endif 550 551 #if 0 552 /* Soft reset the chip. */ 553 RTL_W8(ChipCmd, CmdReset); 554 555 /* Check that the chip has finished the reset. */ 556 for (i = 1000; i > 0; i--) { 557 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 558 break; 559 else 560 udelay(10); 561 } 562 #endif 563 564 RTL_W8(Cfg9346, Cfg9346_Unlock); 565 566 /* RTL-8169sb/8110sb or previous version */ 567 if (tpc->chipset <= 5) 568 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 569 570 RTL_W8(EarlyTxThres, EarlyTxThld); 571 572 /* For gigabit rtl8169 */ 573 RTL_W16(RxMaxSize, RxPacketMaxSize); 574 575 /* Set Rx Config register */ 576 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 577 rtl_chip_info[tpc->chipset].RxConfigMask); 578 RTL_W32(RxConfig, i); 579 580 /* Set DMA burst size and Interframe Gap Time */ 581 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 582 (InterFrameGap << TxInterFrameGapShift)); 583 584 585 tpc->cur_rx = 0; 586 587 RTL_W32(TxDescStartAddrLow, (unsigned long)tpc->TxDescArray); 588 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 589 RTL_W32(RxDescStartAddrLow, (unsigned long)tpc->RxDescArray); 590 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 591 592 /* RTL-8169sc/8110sc or later version */ 593 if (tpc->chipset > 5) 594 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 595 596 RTL_W8(Cfg9346, Cfg9346_Lock); 597 udelay(10); 598 599 RTL_W32(RxMissed, 0); 600 601 rtl8169_set_rx_mode(dev); 602 603 /* no early-rx interrupts */ 604 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 605 606 #ifdef DEBUG_RTL8169 607 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 608 #endif 609 } 610 611 static void rtl8169_init_ring(struct eth_device *dev) 612 { 613 int i; 614 615 #ifdef DEBUG_RTL8169 616 int stime = currticks(); 617 printf ("%s\n", __FUNCTION__); 618 #endif 619 620 tpc->cur_rx = 0; 621 tpc->cur_tx = 0; 622 tpc->dirty_tx = 0; 623 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 624 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 625 626 for (i = 0; i < NUM_TX_DESC; i++) { 627 tpc->Tx_skbuff[i] = &txb[i]; 628 } 629 630 for (i = 0; i < NUM_RX_DESC; i++) { 631 if (i == (NUM_RX_DESC - 1)) 632 tpc->RxDescArray[i].status = 633 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 634 else 635 tpc->RxDescArray[i].status = 636 cpu_to_le32(OWNbit + RX_BUF_SIZE); 637 638 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 639 tpc->RxDescArray[i].buf_addr = 640 cpu_to_le32((unsigned long)tpc->RxBufferRing[i]); 641 } 642 643 #ifdef DEBUG_RTL8169 644 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 645 #endif 646 } 647 648 /************************************************************************** 649 RESET - Finish setting up the ethernet interface 650 ***************************************************************************/ 651 static int rtl_reset(struct eth_device *dev, bd_t *bis) 652 { 653 int i; 654 655 #ifdef DEBUG_RTL8169 656 int stime = currticks(); 657 printf ("%s\n", __FUNCTION__); 658 #endif 659 660 tpc->TxDescArrays = tx_ring; 661 /* Tx Desscriptor needs 256 bytes alignment; */ 662 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 663 255) & ~255); 664 665 tpc->RxDescArrays = rx_ring; 666 /* Rx Desscriptor needs 256 bytes alignment; */ 667 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 668 255) & ~255); 669 670 rtl8169_init_ring(dev); 671 rtl8169_hw_start(dev); 672 /* Construct a perfect filter frame with the mac address as first match 673 * and broadcast for all others */ 674 for (i = 0; i < 192; i++) 675 txb[i] = 0xFF; 676 677 txb[0] = dev->enetaddr[0]; 678 txb[1] = dev->enetaddr[1]; 679 txb[2] = dev->enetaddr[2]; 680 txb[3] = dev->enetaddr[3]; 681 txb[4] = dev->enetaddr[4]; 682 txb[5] = dev->enetaddr[5]; 683 684 #ifdef DEBUG_RTL8169 685 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 686 #endif 687 return 0; 688 } 689 690 /************************************************************************** 691 HALT - Turn off ethernet interface 692 ***************************************************************************/ 693 static void rtl_halt(struct eth_device *dev) 694 { 695 int i; 696 697 #ifdef DEBUG_RTL8169 698 printf ("%s\n", __FUNCTION__); 699 #endif 700 701 ioaddr = dev->iobase; 702 703 /* Stop the chip's Tx and Rx DMA processes. */ 704 RTL_W8(ChipCmd, 0x00); 705 706 /* Disable interrupts by clearing the interrupt mask. */ 707 RTL_W16(IntrMask, 0x0000); 708 709 RTL_W32(RxMissed, 0); 710 711 tpc->TxDescArrays = NULL; 712 tpc->RxDescArrays = NULL; 713 tpc->TxDescArray = NULL; 714 tpc->RxDescArray = NULL; 715 for (i = 0; i < NUM_RX_DESC; i++) { 716 tpc->RxBufferRing[i] = NULL; 717 } 718 } 719 720 /************************************************************************** 721 INIT - Look for an adapter, this routine's visible to the outside 722 ***************************************************************************/ 723 724 #define board_found 1 725 #define valid_link 0 726 static int rtl_init(struct eth_device *dev, bd_t *bis) 727 { 728 static int board_idx = -1; 729 static int printed_version = 0; 730 int i, rc; 731 int option = -1, Cap10_100 = 0, Cap1000 = 0; 732 733 #ifdef DEBUG_RTL8169 734 printf ("%s\n", __FUNCTION__); 735 #endif 736 737 ioaddr = dev->iobase; 738 739 board_idx++; 740 741 printed_version = 1; 742 743 /* point to private storage */ 744 tpc = &tpx; 745 746 rc = rtl8169_init_board(dev); 747 if (rc) 748 return rc; 749 750 /* Get MAC address. FIXME: read EEPROM */ 751 for (i = 0; i < MAC_ADDR_LEN; i++) 752 bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); 753 754 #ifdef DEBUG_RTL8169 755 printf("chipset = %d\n", tpc->chipset); 756 printf("MAC Address"); 757 for (i = 0; i < MAC_ADDR_LEN; i++) 758 printf(":%02x", dev->enetaddr[i]); 759 putc('\n'); 760 #endif 761 762 #ifdef DEBUG_RTL8169 763 /* Print out some hardware info */ 764 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 765 #endif 766 767 /* if TBI is not endbled */ 768 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 769 int val = mdio_read(PHY_AUTO_NEGO_REG); 770 771 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 772 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 773 if (option > 0) { 774 #ifdef DEBUG_RTL8169 775 printf("%s: Force-mode Enabled.\n", dev->name); 776 #endif 777 Cap10_100 = 0, Cap1000 = 0; 778 switch (option) { 779 case _10_Half: 780 Cap10_100 = PHY_Cap_10_Half; 781 Cap1000 = PHY_Cap_Null; 782 break; 783 case _10_Full: 784 Cap10_100 = PHY_Cap_10_Full; 785 Cap1000 = PHY_Cap_Null; 786 break; 787 case _100_Half: 788 Cap10_100 = PHY_Cap_100_Half; 789 Cap1000 = PHY_Cap_Null; 790 break; 791 case _100_Full: 792 Cap10_100 = PHY_Cap_100_Full; 793 Cap1000 = PHY_Cap_Null; 794 break; 795 case _1000_Full: 796 Cap10_100 = PHY_Cap_Null; 797 Cap1000 = PHY_Cap_1000_Full; 798 break; 799 default: 800 break; 801 } 802 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 803 mdio_write(PHY_1000_CTRL_REG, Cap1000); 804 } else { 805 #ifdef DEBUG_RTL8169 806 printf("%s: Auto-negotiation Enabled.\n", 807 dev->name); 808 #endif 809 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 810 mdio_write(PHY_AUTO_NEGO_REG, 811 PHY_Cap_10_Half | PHY_Cap_10_Full | 812 PHY_Cap_100_Half | PHY_Cap_100_Full | 813 (val & 0x1F)); 814 815 /* enable 1000 Full Mode */ 816 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 817 818 } 819 820 /* Enable auto-negotiation and restart auto-nigotiation */ 821 mdio_write(PHY_CTRL_REG, 822 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 823 udelay(100); 824 825 /* wait for auto-negotiation process */ 826 for (i = 10000; i > 0; i--) { 827 /* check if auto-negotiation complete */ 828 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 829 udelay(100); 830 option = RTL_R8(PHYstatus); 831 if (option & _1000bpsF) { 832 #ifdef DEBUG_RTL8169 833 printf("%s: 1000Mbps Full-duplex operation.\n", 834 dev->name); 835 #endif 836 } else { 837 #ifdef DEBUG_RTL8169 838 printf("%s: %sMbps %s-duplex operation.\n", 839 dev->name, 840 (option & _100bps) ? "100" : 841 "10", 842 (option & FullDup) ? "Full" : 843 "Half"); 844 #endif 845 } 846 break; 847 } else { 848 udelay(100); 849 } 850 } /* end for-loop to wait for auto-negotiation process */ 851 852 } else { 853 udelay(100); 854 #ifdef DEBUG_RTL8169 855 printf 856 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 857 dev->name, 858 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 859 #endif 860 } 861 862 return 1; 863 } 864 865 int rtl8169_initialize(bd_t *bis) 866 { 867 pci_dev_t devno; 868 int card_number = 0; 869 struct eth_device *dev; 870 u32 iobase; 871 int idx=0; 872 873 while(1){ 874 /* Find RTL8169 */ 875 if ((devno = pci_find_devices(supported, idx++)) < 0) 876 break; 877 878 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 879 iobase &= ~0xf; 880 881 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 882 883 dev = (struct eth_device *)malloc(sizeof *dev); 884 885 sprintf (dev->name, "RTL8169#%d", card_number); 886 887 dev->priv = (void *) devno; 888 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 889 890 dev->init = rtl_reset; 891 dev->halt = rtl_halt; 892 dev->send = rtl_send; 893 dev->recv = rtl_recv; 894 895 eth_register (dev); 896 897 rtl_init(dev, bis); 898 899 card_number++; 900 } 901 return card_number; 902 } 903