1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <dm.h> 45 #include <errno.h> 46 #include <malloc.h> 47 #include <memalign.h> 48 #include <net.h> 49 #ifndef CONFIG_DM_ETH 50 #include <netdev.h> 51 #endif 52 #include <asm/io.h> 53 #include <pci.h> 54 55 #undef DEBUG_RTL8169 56 #undef DEBUG_RTL8169_TX 57 #undef DEBUG_RTL8169_RX 58 59 #define drv_version "v1.5" 60 #define drv_date "01-17-2004" 61 62 static unsigned long ioaddr; 63 64 /* Condensed operations for readability. */ 65 #define currticks() get_timer(0) 66 67 /* media options */ 68 #define MAX_UNITS 8 69 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 70 71 /* MAC address length*/ 72 #define MAC_ADDR_LEN 6 73 74 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 75 #define MAX_ETH_FRAME_SIZE 1536 76 77 #define TX_FIFO_THRESH 256 /* In bytes */ 78 79 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 80 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 81 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 82 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 83 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 84 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 85 86 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 87 #ifdef CONFIG_SYS_RX_ETH_BUFFER 88 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER 89 #else 90 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 91 #endif 92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 93 #define RX_BUF_LEN 8192 94 95 #define RTL_MIN_IO_SIZE 0x80 96 #define TX_TIMEOUT (6*HZ) 97 98 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 99 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg)) 100 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg)) 101 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg)) 102 #define RTL_R8(reg) readb(ioaddr + (reg)) 103 #define RTL_R16(reg) readw(ioaddr + (reg)) 104 #define RTL_R32(reg) readl(ioaddr + (reg)) 105 106 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 107 #define ETH_ALEN MAC_ADDR_LEN 108 #define ETH_ZLEN 60 109 110 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \ 111 (pci_addr_t)(unsigned long)a) 112 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \ 113 (phys_addr_t)a) 114 115 enum RTL8169_registers { 116 MAC0 = 0, /* Ethernet hardware address. */ 117 MAR0 = 8, /* Multicast filter. */ 118 TxDescStartAddrLow = 0x20, 119 TxDescStartAddrHigh = 0x24, 120 TxHDescStartAddrLow = 0x28, 121 TxHDescStartAddrHigh = 0x2c, 122 FLASH = 0x30, 123 ERSR = 0x36, 124 ChipCmd = 0x37, 125 TxPoll = 0x38, 126 IntrMask = 0x3C, 127 IntrStatus = 0x3E, 128 TxConfig = 0x40, 129 RxConfig = 0x44, 130 RxMissed = 0x4C, 131 Cfg9346 = 0x50, 132 Config0 = 0x51, 133 Config1 = 0x52, 134 Config2 = 0x53, 135 Config3 = 0x54, 136 Config4 = 0x55, 137 Config5 = 0x56, 138 MultiIntr = 0x5C, 139 PHYAR = 0x60, 140 TBICSR = 0x64, 141 TBI_ANAR = 0x68, 142 TBI_LPAR = 0x6A, 143 PHYstatus = 0x6C, 144 RxMaxSize = 0xDA, 145 CPlusCmd = 0xE0, 146 RxDescStartAddrLow = 0xE4, 147 RxDescStartAddrHigh = 0xE8, 148 EarlyTxThres = 0xEC, 149 FuncEvent = 0xF0, 150 FuncEventMask = 0xF4, 151 FuncPresetState = 0xF8, 152 FuncForceEvent = 0xFC, 153 }; 154 155 enum RTL8169_register_content { 156 /*InterruptStatusBits */ 157 SYSErr = 0x8000, 158 PCSTimeout = 0x4000, 159 SWInt = 0x0100, 160 TxDescUnavail = 0x80, 161 RxFIFOOver = 0x40, 162 RxUnderrun = 0x20, 163 RxOverflow = 0x10, 164 TxErr = 0x08, 165 TxOK = 0x04, 166 RxErr = 0x02, 167 RxOK = 0x01, 168 169 /*RxStatusDesc */ 170 RxRES = 0x00200000, 171 RxCRC = 0x00080000, 172 RxRUNT = 0x00100000, 173 RxRWT = 0x00400000, 174 175 /*ChipCmdBits */ 176 CmdReset = 0x10, 177 CmdRxEnb = 0x08, 178 CmdTxEnb = 0x04, 179 RxBufEmpty = 0x01, 180 181 /*Cfg9346Bits */ 182 Cfg9346_Lock = 0x00, 183 Cfg9346_Unlock = 0xC0, 184 185 /*rx_mode_bits */ 186 AcceptErr = 0x20, 187 AcceptRunt = 0x10, 188 AcceptBroadcast = 0x08, 189 AcceptMulticast = 0x04, 190 AcceptMyPhys = 0x02, 191 AcceptAllPhys = 0x01, 192 193 /*RxConfigBits */ 194 RxCfgFIFOShift = 13, 195 RxCfgDMAShift = 8, 196 197 /*TxConfigBits */ 198 TxInterFrameGapShift = 24, 199 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 200 201 /*rtl8169_PHYstatus */ 202 TBI_Enable = 0x80, 203 TxFlowCtrl = 0x40, 204 RxFlowCtrl = 0x20, 205 _1000bpsF = 0x10, 206 _100bps = 0x08, 207 _10bps = 0x04, 208 LinkStatus = 0x02, 209 FullDup = 0x01, 210 211 /*GIGABIT_PHY_registers */ 212 PHY_CTRL_REG = 0, 213 PHY_STAT_REG = 1, 214 PHY_AUTO_NEGO_REG = 4, 215 PHY_1000_CTRL_REG = 9, 216 217 /*GIGABIT_PHY_REG_BIT */ 218 PHY_Restart_Auto_Nego = 0x0200, 219 PHY_Enable_Auto_Nego = 0x1000, 220 221 /* PHY_STAT_REG = 1; */ 222 PHY_Auto_Nego_Comp = 0x0020, 223 224 /* PHY_AUTO_NEGO_REG = 4; */ 225 PHY_Cap_10_Half = 0x0020, 226 PHY_Cap_10_Full = 0x0040, 227 PHY_Cap_100_Half = 0x0080, 228 PHY_Cap_100_Full = 0x0100, 229 230 /* PHY_1000_CTRL_REG = 9; */ 231 PHY_Cap_1000_Full = 0x0200, 232 233 PHY_Cap_Null = 0x0, 234 235 /*_MediaType*/ 236 _10_Half = 0x01, 237 _10_Full = 0x02, 238 _100_Half = 0x04, 239 _100_Full = 0x08, 240 _1000_Full = 0x10, 241 242 /*_TBICSRBit*/ 243 TBILinkOK = 0x02000000, 244 }; 245 246 static struct { 247 const char *name; 248 u8 version; /* depend on RTL8169 docs */ 249 u32 RxConfigMask; /* should clear the bits supported by this chip */ 250 } rtl_chip_info[] = { 251 {"RTL-8169", 0x00, 0xff7e1880,}, 252 {"RTL-8169", 0x04, 0xff7e1880,}, 253 {"RTL-8169", 0x00, 0xff7e1880,}, 254 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 255 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 256 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 257 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 258 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 259 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 260 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 261 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 262 {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, 263 {"RTL-8101e", 0x34, 0xff7e1880,}, 264 {"RTL-8100e", 0x32, 0xff7e1880,}, 265 }; 266 267 enum _DescStatusBit { 268 OWNbit = 0x80000000, 269 EORbit = 0x40000000, 270 FSbit = 0x20000000, 271 LSbit = 0x10000000, 272 }; 273 274 struct TxDesc { 275 u32 status; 276 u32 vlan_tag; 277 u32 buf_addr; 278 u32 buf_Haddr; 279 }; 280 281 struct RxDesc { 282 u32 status; 283 u32 vlan_tag; 284 u32 buf_addr; 285 u32 buf_Haddr; 286 }; 287 288 static unsigned char rxdata[RX_BUF_LEN]; 289 290 #define RTL8169_DESC_SIZE 16 291 292 #if ARCH_DMA_MINALIGN > 256 293 # define RTL8169_ALIGN ARCH_DMA_MINALIGN 294 #else 295 # define RTL8169_ALIGN 256 296 #endif 297 298 /* 299 * Warn if the cache-line size is larger than the descriptor size. In such 300 * cases the driver will likely fail because the CPU needs to flush the cache 301 * when requeuing RX buffers, therefore descriptors written by the hardware 302 * may be discarded. 303 * 304 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 305 * the driver to allocate descriptors from a pool of non-cached memory. 306 */ 307 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN 308 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ 309 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) 310 #warning cache-line size is larger than descriptor size 311 #endif 312 #endif 313 314 /* 315 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All 316 * descriptors point to a part of this buffer. 317 */ 318 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 319 320 /* 321 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All 322 * descriptors point to a part of this buffer. 323 */ 324 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 325 326 struct rtl8169_private { 327 ulong iobase; 328 void *mmio_addr; /* memory map physical address */ 329 int chipset; 330 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 331 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 332 unsigned long dirty_tx; 333 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 334 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 335 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 336 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 337 unsigned char *Tx_skbuff[NUM_TX_DESC]; 338 } tpx; 339 340 static struct rtl8169_private *tpc; 341 342 static const u16 rtl8169_intr_mask = 343 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 344 TxOK | RxErr | RxOK; 345 static const unsigned int rtl8169_rx_config = 346 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 347 348 static struct pci_device_id supported[] = { 349 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, 350 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, 351 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, 352 {} 353 }; 354 355 void mdio_write(int RegAddr, int value) 356 { 357 int i; 358 359 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 360 udelay(1000); 361 362 for (i = 2000; i > 0; i--) { 363 /* Check if the RTL8169 has completed writing to the specified MII register */ 364 if (!(RTL_R32(PHYAR) & 0x80000000)) { 365 break; 366 } else { 367 udelay(100); 368 } 369 } 370 } 371 372 int mdio_read(int RegAddr) 373 { 374 int i, value = -1; 375 376 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 377 udelay(1000); 378 379 for (i = 2000; i > 0; i--) { 380 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 381 if (RTL_R32(PHYAR) & 0x80000000) { 382 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 383 break; 384 } else { 385 udelay(100); 386 } 387 } 388 return value; 389 } 390 391 static int rtl8169_init_board(unsigned long dev_iobase, const char *name) 392 { 393 int i; 394 u32 tmp; 395 396 #ifdef DEBUG_RTL8169 397 printf ("%s\n", __FUNCTION__); 398 #endif 399 ioaddr = dev_iobase; 400 401 /* Soft reset the chip. */ 402 RTL_W8(ChipCmd, CmdReset); 403 404 /* Check that the chip has finished the reset. */ 405 for (i = 1000; i > 0; i--) 406 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 407 break; 408 else 409 udelay(10); 410 411 /* identify chip attached to board */ 412 tmp = RTL_R32(TxConfig); 413 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 414 415 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 416 if (tmp == rtl_chip_info[i].version) { 417 tpc->chipset = i; 418 goto match; 419 } 420 } 421 422 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 423 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", 424 name); 425 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 426 tpc->chipset = 0; 427 428 match: 429 return 0; 430 } 431 432 /* 433 * TX and RX descriptors are 16 bytes. This causes problems with the cache 434 * maintenance on CPUs where the cache-line size exceeds the size of these 435 * descriptors. What will happen is that when the driver receives a packet 436 * it will be immediately requeued for the hardware to reuse. The CPU will 437 * therefore need to flush the cache-line containing the descriptor, which 438 * will cause all other descriptors in the same cache-line to be flushed 439 * along with it. If one of those descriptors had been written to by the 440 * device those changes (and the associated packet) will be lost. 441 * 442 * To work around this, we make use of non-cached memory if available. If 443 * descriptors are mapped uncached there's no need to manually flush them 444 * or invalidate them. 445 * 446 * Note that this only applies to descriptors. The packet data buffers do 447 * not have the same constraints since they are 1536 bytes large, so they 448 * are unlikely to share cache-lines. 449 */ 450 static void *rtl_alloc_descs(unsigned int num) 451 { 452 size_t size = num * RTL8169_DESC_SIZE; 453 454 #ifdef CONFIG_SYS_NONCACHED_MEMORY 455 return (void *)noncached_alloc(size, RTL8169_ALIGN); 456 #else 457 return memalign(RTL8169_ALIGN, size); 458 #endif 459 } 460 461 /* 462 * Cache maintenance functions. These are simple wrappers around the more 463 * general purpose flush_cache() and invalidate_dcache_range() functions. 464 */ 465 466 static void rtl_inval_rx_desc(struct RxDesc *desc) 467 { 468 #ifndef CONFIG_SYS_NONCACHED_MEMORY 469 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 470 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 471 472 invalidate_dcache_range(start, end); 473 #endif 474 } 475 476 static void rtl_flush_rx_desc(struct RxDesc *desc) 477 { 478 #ifndef CONFIG_SYS_NONCACHED_MEMORY 479 flush_cache((unsigned long)desc, sizeof(*desc)); 480 #endif 481 } 482 483 static void rtl_inval_tx_desc(struct TxDesc *desc) 484 { 485 #ifndef CONFIG_SYS_NONCACHED_MEMORY 486 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 487 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 488 489 invalidate_dcache_range(start, end); 490 #endif 491 } 492 493 static void rtl_flush_tx_desc(struct TxDesc *desc) 494 { 495 #ifndef CONFIG_SYS_NONCACHED_MEMORY 496 flush_cache((unsigned long)desc, sizeof(*desc)); 497 #endif 498 } 499 500 static void rtl_inval_buffer(void *buf, size_t size) 501 { 502 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 503 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 504 505 invalidate_dcache_range(start, end); 506 } 507 508 static void rtl_flush_buffer(void *buf, size_t size) 509 { 510 flush_cache((unsigned long)buf, size); 511 } 512 513 /************************************************************************** 514 RECV - Receive a frame 515 ***************************************************************************/ 516 static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase, 517 uchar **packetp) 518 { 519 /* return true if there's an ethernet packet ready to read */ 520 /* nic->packet should contain data on return */ 521 /* nic->packetlen should contain length of data */ 522 int cur_rx; 523 int length = 0; 524 525 #ifdef DEBUG_RTL8169_RX 526 printf ("%s\n", __FUNCTION__); 527 #endif 528 ioaddr = dev_iobase; 529 530 cur_rx = tpc->cur_rx; 531 532 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 533 534 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 535 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 536 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 537 status) & 0x00001FFF) - 4; 538 539 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 540 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 541 542 if (cur_rx == NUM_RX_DESC - 1) 543 tpc->RxDescArray[cur_rx].status = 544 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 545 else 546 tpc->RxDescArray[cur_rx].status = 547 cpu_to_le32(OWNbit + RX_BUF_SIZE); 548 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( 549 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long) 550 tpc->RxBufferRing[cur_rx])); 551 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 552 #ifdef CONFIG_DM_ETH 553 *packetp = rxdata; 554 #else 555 net_process_received_packet(rxdata, length); 556 #endif 557 } else { 558 puts("Error Rx"); 559 length = -EIO; 560 } 561 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 562 tpc->cur_rx = cur_rx; 563 return length; 564 565 } else { 566 ushort sts = RTL_R8(IntrStatus); 567 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 568 udelay(100); /* wait */ 569 } 570 tpc->cur_rx = cur_rx; 571 return (0); /* initially as this is called to flush the input */ 572 } 573 574 #ifdef CONFIG_DM_ETH 575 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) 576 { 577 struct rtl8169_private *priv = dev_get_priv(dev); 578 579 return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp); 580 } 581 #else 582 static int rtl_recv(struct eth_device *dev) 583 { 584 return rtl_recv_common((pci_dev_t)dev->priv, dev->iobase, NULL); 585 } 586 #endif /* nCONFIG_DM_ETH */ 587 588 #define HZ 1000 589 /************************************************************************** 590 SEND - Transmit a frame 591 ***************************************************************************/ 592 static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase, 593 void *packet, int length) 594 { 595 /* send the packet to destination */ 596 597 u32 to; 598 u8 *ptxb; 599 int entry = tpc->cur_tx % NUM_TX_DESC; 600 u32 len = length; 601 int ret; 602 603 #ifdef DEBUG_RTL8169_TX 604 int stime = currticks(); 605 printf ("%s\n", __FUNCTION__); 606 printf("sending %d bytes\n", len); 607 #endif 608 609 ioaddr = dev_iobase; 610 611 /* point to the current txb incase multiple tx_rings are used */ 612 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 613 memcpy(ptxb, (char *)packet, (int)length); 614 rtl_flush_buffer(ptxb, length); 615 616 while (len < ETH_ZLEN) 617 ptxb[len++] = '\0'; 618 619 tpc->TxDescArray[entry].buf_Haddr = 0; 620 tpc->TxDescArray[entry].buf_addr = cpu_to_le32( 621 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb)); 622 if (entry != (NUM_TX_DESC - 1)) { 623 tpc->TxDescArray[entry].status = 624 cpu_to_le32((OWNbit | FSbit | LSbit) | 625 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 626 } else { 627 tpc->TxDescArray[entry].status = 628 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 629 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 630 } 631 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 632 RTL_W8(TxPoll, 0x40); /* set polling bit */ 633 634 tpc->cur_tx++; 635 to = currticks() + TX_TIMEOUT; 636 do { 637 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 638 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 639 && (currticks() < to)); /* wait */ 640 641 if (currticks() >= to) { 642 #ifdef DEBUG_RTL8169_TX 643 puts("tx timeout/error\n"); 644 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 645 #endif 646 ret = 0; 647 } else { 648 #ifdef DEBUG_RTL8169_TX 649 puts("tx done\n"); 650 #endif 651 ret = length; 652 } 653 /* Delay to make net console (nc) work properly */ 654 udelay(20); 655 return ret; 656 } 657 658 #ifdef CONFIG_DM_ETH 659 int rtl8169_eth_send(struct udevice *dev, void *packet, int length) 660 { 661 struct rtl8169_private *priv = dev_get_priv(dev); 662 663 return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length); 664 } 665 666 #else 667 static int rtl_send(struct eth_device *dev, void *packet, int length) 668 { 669 return rtl_send_common((pci_dev_t)dev->priv, dev->iobase, packet, 670 length); 671 } 672 #endif 673 674 static void rtl8169_set_rx_mode(void) 675 { 676 u32 mc_filter[2]; /* Multicast hash filter */ 677 int rx_mode; 678 u32 tmp = 0; 679 680 #ifdef DEBUG_RTL8169 681 printf ("%s\n", __FUNCTION__); 682 #endif 683 684 /* IFF_ALLMULTI */ 685 /* Too many to filter perfectly -- accept all multicasts. */ 686 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 687 mc_filter[1] = mc_filter[0] = 0xffffffff; 688 689 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 690 rtl_chip_info[tpc->chipset].RxConfigMask); 691 692 RTL_W32(RxConfig, tmp); 693 RTL_W32(MAR0 + 0, mc_filter[0]); 694 RTL_W32(MAR0 + 4, mc_filter[1]); 695 } 696 697 static void rtl8169_hw_start(pci_dev_t bdf) 698 { 699 u32 i; 700 701 #ifdef DEBUG_RTL8169 702 int stime = currticks(); 703 printf ("%s\n", __FUNCTION__); 704 #endif 705 706 #if 0 707 /* Soft reset the chip. */ 708 RTL_W8(ChipCmd, CmdReset); 709 710 /* Check that the chip has finished the reset. */ 711 for (i = 1000; i > 0; i--) { 712 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 713 break; 714 else 715 udelay(10); 716 } 717 #endif 718 719 RTL_W8(Cfg9346, Cfg9346_Unlock); 720 721 /* RTL-8169sb/8110sb or previous version */ 722 if (tpc->chipset <= 5) 723 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 724 725 RTL_W8(EarlyTxThres, EarlyTxThld); 726 727 /* For gigabit rtl8169 */ 728 RTL_W16(RxMaxSize, RxPacketMaxSize); 729 730 /* Set Rx Config register */ 731 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 732 rtl_chip_info[tpc->chipset].RxConfigMask); 733 RTL_W32(RxConfig, i); 734 735 /* Set DMA burst size and Interframe Gap Time */ 736 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 737 (InterFrameGap << TxInterFrameGapShift)); 738 739 740 tpc->cur_rx = 0; 741 742 RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf, 743 (pci_addr_t)(unsigned long)tpc->TxDescArray)); 744 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 745 RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( 746 bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray)); 747 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 748 749 /* RTL-8169sc/8110sc or later version */ 750 if (tpc->chipset > 5) 751 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 752 753 RTL_W8(Cfg9346, Cfg9346_Lock); 754 udelay(10); 755 756 RTL_W32(RxMissed, 0); 757 758 rtl8169_set_rx_mode(); 759 760 /* no early-rx interrupts */ 761 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 762 763 #ifdef DEBUG_RTL8169 764 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 765 #endif 766 } 767 768 static void rtl8169_init_ring(pci_dev_t bdf) 769 { 770 int i; 771 772 #ifdef DEBUG_RTL8169 773 int stime = currticks(); 774 printf ("%s\n", __FUNCTION__); 775 #endif 776 777 tpc->cur_rx = 0; 778 tpc->cur_tx = 0; 779 tpc->dirty_tx = 0; 780 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 781 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 782 783 for (i = 0; i < NUM_TX_DESC; i++) { 784 tpc->Tx_skbuff[i] = &txb[i]; 785 } 786 787 for (i = 0; i < NUM_RX_DESC; i++) { 788 if (i == (NUM_RX_DESC - 1)) 789 tpc->RxDescArray[i].status = 790 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 791 else 792 tpc->RxDescArray[i].status = 793 cpu_to_le32(OWNbit + RX_BUF_SIZE); 794 795 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 796 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( 797 bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); 798 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 799 } 800 801 #ifdef DEBUG_RTL8169 802 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 803 #endif 804 } 805 806 static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr) 807 { 808 int i; 809 810 #ifdef DEBUG_RTL8169 811 int stime = currticks(); 812 printf ("%s\n", __FUNCTION__); 813 #endif 814 815 rtl8169_init_ring(bdf); 816 rtl8169_hw_start(bdf); 817 /* Construct a perfect filter frame with the mac address as first match 818 * and broadcast for all others */ 819 for (i = 0; i < 192; i++) 820 txb[i] = 0xFF; 821 822 txb[0] = enetaddr[0]; 823 txb[1] = enetaddr[1]; 824 txb[2] = enetaddr[2]; 825 txb[3] = enetaddr[3]; 826 txb[4] = enetaddr[4]; 827 txb[5] = enetaddr[5]; 828 829 #ifdef DEBUG_RTL8169 830 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 831 #endif 832 } 833 834 #ifdef CONFIG_DM_ETH 835 static int rtl8169_eth_start(struct udevice *dev) 836 { 837 struct eth_pdata *plat = dev_get_platdata(dev); 838 839 rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr); 840 841 return 0; 842 } 843 #else 844 /************************************************************************** 845 RESET - Finish setting up the ethernet interface 846 ***************************************************************************/ 847 static int rtl_reset(struct eth_device *dev, bd_t *bis) 848 { 849 rtl8169_common_start((pci_dev_t)dev->priv, dev->enetaddr); 850 851 return 0; 852 } 853 #endif /* nCONFIG_DM_ETH */ 854 855 static void rtl_halt_common(unsigned long dev_iobase) 856 { 857 int i; 858 859 #ifdef DEBUG_RTL8169 860 printf ("%s\n", __FUNCTION__); 861 #endif 862 863 ioaddr = dev_iobase; 864 865 /* Stop the chip's Tx and Rx DMA processes. */ 866 RTL_W8(ChipCmd, 0x00); 867 868 /* Disable interrupts by clearing the interrupt mask. */ 869 RTL_W16(IntrMask, 0x0000); 870 871 RTL_W32(RxMissed, 0); 872 873 for (i = 0; i < NUM_RX_DESC; i++) { 874 tpc->RxBufferRing[i] = NULL; 875 } 876 } 877 878 #ifdef CONFIG_DM_ETH 879 void rtl8169_eth_stop(struct udevice *dev) 880 { 881 struct rtl8169_private *priv = dev_get_priv(dev); 882 883 rtl_halt_common(priv->iobase); 884 } 885 #else 886 /************************************************************************** 887 HALT - Turn off ethernet interface 888 ***************************************************************************/ 889 static void rtl_halt(struct eth_device *dev) 890 { 891 rtl_halt_common(dev->iobase); 892 } 893 #endif 894 895 /************************************************************************** 896 INIT - Look for an adapter, this routine's visible to the outside 897 ***************************************************************************/ 898 899 #define board_found 1 900 #define valid_link 0 901 static int rtl_init(unsigned long dev_ioaddr, const char *name, 902 unsigned char *enetaddr) 903 { 904 static int board_idx = -1; 905 int i, rc; 906 int option = -1, Cap10_100 = 0, Cap1000 = 0; 907 908 #ifdef DEBUG_RTL8169 909 printf ("%s\n", __FUNCTION__); 910 #endif 911 ioaddr = dev_ioaddr; 912 913 board_idx++; 914 915 /* point to private storage */ 916 tpc = &tpx; 917 918 rc = rtl8169_init_board(ioaddr, name); 919 if (rc) 920 return rc; 921 922 /* Get MAC address. FIXME: read EEPROM */ 923 for (i = 0; i < MAC_ADDR_LEN; i++) 924 enetaddr[i] = RTL_R8(MAC0 + i); 925 926 #ifdef DEBUG_RTL8169 927 printf("chipset = %d\n", tpc->chipset); 928 printf("MAC Address"); 929 for (i = 0; i < MAC_ADDR_LEN; i++) 930 printf(":%02x", enetaddr[i]); 931 putc('\n'); 932 #endif 933 934 #ifdef DEBUG_RTL8169 935 /* Print out some hardware info */ 936 printf("%s: at ioaddr 0x%lx\n", name, ioaddr); 937 #endif 938 939 /* if TBI is not endbled */ 940 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 941 int val = mdio_read(PHY_AUTO_NEGO_REG); 942 943 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 944 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 945 if (option > 0) { 946 #ifdef DEBUG_RTL8169 947 printf("%s: Force-mode Enabled.\n", dev->name); 948 #endif 949 Cap10_100 = 0, Cap1000 = 0; 950 switch (option) { 951 case _10_Half: 952 Cap10_100 = PHY_Cap_10_Half; 953 Cap1000 = PHY_Cap_Null; 954 break; 955 case _10_Full: 956 Cap10_100 = PHY_Cap_10_Full; 957 Cap1000 = PHY_Cap_Null; 958 break; 959 case _100_Half: 960 Cap10_100 = PHY_Cap_100_Half; 961 Cap1000 = PHY_Cap_Null; 962 break; 963 case _100_Full: 964 Cap10_100 = PHY_Cap_100_Full; 965 Cap1000 = PHY_Cap_Null; 966 break; 967 case _1000_Full: 968 Cap10_100 = PHY_Cap_Null; 969 Cap1000 = PHY_Cap_1000_Full; 970 break; 971 default: 972 break; 973 } 974 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 975 mdio_write(PHY_1000_CTRL_REG, Cap1000); 976 } else { 977 #ifdef DEBUG_RTL8169 978 printf("%s: Auto-negotiation Enabled.\n", 979 dev->name); 980 #endif 981 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 982 mdio_write(PHY_AUTO_NEGO_REG, 983 PHY_Cap_10_Half | PHY_Cap_10_Full | 984 PHY_Cap_100_Half | PHY_Cap_100_Full | 985 (val & 0x1F)); 986 987 /* enable 1000 Full Mode */ 988 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 989 990 } 991 992 /* Enable auto-negotiation and restart auto-nigotiation */ 993 mdio_write(PHY_CTRL_REG, 994 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 995 udelay(100); 996 997 /* wait for auto-negotiation process */ 998 for (i = 10000; i > 0; i--) { 999 /* check if auto-negotiation complete */ 1000 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 1001 udelay(100); 1002 option = RTL_R8(PHYstatus); 1003 if (option & _1000bpsF) { 1004 #ifdef DEBUG_RTL8169 1005 printf("%s: 1000Mbps Full-duplex operation.\n", 1006 dev->name); 1007 #endif 1008 } else { 1009 #ifdef DEBUG_RTL8169 1010 printf("%s: %sMbps %s-duplex operation.\n", 1011 dev->name, 1012 (option & _100bps) ? "100" : 1013 "10", 1014 (option & FullDup) ? "Full" : 1015 "Half"); 1016 #endif 1017 } 1018 break; 1019 } else { 1020 udelay(100); 1021 } 1022 } /* end for-loop to wait for auto-negotiation process */ 1023 1024 } else { 1025 udelay(100); 1026 #ifdef DEBUG_RTL8169 1027 printf 1028 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 1029 dev->name, 1030 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 1031 #endif 1032 } 1033 1034 1035 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); 1036 if (!tpc->RxDescArray) 1037 return -ENOMEM; 1038 1039 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); 1040 if (!tpc->TxDescArray) 1041 return -ENOMEM; 1042 1043 return 0; 1044 } 1045 1046 #ifndef CONFIG_DM_ETH 1047 int rtl8169_initialize(bd_t *bis) 1048 { 1049 pci_dev_t devno; 1050 int card_number = 0; 1051 struct eth_device *dev; 1052 u32 iobase; 1053 int idx=0; 1054 1055 while(1){ 1056 unsigned int region; 1057 u16 device; 1058 int err; 1059 1060 /* Find RTL8169 */ 1061 if ((devno = pci_find_devices(supported, idx++)) < 0) 1062 break; 1063 1064 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 1065 switch (device) { 1066 case 0x8168: 1067 region = 2; 1068 break; 1069 1070 default: 1071 region = 1; 1072 break; 1073 } 1074 1075 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 1076 iobase &= ~0xf; 1077 1078 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1079 1080 dev = (struct eth_device *)malloc(sizeof *dev); 1081 if (!dev) { 1082 printf("Can not allocate memory of rtl8169\n"); 1083 break; 1084 } 1085 1086 memset(dev, 0, sizeof(*dev)); 1087 sprintf (dev->name, "RTL8169#%d", card_number); 1088 1089 dev->priv = (void *)(unsigned long)devno; 1090 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 1091 1092 dev->init = rtl_reset; 1093 dev->halt = rtl_halt; 1094 dev->send = rtl_send; 1095 dev->recv = rtl_recv; 1096 1097 err = rtl_init(dev->iobase, dev->name, dev->enetaddr); 1098 if (err < 0) { 1099 printf(pr_fmt("failed to initialize card: %d\n"), err); 1100 free(dev); 1101 continue; 1102 } 1103 1104 eth_register (dev); 1105 1106 card_number++; 1107 } 1108 return card_number; 1109 } 1110 #endif 1111 1112 #ifdef CONFIG_DM_ETH 1113 static int rtl8169_eth_probe(struct udevice *dev) 1114 { 1115 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 1116 struct rtl8169_private *priv = dev_get_priv(dev); 1117 struct eth_pdata *plat = dev_get_platdata(dev); 1118 u32 iobase; 1119 int region; 1120 int ret; 1121 1122 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1123 switch (pplat->device) { 1124 case 0x8168: 1125 region = 2; 1126 break; 1127 default: 1128 region = 1; 1129 break; 1130 } 1131 pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4, 1132 &iobase); 1133 iobase &= ~0xf; 1134 priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase); 1135 1136 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); 1137 if (ret < 0) { 1138 printf(pr_fmt("failed to initialize card: %d\n"), ret); 1139 return ret; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static const struct eth_ops rtl8169_eth_ops = { 1146 .start = rtl8169_eth_start, 1147 .send = rtl8169_eth_send, 1148 .recv = rtl8169_eth_recv, 1149 .stop = rtl8169_eth_stop, 1150 }; 1151 1152 static const struct udevice_id rtl8169_eth_ids[] = { 1153 { .compatible = "realtek,rtl8169" }, 1154 { } 1155 }; 1156 1157 U_BOOT_DRIVER(eth_rtl8169) = { 1158 .name = "eth_rtl8169", 1159 .id = UCLASS_ETH, 1160 .of_match = rtl8169_eth_ids, 1161 .probe = rtl8169_eth_probe, 1162 .ops = &rtl8169_eth_ops, 1163 .priv_auto_alloc_size = sizeof(struct rtl8169_private), 1164 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1165 }; 1166 1167 U_BOOT_PCI_DEVICE(eth_rtl8169, supported); 1168 #endif 1169