1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 28 * Portions of this code based on: 29 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 30 * for Linux kernel 2.4.x. 31 * 32 * Written 2002 ShuChen <shuchen@realtek.com.tw> 33 * See Linux Driver for full information 34 * 35 * Linux Driver Version 1.27a, 10.02.2002 36 * 37 * Thanks to: 38 * Jean Chen of RealTek Semiconductor Corp. for 39 * providing the evaluation NIC used to develop 40 * this driver. RealTek's support for Etherboot 41 * is appreciated. 42 * 43 * REVISION HISTORY: 44 * ================ 45 * 46 * v1.0 11-26-2003 timlegge Initial port of Linux driver 47 * v1.5 01-17-2004 timlegge Initial driver output cleanup 48 * 49 * Indent Options: indent -kr -i8 50 ***************************************************************************/ 51 /* 52 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 53 * Modified to use le32_to_cpu and cpu_to_le32 properly 54 */ 55 #include <common.h> 56 #include <malloc.h> 57 #include <net.h> 58 #include <asm/io.h> 59 #include <pci.h> 60 61 #undef DEBUG_RTL8169 62 #undef DEBUG_RTL8169_TX 63 #undef DEBUG_RTL8169_RX 64 65 #define drv_version "v1.5" 66 #define drv_date "01-17-2004" 67 68 static u32 ioaddr; 69 70 /* Condensed operations for readability. */ 71 #define currticks() get_timer(0) 72 73 /* media options */ 74 #define MAX_UNITS 8 75 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 76 77 /* MAC address length*/ 78 #define MAC_ADDR_LEN 6 79 80 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 81 #define MAX_ETH_FRAME_SIZE 1536 82 83 #define TX_FIFO_THRESH 256 /* In bytes */ 84 85 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 86 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 87 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 88 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 89 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 90 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 91 92 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 93 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 94 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 95 #define RX_BUF_LEN 8192 96 97 #define RTL_MIN_IO_SIZE 0x80 98 #define TX_TIMEOUT (6*HZ) 99 100 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 101 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 102 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 103 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 104 #define RTL_R8(reg) readb (ioaddr + (reg)) 105 #define RTL_R16(reg) readw (ioaddr + (reg)) 106 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 107 108 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 109 #define ETH_ALEN MAC_ADDR_LEN 110 #define ETH_ZLEN 60 111 112 enum RTL8169_registers { 113 MAC0 = 0, /* Ethernet hardware address. */ 114 MAR0 = 8, /* Multicast filter. */ 115 TxDescStartAddr = 0x20, 116 TxHDescStartAddr = 0x28, 117 FLASH = 0x30, 118 ERSR = 0x36, 119 ChipCmd = 0x37, 120 TxPoll = 0x38, 121 IntrMask = 0x3C, 122 IntrStatus = 0x3E, 123 TxConfig = 0x40, 124 RxConfig = 0x44, 125 RxMissed = 0x4C, 126 Cfg9346 = 0x50, 127 Config0 = 0x51, 128 Config1 = 0x52, 129 Config2 = 0x53, 130 Config3 = 0x54, 131 Config4 = 0x55, 132 Config5 = 0x56, 133 MultiIntr = 0x5C, 134 PHYAR = 0x60, 135 TBICSR = 0x64, 136 TBI_ANAR = 0x68, 137 TBI_LPAR = 0x6A, 138 PHYstatus = 0x6C, 139 RxMaxSize = 0xDA, 140 CPlusCmd = 0xE0, 141 RxDescStartAddr = 0xE4, 142 EarlyTxThres = 0xEC, 143 FuncEvent = 0xF0, 144 FuncEventMask = 0xF4, 145 FuncPresetState = 0xF8, 146 FuncForceEvent = 0xFC, 147 }; 148 149 enum RTL8169_register_content { 150 /*InterruptStatusBits */ 151 SYSErr = 0x8000, 152 PCSTimeout = 0x4000, 153 SWInt = 0x0100, 154 TxDescUnavail = 0x80, 155 RxFIFOOver = 0x40, 156 RxUnderrun = 0x20, 157 RxOverflow = 0x10, 158 TxErr = 0x08, 159 TxOK = 0x04, 160 RxErr = 0x02, 161 RxOK = 0x01, 162 163 /*RxStatusDesc */ 164 RxRES = 0x00200000, 165 RxCRC = 0x00080000, 166 RxRUNT = 0x00100000, 167 RxRWT = 0x00400000, 168 169 /*ChipCmdBits */ 170 CmdReset = 0x10, 171 CmdRxEnb = 0x08, 172 CmdTxEnb = 0x04, 173 RxBufEmpty = 0x01, 174 175 /*Cfg9346Bits */ 176 Cfg9346_Lock = 0x00, 177 Cfg9346_Unlock = 0xC0, 178 179 /*rx_mode_bits */ 180 AcceptErr = 0x20, 181 AcceptRunt = 0x10, 182 AcceptBroadcast = 0x08, 183 AcceptMulticast = 0x04, 184 AcceptMyPhys = 0x02, 185 AcceptAllPhys = 0x01, 186 187 /*RxConfigBits */ 188 RxCfgFIFOShift = 13, 189 RxCfgDMAShift = 8, 190 191 /*TxConfigBits */ 192 TxInterFrameGapShift = 24, 193 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 194 195 /*rtl8169_PHYstatus */ 196 TBI_Enable = 0x80, 197 TxFlowCtrl = 0x40, 198 RxFlowCtrl = 0x20, 199 _1000bpsF = 0x10, 200 _100bps = 0x08, 201 _10bps = 0x04, 202 LinkStatus = 0x02, 203 FullDup = 0x01, 204 205 /*GIGABIT_PHY_registers */ 206 PHY_CTRL_REG = 0, 207 PHY_STAT_REG = 1, 208 PHY_AUTO_NEGO_REG = 4, 209 PHY_1000_CTRL_REG = 9, 210 211 /*GIGABIT_PHY_REG_BIT */ 212 PHY_Restart_Auto_Nego = 0x0200, 213 PHY_Enable_Auto_Nego = 0x1000, 214 215 /* PHY_STAT_REG = 1; */ 216 PHY_Auto_Nego_Comp = 0x0020, 217 218 /* PHY_AUTO_NEGO_REG = 4; */ 219 PHY_Cap_10_Half = 0x0020, 220 PHY_Cap_10_Full = 0x0040, 221 PHY_Cap_100_Half = 0x0080, 222 PHY_Cap_100_Full = 0x0100, 223 224 /* PHY_1000_CTRL_REG = 9; */ 225 PHY_Cap_1000_Full = 0x0200, 226 227 PHY_Cap_Null = 0x0, 228 229 /*_MediaType*/ 230 _10_Half = 0x01, 231 _10_Full = 0x02, 232 _100_Half = 0x04, 233 _100_Full = 0x08, 234 _1000_Full = 0x10, 235 236 /*_TBICSRBit*/ 237 TBILinkOK = 0x02000000, 238 }; 239 240 static struct { 241 const char *name; 242 u8 version; /* depend on RTL8169 docs */ 243 u32 RxConfigMask; /* should clear the bits supported by this chip */ 244 } rtl_chip_info[] = { 245 {"RTL-8169", 0x00, 0xff7e1880,}, 246 {"RTL-8169", 0x04, 0xff7e1880,}, 247 {"RTL-8169", 0x00, 0xff7e1880,}, 248 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 249 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 250 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 251 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 252 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 253 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 254 {"RTL-8101e", 0x34, 0xff7e1880,}, 255 {"RTL-8100e", 0x32, 0xff7e1880,}, 256 }; 257 258 enum _DescStatusBit { 259 OWNbit = 0x80000000, 260 EORbit = 0x40000000, 261 FSbit = 0x20000000, 262 LSbit = 0x10000000, 263 }; 264 265 struct TxDesc { 266 u32 status; 267 u32 vlan_tag; 268 u32 buf_addr; 269 u32 buf_Haddr; 270 }; 271 272 struct RxDesc { 273 u32 status; 274 u32 vlan_tag; 275 u32 buf_addr; 276 u32 buf_Haddr; 277 }; 278 279 /* Define the TX Descriptor */ 280 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 281 /* __attribute__ ((aligned(256))); */ 282 283 /* Create a static buffer of size RX_BUF_SZ for each 284 TX Descriptor. All descriptors point to a 285 part of this buffer */ 286 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 287 288 /* Define the RX Descriptor */ 289 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 290 /* __attribute__ ((aligned(256))); */ 291 292 /* Create a static buffer of size RX_BUF_SZ for each 293 RX Descriptor All descriptors point to a 294 part of this buffer */ 295 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 296 297 struct rtl8169_private { 298 void *mmio_addr; /* memory map physical address */ 299 int chipset; 300 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 301 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 302 unsigned long dirty_tx; 303 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 304 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 305 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 306 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 307 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 308 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 309 unsigned char *Tx_skbuff[NUM_TX_DESC]; 310 } tpx; 311 312 static struct rtl8169_private *tpc; 313 314 static const u16 rtl8169_intr_mask = 315 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 316 TxOK | RxErr | RxOK; 317 static const unsigned int rtl8169_rx_config = 318 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 319 320 static struct pci_device_id supported[] = { 321 {PCI_VENDOR_ID_REALTEK, 0x8167}, 322 {PCI_VENDOR_ID_REALTEK, 0x8169}, 323 {} 324 }; 325 326 void mdio_write(int RegAddr, int value) 327 { 328 int i; 329 330 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 331 udelay(1000); 332 333 for (i = 2000; i > 0; i--) { 334 /* Check if the RTL8169 has completed writing to the specified MII register */ 335 if (!(RTL_R32(PHYAR) & 0x80000000)) { 336 break; 337 } else { 338 udelay(100); 339 } 340 } 341 } 342 343 int mdio_read(int RegAddr) 344 { 345 int i, value = -1; 346 347 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 348 udelay(1000); 349 350 for (i = 2000; i > 0; i--) { 351 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 352 if (RTL_R32(PHYAR) & 0x80000000) { 353 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 354 break; 355 } else { 356 udelay(100); 357 } 358 } 359 return value; 360 } 361 362 static int rtl8169_init_board(struct eth_device *dev) 363 { 364 int i; 365 u32 tmp; 366 367 #ifdef DEBUG_RTL8169 368 printf ("%s\n", __FUNCTION__); 369 #endif 370 ioaddr = dev->iobase; 371 372 /* Soft reset the chip. */ 373 RTL_W8(ChipCmd, CmdReset); 374 375 /* Check that the chip has finished the reset. */ 376 for (i = 1000; i > 0; i--) 377 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 378 break; 379 else 380 udelay(10); 381 382 /* identify chip attached to board */ 383 tmp = RTL_R32(TxConfig); 384 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 385 386 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 387 if (tmp == rtl_chip_info[i].version) { 388 tpc->chipset = i; 389 goto match; 390 } 391 } 392 393 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 394 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 395 printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); 396 tpc->chipset = 0; 397 398 match: 399 return 0; 400 } 401 402 /************************************************************************** 403 RECV - Receive a frame 404 ***************************************************************************/ 405 static int rtl_recv(struct eth_device *dev) 406 { 407 /* return true if there's an ethernet packet ready to read */ 408 /* nic->packet should contain data on return */ 409 /* nic->packetlen should contain length of data */ 410 int cur_rx; 411 int length = 0; 412 413 #ifdef DEBUG_RTL8169_RX 414 printf ("%s\n", __FUNCTION__); 415 #endif 416 ioaddr = dev->iobase; 417 418 cur_rx = tpc->cur_rx; 419 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 420 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 421 unsigned char rxdata[RX_BUF_LEN]; 422 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 423 status) & 0x00001FFF) - 4; 424 425 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 426 NetReceive(rxdata, length); 427 428 if (cur_rx == NUM_RX_DESC - 1) 429 tpc->RxDescArray[cur_rx].status = 430 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 431 else 432 tpc->RxDescArray[cur_rx].status = 433 cpu_to_le32(OWNbit + RX_BUF_SIZE); 434 tpc->RxDescArray[cur_rx].buf_addr = 435 cpu_to_le32((unsigned long)tpc->RxBufferRing[cur_rx]); 436 } else { 437 puts("Error Rx"); 438 } 439 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 440 tpc->cur_rx = cur_rx; 441 return 1; 442 443 } else { 444 ushort sts = RTL_R8(IntrStatus); 445 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 446 udelay(100); /* wait */ 447 } 448 tpc->cur_rx = cur_rx; 449 return (0); /* initially as this is called to flush the input */ 450 } 451 452 #define HZ 1000 453 /************************************************************************** 454 SEND - Transmit a frame 455 ***************************************************************************/ 456 static int rtl_send(struct eth_device *dev, volatile void *packet, int length) 457 { 458 /* send the packet to destination */ 459 460 u32 to; 461 u8 *ptxb; 462 int entry = tpc->cur_tx % NUM_TX_DESC; 463 u32 len = length; 464 int ret; 465 466 #ifdef DEBUG_RTL8169_TX 467 int stime = currticks(); 468 printf ("%s\n", __FUNCTION__); 469 printf("sending %d bytes\n", len); 470 #endif 471 472 ioaddr = dev->iobase; 473 474 /* point to the current txb incase multiple tx_rings are used */ 475 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 476 memcpy(ptxb, (char *)packet, (int)length); 477 478 while (len < ETH_ZLEN) 479 ptxb[len++] = '\0'; 480 481 tpc->TxDescArray[entry].buf_addr = cpu_to_le32((unsigned long)ptxb); 482 if (entry != (NUM_TX_DESC - 1)) { 483 tpc->TxDescArray[entry].status = 484 cpu_to_le32((OWNbit | FSbit | LSbit) | 485 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 486 } else { 487 tpc->TxDescArray[entry].status = 488 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 489 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 490 } 491 RTL_W8(TxPoll, 0x40); /* set polling bit */ 492 493 tpc->cur_tx++; 494 to = currticks() + TX_TIMEOUT; 495 while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 496 && (currticks() < to)); /* wait */ 497 498 if (currticks() >= to) { 499 #ifdef DEBUG_RTL8169_TX 500 puts ("tx timeout/error\n"); 501 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 502 #endif 503 ret = 0; 504 } else { 505 #ifdef DEBUG_RTL8169_TX 506 puts("tx done\n"); 507 #endif 508 ret = length; 509 } 510 /* Delay to make net console (nc) work properly */ 511 udelay(20); 512 return ret; 513 } 514 515 static void rtl8169_set_rx_mode(struct eth_device *dev) 516 { 517 u32 mc_filter[2]; /* Multicast hash filter */ 518 int rx_mode; 519 u32 tmp = 0; 520 521 #ifdef DEBUG_RTL8169 522 printf ("%s\n", __FUNCTION__); 523 #endif 524 525 /* IFF_ALLMULTI */ 526 /* Too many to filter perfectly -- accept all multicasts. */ 527 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 528 mc_filter[1] = mc_filter[0] = 0xffffffff; 529 530 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 531 rtl_chip_info[tpc->chipset].RxConfigMask); 532 533 RTL_W32(RxConfig, tmp); 534 RTL_W32(MAR0 + 0, mc_filter[0]); 535 RTL_W32(MAR0 + 4, mc_filter[1]); 536 } 537 538 static void rtl8169_hw_start(struct eth_device *dev) 539 { 540 u32 i; 541 542 #ifdef DEBUG_RTL8169 543 int stime = currticks(); 544 printf ("%s\n", __FUNCTION__); 545 #endif 546 547 #if 0 548 /* Soft reset the chip. */ 549 RTL_W8(ChipCmd, CmdReset); 550 551 /* Check that the chip has finished the reset. */ 552 for (i = 1000; i > 0; i--) { 553 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 554 break; 555 else 556 udelay(10); 557 } 558 #endif 559 560 RTL_W8(Cfg9346, Cfg9346_Unlock); 561 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 562 RTL_W8(EarlyTxThres, EarlyTxThld); 563 564 /* For gigabit rtl8169 */ 565 RTL_W16(RxMaxSize, RxPacketMaxSize); 566 567 /* Set Rx Config register */ 568 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 569 rtl_chip_info[tpc->chipset].RxConfigMask); 570 RTL_W32(RxConfig, i); 571 572 /* Set DMA burst size and Interframe Gap Time */ 573 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 574 (InterFrameGap << TxInterFrameGapShift)); 575 576 577 tpc->cur_rx = 0; 578 579 RTL_W32(TxDescStartAddr, (unsigned long)tpc->TxDescArray); 580 RTL_W32(RxDescStartAddr, (unsigned long)tpc->RxDescArray); 581 RTL_W8(Cfg9346, Cfg9346_Lock); 582 udelay(10); 583 584 RTL_W32(RxMissed, 0); 585 586 rtl8169_set_rx_mode(dev); 587 588 /* no early-rx interrupts */ 589 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 590 591 #ifdef DEBUG_RTL8169 592 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 593 #endif 594 } 595 596 static void rtl8169_init_ring(struct eth_device *dev) 597 { 598 int i; 599 600 #ifdef DEBUG_RTL8169 601 int stime = currticks(); 602 printf ("%s\n", __FUNCTION__); 603 #endif 604 605 tpc->cur_rx = 0; 606 tpc->cur_tx = 0; 607 tpc->dirty_tx = 0; 608 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 609 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 610 611 for (i = 0; i < NUM_TX_DESC; i++) { 612 tpc->Tx_skbuff[i] = &txb[i]; 613 } 614 615 for (i = 0; i < NUM_RX_DESC; i++) { 616 if (i == (NUM_RX_DESC - 1)) 617 tpc->RxDescArray[i].status = 618 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 619 else 620 tpc->RxDescArray[i].status = 621 cpu_to_le32(OWNbit + RX_BUF_SIZE); 622 623 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 624 tpc->RxDescArray[i].buf_addr = 625 cpu_to_le32((unsigned long)tpc->RxBufferRing[i]); 626 } 627 628 #ifdef DEBUG_RTL8169 629 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 630 #endif 631 } 632 633 /************************************************************************** 634 RESET - Finish setting up the ethernet interface 635 ***************************************************************************/ 636 static int rtl_reset(struct eth_device *dev, bd_t *bis) 637 { 638 int i; 639 640 #ifdef DEBUG_RTL8169 641 int stime = currticks(); 642 printf ("%s\n", __FUNCTION__); 643 #endif 644 645 tpc->TxDescArrays = tx_ring; 646 /* Tx Desscriptor needs 256 bytes alignment; */ 647 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 648 255) & ~255); 649 650 tpc->RxDescArrays = rx_ring; 651 /* Rx Desscriptor needs 256 bytes alignment; */ 652 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 653 255) & ~255); 654 655 rtl8169_init_ring(dev); 656 rtl8169_hw_start(dev); 657 /* Construct a perfect filter frame with the mac address as first match 658 * and broadcast for all others */ 659 for (i = 0; i < 192; i++) 660 txb[i] = 0xFF; 661 662 txb[0] = dev->enetaddr[0]; 663 txb[1] = dev->enetaddr[1]; 664 txb[2] = dev->enetaddr[2]; 665 txb[3] = dev->enetaddr[3]; 666 txb[4] = dev->enetaddr[4]; 667 txb[5] = dev->enetaddr[5]; 668 669 #ifdef DEBUG_RTL8169 670 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 671 #endif 672 return 0; 673 } 674 675 /************************************************************************** 676 HALT - Turn off ethernet interface 677 ***************************************************************************/ 678 static void rtl_halt(struct eth_device *dev) 679 { 680 int i; 681 682 #ifdef DEBUG_RTL8169 683 printf ("%s\n", __FUNCTION__); 684 #endif 685 686 ioaddr = dev->iobase; 687 688 /* Stop the chip's Tx and Rx DMA processes. */ 689 RTL_W8(ChipCmd, 0x00); 690 691 /* Disable interrupts by clearing the interrupt mask. */ 692 RTL_W16(IntrMask, 0x0000); 693 694 RTL_W32(RxMissed, 0); 695 696 tpc->TxDescArrays = NULL; 697 tpc->RxDescArrays = NULL; 698 tpc->TxDescArray = NULL; 699 tpc->RxDescArray = NULL; 700 for (i = 0; i < NUM_RX_DESC; i++) { 701 tpc->RxBufferRing[i] = NULL; 702 } 703 } 704 705 /************************************************************************** 706 INIT - Look for an adapter, this routine's visible to the outside 707 ***************************************************************************/ 708 709 #define board_found 1 710 #define valid_link 0 711 static int rtl_init(struct eth_device *dev, bd_t *bis) 712 { 713 static int board_idx = -1; 714 static int printed_version = 0; 715 int i, rc; 716 int option = -1, Cap10_100 = 0, Cap1000 = 0; 717 718 #ifdef DEBUG_RTL8169 719 printf ("%s\n", __FUNCTION__); 720 #endif 721 722 ioaddr = dev->iobase; 723 724 board_idx++; 725 726 printed_version = 1; 727 728 /* point to private storage */ 729 tpc = &tpx; 730 731 rc = rtl8169_init_board(dev); 732 if (rc) 733 return rc; 734 735 /* Get MAC address. FIXME: read EEPROM */ 736 for (i = 0; i < MAC_ADDR_LEN; i++) 737 bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); 738 739 #ifdef DEBUG_RTL8169 740 printf("MAC Address"); 741 for (i = 0; i < MAC_ADDR_LEN; i++) 742 printf(":%02x", dev->enetaddr[i]); 743 putc('\n'); 744 #endif 745 746 #ifdef DEBUG_RTL8169 747 /* Print out some hardware info */ 748 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 749 #endif 750 751 /* if TBI is not endbled */ 752 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 753 int val = mdio_read(PHY_AUTO_NEGO_REG); 754 755 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 756 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 757 if (option > 0) { 758 #ifdef DEBUG_RTL8169 759 printf("%s: Force-mode Enabled.\n", dev->name); 760 #endif 761 Cap10_100 = 0, Cap1000 = 0; 762 switch (option) { 763 case _10_Half: 764 Cap10_100 = PHY_Cap_10_Half; 765 Cap1000 = PHY_Cap_Null; 766 break; 767 case _10_Full: 768 Cap10_100 = PHY_Cap_10_Full; 769 Cap1000 = PHY_Cap_Null; 770 break; 771 case _100_Half: 772 Cap10_100 = PHY_Cap_100_Half; 773 Cap1000 = PHY_Cap_Null; 774 break; 775 case _100_Full: 776 Cap10_100 = PHY_Cap_100_Full; 777 Cap1000 = PHY_Cap_Null; 778 break; 779 case _1000_Full: 780 Cap10_100 = PHY_Cap_Null; 781 Cap1000 = PHY_Cap_1000_Full; 782 break; 783 default: 784 break; 785 } 786 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 787 mdio_write(PHY_1000_CTRL_REG, Cap1000); 788 } else { 789 #ifdef DEBUG_RTL8169 790 printf("%s: Auto-negotiation Enabled.\n", 791 dev->name); 792 #endif 793 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 794 mdio_write(PHY_AUTO_NEGO_REG, 795 PHY_Cap_10_Half | PHY_Cap_10_Full | 796 PHY_Cap_100_Half | PHY_Cap_100_Full | 797 (val & 0x1F)); 798 799 /* enable 1000 Full Mode */ 800 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 801 802 } 803 804 /* Enable auto-negotiation and restart auto-nigotiation */ 805 mdio_write(PHY_CTRL_REG, 806 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 807 udelay(100); 808 809 /* wait for auto-negotiation process */ 810 for (i = 10000; i > 0; i--) { 811 /* check if auto-negotiation complete */ 812 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 813 udelay(100); 814 option = RTL_R8(PHYstatus); 815 if (option & _1000bpsF) { 816 #ifdef DEBUG_RTL8169 817 printf("%s: 1000Mbps Full-duplex operation.\n", 818 dev->name); 819 #endif 820 } else { 821 #ifdef DEBUG_RTL8169 822 printf("%s: %sMbps %s-duplex operation.\n", 823 dev->name, 824 (option & _100bps) ? "100" : 825 "10", 826 (option & FullDup) ? "Full" : 827 "Half"); 828 #endif 829 } 830 break; 831 } else { 832 udelay(100); 833 } 834 } /* end for-loop to wait for auto-negotiation process */ 835 836 } else { 837 udelay(100); 838 #ifdef DEBUG_RTL8169 839 printf 840 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 841 dev->name, 842 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 843 #endif 844 } 845 846 return 1; 847 } 848 849 int rtl8169_initialize(bd_t *bis) 850 { 851 pci_dev_t devno; 852 int card_number = 0; 853 struct eth_device *dev; 854 u32 iobase; 855 int idx=0; 856 857 while(1){ 858 /* Find RTL8169 */ 859 if ((devno = pci_find_devices(supported, idx++)) < 0) 860 break; 861 862 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 863 iobase &= ~0xf; 864 865 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 866 867 dev = (struct eth_device *)malloc(sizeof *dev); 868 869 sprintf (dev->name, "RTL8169#%d", card_number); 870 871 dev->priv = (void *) devno; 872 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 873 874 dev->init = rtl_reset; 875 dev->halt = rtl_halt; 876 dev->send = rtl_send; 877 dev->recv = rtl_recv; 878 879 eth_register (dev); 880 881 rtl_init(dev, bis); 882 883 card_number++; 884 } 885 return card_number; 886 } 887