1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 28 * Portions of this code based on: 29 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 30 * for Linux kernel 2.4.x. 31 * 32 * Written 2002 ShuChen <shuchen@realtek.com.tw> 33 * See Linux Driver for full information 34 * 35 * Linux Driver Version 1.27a, 10.02.2002 36 * 37 * Thanks to: 38 * Jean Chen of RealTek Semiconductor Corp. for 39 * providing the evaluation NIC used to develop 40 * this driver. RealTek's support for Etherboot 41 * is appreciated. 42 * 43 * REVISION HISTORY: 44 * ================ 45 * 46 * v1.0 11-26-2003 timlegge Initial port of Linux driver 47 * v1.5 01-17-2004 timlegge Initial driver output cleanup 48 * 49 * Indent Options: indent -kr -i8 50 ***************************************************************************/ 51 52 #include <common.h> 53 #include <malloc.h> 54 #include <net.h> 55 #include <asm/io.h> 56 #include <pci.h> 57 58 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ 59 defined(CONFIG_RTL8169) 60 61 #undef DEBUG_RTL8169 62 #undef DEBUG_RTL8169_TX 63 #undef DEBUG_RTL8169_RX 64 65 #define drv_version "v1.5" 66 #define drv_date "01-17-2004" 67 68 static u32 ioaddr; 69 70 /* Condensed operations for readability. */ 71 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) 72 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) 73 74 #define currticks() get_timer(0) 75 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 76 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 77 78 /* media options */ 79 #define MAX_UNITS 8 80 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 81 82 /* MAC address length*/ 83 #define MAC_ADDR_LEN 6 84 85 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 86 #define MAX_ETH_FRAME_SIZE 1536 87 88 #define TX_FIFO_THRESH 256 /* In bytes */ 89 90 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 91 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 92 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 93 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 94 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 95 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 96 97 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 98 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 99 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 100 #define RX_BUF_LEN 8192 101 102 #define RTL_MIN_IO_SIZE 0x80 103 #define TX_TIMEOUT (6*HZ) 104 105 /* write/read MMIO register */ 106 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 107 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 108 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 109 #define RTL_R8(reg) readb (ioaddr + (reg)) 110 #define RTL_R16(reg) readw (ioaddr + (reg)) 111 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 112 113 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 114 #define ETH_ALEN MAC_ADDR_LEN 115 #define ETH_ZLEN 60 116 117 enum RTL8169_registers { 118 MAC0 = 0, /* Ethernet hardware address. */ 119 MAR0 = 8, /* Multicast filter. */ 120 TxDescStartAddr = 0x20, 121 TxHDescStartAddr = 0x28, 122 FLASH = 0x30, 123 ERSR = 0x36, 124 ChipCmd = 0x37, 125 TxPoll = 0x38, 126 IntrMask = 0x3C, 127 IntrStatus = 0x3E, 128 TxConfig = 0x40, 129 RxConfig = 0x44, 130 RxMissed = 0x4C, 131 Cfg9346 = 0x50, 132 Config0 = 0x51, 133 Config1 = 0x52, 134 Config2 = 0x53, 135 Config3 = 0x54, 136 Config4 = 0x55, 137 Config5 = 0x56, 138 MultiIntr = 0x5C, 139 PHYAR = 0x60, 140 TBICSR = 0x64, 141 TBI_ANAR = 0x68, 142 TBI_LPAR = 0x6A, 143 PHYstatus = 0x6C, 144 RxMaxSize = 0xDA, 145 CPlusCmd = 0xE0, 146 RxDescStartAddr = 0xE4, 147 EarlyTxThres = 0xEC, 148 FuncEvent = 0xF0, 149 FuncEventMask = 0xF4, 150 FuncPresetState = 0xF8, 151 FuncForceEvent = 0xFC, 152 }; 153 154 enum RTL8169_register_content { 155 /*InterruptStatusBits */ 156 SYSErr = 0x8000, 157 PCSTimeout = 0x4000, 158 SWInt = 0x0100, 159 TxDescUnavail = 0x80, 160 RxFIFOOver = 0x40, 161 RxUnderrun = 0x20, 162 RxOverflow = 0x10, 163 TxErr = 0x08, 164 TxOK = 0x04, 165 RxErr = 0x02, 166 RxOK = 0x01, 167 168 /*RxStatusDesc */ 169 RxRES = 0x00200000, 170 RxCRC = 0x00080000, 171 RxRUNT = 0x00100000, 172 RxRWT = 0x00400000, 173 174 /*ChipCmdBits */ 175 CmdReset = 0x10, 176 CmdRxEnb = 0x08, 177 CmdTxEnb = 0x04, 178 RxBufEmpty = 0x01, 179 180 /*Cfg9346Bits */ 181 Cfg9346_Lock = 0x00, 182 Cfg9346_Unlock = 0xC0, 183 184 /*rx_mode_bits */ 185 AcceptErr = 0x20, 186 AcceptRunt = 0x10, 187 AcceptBroadcast = 0x08, 188 AcceptMulticast = 0x04, 189 AcceptMyPhys = 0x02, 190 AcceptAllPhys = 0x01, 191 192 /*RxConfigBits */ 193 RxCfgFIFOShift = 13, 194 RxCfgDMAShift = 8, 195 196 /*TxConfigBits */ 197 TxInterFrameGapShift = 24, 198 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 199 200 /*rtl8169_PHYstatus */ 201 TBI_Enable = 0x80, 202 TxFlowCtrl = 0x40, 203 RxFlowCtrl = 0x20, 204 _1000bpsF = 0x10, 205 _100bps = 0x08, 206 _10bps = 0x04, 207 LinkStatus = 0x02, 208 FullDup = 0x01, 209 210 /*GIGABIT_PHY_registers */ 211 PHY_CTRL_REG = 0, 212 PHY_STAT_REG = 1, 213 PHY_AUTO_NEGO_REG = 4, 214 PHY_1000_CTRL_REG = 9, 215 216 /*GIGABIT_PHY_REG_BIT */ 217 PHY_Restart_Auto_Nego = 0x0200, 218 PHY_Enable_Auto_Nego = 0x1000, 219 220 /* PHY_STAT_REG = 1; */ 221 PHY_Auto_Neco_Comp = 0x0020, 222 223 /* PHY_AUTO_NEGO_REG = 4; */ 224 PHY_Cap_10_Half = 0x0020, 225 PHY_Cap_10_Full = 0x0040, 226 PHY_Cap_100_Half = 0x0080, 227 PHY_Cap_100_Full = 0x0100, 228 229 /* PHY_1000_CTRL_REG = 9; */ 230 PHY_Cap_1000_Full = 0x0200, 231 232 PHY_Cap_Null = 0x0, 233 234 /*_MediaType*/ 235 _10_Half = 0x01, 236 _10_Full = 0x02, 237 _100_Half = 0x04, 238 _100_Full = 0x08, 239 _1000_Full = 0x10, 240 241 /*_TBICSRBit*/ 242 TBILinkOK = 0x02000000, 243 }; 244 245 static struct { 246 const char *name; 247 u8 version; /* depend on RTL8169 docs */ 248 u32 RxConfigMask; /* should clear the bits supported by this chip */ 249 } rtl_chip_info[] = { 250 {"RTL-8169", 0x00, 0xff7e1880,}, 251 {"RTL-8169", 0x04, 0xff7e1880,}, 252 }; 253 254 enum _DescStatusBit { 255 OWNbit = 0x80000000, 256 EORbit = 0x40000000, 257 FSbit = 0x20000000, 258 LSbit = 0x10000000, 259 }; 260 261 struct TxDesc { 262 u32 status; 263 u32 vlan_tag; 264 u32 buf_addr; 265 u32 buf_Haddr; 266 }; 267 268 struct RxDesc { 269 u32 status; 270 u32 vlan_tag; 271 u32 buf_addr; 272 u32 buf_Haddr; 273 }; 274 275 /* Define the TX Descriptor */ 276 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 277 /* __attribute__ ((aligned(256))); */ 278 279 /* Create a static buffer of size RX_BUF_SZ for each 280 TX Descriptor. All descriptors point to a 281 part of this buffer */ 282 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 283 284 /* Define the RX Descriptor */ 285 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 286 /* __attribute__ ((aligned(256))); */ 287 288 /* Create a static buffer of size RX_BUF_SZ for each 289 RX Descriptor All descriptors point to a 290 part of this buffer */ 291 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 292 293 struct rtl8169_private { 294 void *mmio_addr; /* memory map physical address */ 295 int chipset; 296 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 297 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 298 unsigned long dirty_tx; 299 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 300 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 301 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 302 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 303 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 304 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 305 unsigned char *Tx_skbuff[NUM_TX_DESC]; 306 } tpx; 307 308 static struct rtl8169_private *tpc; 309 310 static const u16 rtl8169_intr_mask = 311 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 312 TxOK | RxErr | RxOK; 313 static const unsigned int rtl8169_rx_config = 314 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 315 316 static struct pci_device_id supported[] = { 317 {PCI_VENDOR_ID_REALTEK, 0x8169}, 318 {} 319 }; 320 321 void mdio_write(int RegAddr, int value) 322 { 323 int i; 324 325 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 326 udelay(1000); 327 328 for (i = 2000; i > 0; i--) { 329 /* Check if the RTL8169 has completed writing to the specified MII register */ 330 if (!(RTL_R32(PHYAR) & 0x80000000)) { 331 break; 332 } else { 333 udelay(100); 334 } 335 } 336 } 337 338 int mdio_read(int RegAddr) 339 { 340 int i, value = -1; 341 342 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 343 udelay(1000); 344 345 for (i = 2000; i > 0; i--) { 346 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 347 if (RTL_R32(PHYAR) & 0x80000000) { 348 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 349 break; 350 } else { 351 udelay(100); 352 } 353 } 354 return value; 355 } 356 357 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 358 359 static int rtl8169_init_board(struct eth_device *dev) 360 { 361 int i; 362 u32 tmp; 363 364 #ifdef DEBUG_RTL8169 365 printf ("%s\n", __FUNCTION__); 366 #endif 367 ioaddr = dev->iobase; 368 369 /* Soft reset the chip. */ 370 RTL_W8(ChipCmd, CmdReset); 371 372 /* Check that the chip has finished the reset. */ 373 for (i = 1000; i > 0; i--) 374 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 375 break; 376 else 377 udelay(10); 378 379 /* identify chip attached to board */ 380 tmp = RTL_R32(TxConfig); 381 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 382 383 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 384 if (tmp == rtl_chip_info[i].version) { 385 tpc->chipset = i; 386 goto match; 387 } 388 } 389 390 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 391 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 392 printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); 393 tpc->chipset = 0; 394 395 match: 396 return 0; 397 } 398 399 /************************************************************************** 400 RECV - Receive a frame 401 ***************************************************************************/ 402 static int rtl_recv(struct eth_device *dev) 403 { 404 /* return true if there's an ethernet packet ready to read */ 405 /* nic->packet should contain data on return */ 406 /* nic->packetlen should contain length of data */ 407 int cur_rx; 408 int length = 0; 409 410 #ifdef DEBUG_RTL8169_RX 411 printf ("%s\n", __FUNCTION__); 412 #endif 413 ioaddr = dev->iobase; 414 415 cur_rx = tpc->cur_rx; 416 if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) { 417 if (!(tpc->RxDescArray[cur_rx].status & RxRES)) { 418 unsigned char rxdata[RX_BUF_LEN]; 419 length = (int) (tpc->RxDescArray[cur_rx]. 420 status & 0x00001FFF) - 4; 421 422 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 423 NetReceive(rxdata, length); 424 425 if (cur_rx == NUM_RX_DESC - 1) 426 tpc->RxDescArray[cur_rx].status = 427 (OWNbit | EORbit) + RX_BUF_SIZE; 428 else 429 tpc->RxDescArray[cur_rx].status = 430 OWNbit + RX_BUF_SIZE; 431 tpc->RxDescArray[cur_rx].buf_addr = 432 virt_to_bus(tpc->RxBufferRing[cur_rx]); 433 } else { 434 puts("Error Rx"); 435 } 436 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 437 tpc->cur_rx = cur_rx; 438 return 1; 439 440 } 441 tpc->cur_rx = cur_rx; 442 return (0); /* initially as this is called to flush the input */ 443 } 444 445 #define HZ 1000 446 /************************************************************************** 447 SEND - Transmit a frame 448 ***************************************************************************/ 449 static int rtl_send(struct eth_device *dev, volatile void *packet, int length) 450 { 451 /* send the packet to destination */ 452 453 u32 to; 454 u8 *ptxb; 455 int entry = tpc->cur_tx % NUM_TX_DESC; 456 u32 len = length; 457 458 #ifdef DEBUG_RTL8169_TX 459 int stime = currticks(); 460 printf ("%s\n", __FUNCTION__); 461 printf("sending %d bytes\n", len); 462 #endif 463 464 ioaddr = dev->iobase; 465 466 /* point to the current txb incase multiple tx_rings are used */ 467 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 468 memcpy(ptxb, (char *)packet, (int)length); 469 470 while (len < ETH_ZLEN) 471 ptxb[len++] = '\0'; 472 473 tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb); 474 if (entry != (NUM_TX_DESC - 1)) { 475 tpc->TxDescArray[entry].status = 476 (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? 477 len : ETH_ZLEN); 478 } else { 479 tpc->TxDescArray[entry].status = 480 (OWNbit | EORbit | FSbit | LSbit) | 481 ((len > ETH_ZLEN) ? length : ETH_ZLEN); 482 } 483 RTL_W8(TxPoll, 0x40); /* set polling bit */ 484 485 tpc->cur_tx++; 486 to = currticks() + TX_TIMEOUT; 487 while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ 488 489 if (currticks() >= to) { 490 #ifdef DEBUG_RTL8169_TX 491 puts ("tx timeout/error\n"); 492 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 493 #endif 494 return 0; 495 } else { 496 #ifdef DEBUG_RTL8169_TX 497 puts("tx done\n"); 498 #endif 499 return length; 500 } 501 } 502 503 static void rtl8169_set_rx_mode(struct eth_device *dev) 504 { 505 u32 mc_filter[2]; /* Multicast hash filter */ 506 int rx_mode; 507 u32 tmp = 0; 508 509 #ifdef DEBUG_RTL8169 510 printf ("%s\n", __FUNCTION__); 511 #endif 512 513 /* IFF_ALLMULTI */ 514 /* Too many to filter perfectly -- accept all multicasts. */ 515 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 516 mc_filter[1] = mc_filter[0] = 0xffffffff; 517 518 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 519 rtl_chip_info[tpc->chipset].RxConfigMask); 520 521 RTL_W32(RxConfig, tmp); 522 RTL_W32(MAR0 + 0, mc_filter[0]); 523 RTL_W32(MAR0 + 4, mc_filter[1]); 524 } 525 526 static void rtl8169_hw_start(struct eth_device *dev) 527 { 528 u32 i; 529 530 #ifdef DEBUG_RTL8169 531 int stime = currticks(); 532 printf ("%s\n", __FUNCTION__); 533 #endif 534 535 #if 0 536 /* Soft reset the chip. */ 537 RTL_W8(ChipCmd, CmdReset); 538 539 /* Check that the chip has finished the reset. */ 540 for (i = 1000; i > 0; i--) { 541 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 542 break; 543 else 544 udelay(10); 545 } 546 #endif 547 548 RTL_W8(Cfg9346, Cfg9346_Unlock); 549 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 550 RTL_W8(EarlyTxThres, EarlyTxThld); 551 552 /* For gigabit rtl8169 */ 553 RTL_W16(RxMaxSize, RxPacketMaxSize); 554 555 /* Set Rx Config register */ 556 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 557 rtl_chip_info[tpc->chipset].RxConfigMask); 558 RTL_W32(RxConfig, i); 559 560 /* Set DMA burst size and Interframe Gap Time */ 561 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 562 (InterFrameGap << TxInterFrameGapShift)); 563 564 565 tpc->cur_rx = 0; 566 567 RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray)); 568 RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray)); 569 RTL_W8(Cfg9346, Cfg9346_Lock); 570 udelay(10); 571 572 RTL_W32(RxMissed, 0); 573 574 rtl8169_set_rx_mode(dev); 575 576 /* no early-rx interrupts */ 577 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 578 579 #ifdef DEBUG_RTL8169 580 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 581 #endif 582 } 583 584 static void rtl8169_init_ring(struct eth_device *dev) 585 { 586 int i; 587 588 #ifdef DEBUG_RTL8169 589 int stime = currticks(); 590 printf ("%s\n", __FUNCTION__); 591 #endif 592 593 tpc->cur_rx = 0; 594 tpc->cur_tx = 0; 595 tpc->dirty_tx = 0; 596 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 597 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 598 599 for (i = 0; i < NUM_TX_DESC; i++) { 600 tpc->Tx_skbuff[i] = &txb[i]; 601 } 602 603 for (i = 0; i < NUM_RX_DESC; i++) { 604 if (i == (NUM_RX_DESC - 1)) 605 tpc->RxDescArray[i].status = 606 (OWNbit | EORbit) + RX_BUF_SIZE; 607 else 608 tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE; 609 610 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 611 tpc->RxDescArray[i].buf_addr = 612 virt_to_bus(tpc->RxBufferRing[i]); 613 } 614 615 #ifdef DEBUG_RTL8169 616 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 617 #endif 618 } 619 620 /************************************************************************** 621 RESET - Finish setting up the ethernet interface 622 ***************************************************************************/ 623 static void rtl_reset(struct eth_device *dev, bd_t *bis) 624 { 625 int i; 626 u8 diff; 627 u32 TxPhyAddr, RxPhyAddr; 628 629 #ifdef DEBUG_RTL8169 630 int stime = currticks(); 631 printf ("%s\n", __FUNCTION__); 632 #endif 633 634 tpc->TxDescArrays = tx_ring; 635 if (tpc->TxDescArrays == 0) 636 puts("Allot Error"); 637 /* Tx Desscriptor needs 256 bytes alignment; */ 638 TxPhyAddr = virt_to_bus(tpc->TxDescArrays); 639 diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8)); 640 TxPhyAddr += diff; 641 tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff); 642 643 tpc->RxDescArrays = rx_ring; 644 /* Rx Desscriptor needs 256 bytes alignment; */ 645 RxPhyAddr = virt_to_bus(tpc->RxDescArrays); 646 diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8)); 647 RxPhyAddr += diff; 648 tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff); 649 650 if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) { 651 puts("Allocate RxDescArray or TxDescArray failed\n"); 652 return; 653 } 654 655 rtl8169_init_ring(dev); 656 rtl8169_hw_start(dev); 657 /* Construct a perfect filter frame with the mac address as first match 658 * and broadcast for all others */ 659 for (i = 0; i < 192; i++) 660 txb[i] = 0xFF; 661 662 txb[0] = dev->enetaddr[0]; 663 txb[1] = dev->enetaddr[1]; 664 txb[2] = dev->enetaddr[2]; 665 txb[3] = dev->enetaddr[3]; 666 txb[4] = dev->enetaddr[4]; 667 txb[5] = dev->enetaddr[5]; 668 669 #ifdef DEBUG_RTL8169 670 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 671 #endif 672 } 673 674 /************************************************************************** 675 HALT - Turn off ethernet interface 676 ***************************************************************************/ 677 static void rtl_halt(struct eth_device *dev) 678 { 679 int i; 680 681 #ifdef DEBUG_RTL8169 682 printf ("%s\n", __FUNCTION__); 683 #endif 684 685 ioaddr = dev->iobase; 686 687 /* Stop the chip's Tx and Rx DMA processes. */ 688 RTL_W8(ChipCmd, 0x00); 689 690 /* Disable interrupts by clearing the interrupt mask. */ 691 RTL_W16(IntrMask, 0x0000); 692 693 RTL_W32(RxMissed, 0); 694 695 tpc->TxDescArrays = NULL; 696 tpc->RxDescArrays = NULL; 697 tpc->TxDescArray = NULL; 698 tpc->RxDescArray = NULL; 699 for (i = 0; i < NUM_RX_DESC; i++) { 700 tpc->RxBufferRing[i] = NULL; 701 } 702 } 703 704 /************************************************************************** 705 INIT - Look for an adapter, this routine's visible to the outside 706 ***************************************************************************/ 707 708 #define board_found 1 709 #define valid_link 0 710 static int rtl_init(struct eth_device *dev, bd_t *bis) 711 { 712 static int board_idx = -1; 713 static int printed_version = 0; 714 int i, rc; 715 int option = -1, Cap10_100 = 0, Cap1000 = 0; 716 717 #ifdef DEBUG_RTL8169 718 printf ("%s\n", __FUNCTION__); 719 #endif 720 721 ioaddr = dev->iobase; 722 723 board_idx++; 724 725 printed_version = 1; 726 727 /* point to private storage */ 728 tpc = &tpx; 729 730 rc = rtl8169_init_board(dev); 731 if (rc) 732 return rc; 733 734 /* Get MAC address. FIXME: read EEPROM */ 735 for (i = 0; i < MAC_ADDR_LEN; i++) 736 dev->enetaddr[i] = RTL_R8(MAC0 + i); 737 738 #ifdef DEBUG_RTL8169 739 printf("MAC Address"); 740 for (i = 0; i < MAC_ADDR_LEN; i++) 741 printf(":%02x", dev->enetaddr[i]); 742 putc('\n'); 743 #endif 744 745 #ifdef DEBUG_RTL8169 746 /* Print out some hardware info */ 747 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 748 #endif 749 750 /* if TBI is not endbled */ 751 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 752 int val = mdio_read(PHY_AUTO_NEGO_REG); 753 754 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 755 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 756 if (option > 0) { 757 #ifdef DEBUG_RTL8169 758 printf("%s: Force-mode Enabled.\n", dev->name); 759 #endif 760 Cap10_100 = 0, Cap1000 = 0; 761 switch (option) { 762 case _10_Half: 763 Cap10_100 = PHY_Cap_10_Half; 764 Cap1000 = PHY_Cap_Null; 765 break; 766 case _10_Full: 767 Cap10_100 = PHY_Cap_10_Full; 768 Cap1000 = PHY_Cap_Null; 769 break; 770 case _100_Half: 771 Cap10_100 = PHY_Cap_100_Half; 772 Cap1000 = PHY_Cap_Null; 773 break; 774 case _100_Full: 775 Cap10_100 = PHY_Cap_100_Full; 776 Cap1000 = PHY_Cap_Null; 777 break; 778 case _1000_Full: 779 Cap10_100 = PHY_Cap_Null; 780 Cap1000 = PHY_Cap_1000_Full; 781 break; 782 default: 783 break; 784 } 785 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 786 mdio_write(PHY_1000_CTRL_REG, Cap1000); 787 } else { 788 #ifdef DEBUG_RTL8169 789 printf("%s: Auto-negotiation Enabled.\n", 790 dev->name); 791 #endif 792 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 793 mdio_write(PHY_AUTO_NEGO_REG, 794 PHY_Cap_10_Half | PHY_Cap_10_Full | 795 PHY_Cap_100_Half | PHY_Cap_100_Full | 796 (val & 0x1F)); 797 798 /* enable 1000 Full Mode */ 799 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 800 801 } 802 803 /* Enable auto-negotiation and restart auto-nigotiation */ 804 mdio_write(PHY_CTRL_REG, 805 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 806 udelay(100); 807 808 /* wait for auto-negotiation process */ 809 for (i = 10000; i > 0; i--) { 810 /* check if auto-negotiation complete */ 811 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) { 812 udelay(100); 813 option = RTL_R8(PHYstatus); 814 if (option & _1000bpsF) { 815 #ifdef DEBUG_RTL8169 816 printf("%s: 1000Mbps Full-duplex operation.\n", 817 dev->name); 818 #endif 819 } else { 820 #ifdef DEBUG_RTL8169 821 printf 822 ("%s: %sMbps %s-duplex operation.\n", 823 dev->name, 824 (option & _100bps) ? "100" : 825 "10", 826 (option & FullDup) ? "Full" : 827 "Half"); 828 #endif 829 } 830 break; 831 } else { 832 udelay(100); 833 } 834 } /* end for-loop to wait for auto-negotiation process */ 835 836 } else { 837 udelay(100); 838 #ifdef DEBUG_RTL8169 839 printf 840 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 841 dev->name, 842 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 843 #endif 844 } 845 846 return 1; 847 } 848 849 int rtl8169_initialize(bd_t *bis) 850 { 851 pci_dev_t devno; 852 int card_number = 0; 853 struct eth_device *dev; 854 u32 iobase; 855 int idx=0; 856 857 while(1){ 858 /* Find RTL8169 */ 859 if ((devno = pci_find_devices(supported, idx++)) < 0) 860 break; 861 862 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 863 iobase &= ~0xf; 864 865 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 866 867 dev = (struct eth_device *)malloc(sizeof *dev); 868 869 sprintf (dev->name, "RTL8169#%d", card_number); 870 871 dev->priv = (void *) devno; 872 dev->iobase = (int)bus_to_phys(iobase); 873 874 dev->init = rtl_reset; 875 dev->halt = rtl_halt; 876 dev->send = rtl_send; 877 dev->recv = rtl_recv; 878 879 eth_register (dev); 880 881 rtl_init(dev, bis); 882 883 card_number++; 884 } 885 return card_number; 886 } 887 888 #endif 889